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794217b46e
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chore: Add license header to source files
Signed-off-by: Christoph Heiss <contact@christoph-heiss.at>
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2022-07-14 16:32:19 +02:00 |
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3e1147b27c
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refactor: Simplify some bool logic
Signed-off-by: Christoph Heiss <contact@christoph-heiss.at>
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2022-03-29 10:44:59 +02:00 |
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66d5327af7
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sim: Use correct pysim import
Signed-off-by: Christoph Heiss <contact@christoph-heiss.at>
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2022-03-29 10:44:36 +02:00 |
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3fd05217c2
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feat: More work; implement JAL, fix some stuff
Signed-off-by: Christoph Heiss <contact@christoph-heiss.at>
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2022-03-27 16:36:15 +02:00 |
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a5a3241688
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chore: Add license
Signed-off-by: Christoph Heiss <contact@christoph-heiss.at>
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2022-03-27 16:35:43 +02:00 |
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3fea46f4d6
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feat: Implement simple base machine with add and addi instructions
Signed-off-by: Christoph Heiss <contact@christoph-heiss.at>
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2022-03-26 23:10:43 +01:00 |
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8cbd199e1e
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feat: Add command to generate Verilog
Signed-off-by: Christoph Heiss <contact@christoph-heiss.at>
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2022-03-26 21:47:39 +01:00 |
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e5cc224fbc
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chore: Add some common development files
Signed-off-by: Christoph Heiss <contact@christoph-heiss.at>
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2022-03-26 21:24:10 +01:00 |
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0ca5b8c12e
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Initial commit
Signed-off-by: Christoph Heiss <contact@christoph-heiss.at>
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2022-03-25 14:22:53 +01:00 |
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