c8h4/teuthida
1
0
Fork 0
Code Issues Pull requests Actions Packages Projects Releases Wiki Activity
An [WIP] in-order, 5-stage RISC-V (toy) implementation in Amaranth HDL.
5 commits 1 branch 0 tags 50 KiB
Python 100%
Find a file
Christoph Heiss a5a3241688
chore: Add license 
Signed-off-by: Christoph Heiss <contact@christoph-heiss.at>
2022-03-27 16:35:43 +02:00
teuthida feat: Implement simple base machine with add and addi instructions 2022-03-26 23:10:43 +01:00
.editorconfig Initial commit 2022-03-25 14:22:53 +01:00
.gitignore feat: Add command to generate Verilog 2022-03-26 21:47:39 +01:00
LICENSE chore: Add license 2022-03-27 16:35:43 +02:00
poetry.lock Initial commit 2022-03-25 14:22:53 +01:00
pyproject.toml feat: Add command to generate Verilog 2022-03-26 21:47:39 +01:00