feat: Implement simple base machine with add and addi instructions
Signed-off-by: Christoph Heiss <contact@christoph-heiss.at>
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251
teuthida/__init__.py
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251
teuthida/__init__.py
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from amaranth import *
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from enum import IntEnum
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DEFAULT_XLEN = 64
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class AluOp(IntEnum):
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ADD = 0
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class Alu(Elaboratable):
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def __init__(self, xlen=DEFAULT_XLEN):
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# Inputs
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self.en = Signal()
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self.op = Signal(range(len(AluOp)))
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self.in1 = Signal(xlen)
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self.in2 = Signal(xlen)
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# Outputs
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self.out = Signal(xlen)
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def elaborate(self, _):
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m = Module()
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with m.If(self.en == 1):
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with m.Switch(self.op):
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with m.Case(AluOp.ADD):
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m.d.comb += self.out.eq(self.in1 + self.in2)
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return m
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class Registeregf(Elaboratable):
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def __init__(self, xlen=DEFAULT_XLEN):
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# State
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self.regs = Array([Signal(xlen)] * 30) # x1 - x31
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self.pc = Signal(xlen) # x32
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# Inputs
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self.sel1 = Signal(5)
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self.sel2 = Signal(5)
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self.wren = Signal()
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self.wrsel = Signal(5)
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self.wrval = Signal(xlen)
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# Outputs
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self.out1 = Signal(xlen)
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self.out2 = Signal(xlen)
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def elaborate(self, _):
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m = Module()
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with m.Switch(self.sel1):
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with m.Case(0):
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# TODO: Optimize away everywhere else
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m.d.comb += self.out1.eq(0)
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with m.Default():
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m.d.comb += self.out1.eq(self.regs[self.sel1 - 1])
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with m.Switch(self.sel2):
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with m.Case(0):
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m.d.comb += self.out2.eq(0)
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with m.Default():
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m.d.comb += self.out2.eq(self.regs[self.sel2 - 1])
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with m.If(self.wren == 1):
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# TODO: Eliminate need for checking for x0
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with m.If((self.wrsel > 0) & (self.wrsel < 31)):
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m.d.comb += self.regs[self.wrsel - 1].eq(self.wrval)
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return m
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class BootRom(Elaboratable):
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def __init__(self, xlen=DEFAULT_XLEN):
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# Inputs
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self.addr = Signal(xlen)
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# Outputs
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self.out = Signal(xlen)
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# State
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data = [
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0x0000_0533, # add a0, x0, x0
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0x0420_0593, # addi a1, x0, 0x42 (aka li a1, 0x42)
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0x00b5_0533, # add a0, a0, a1
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]
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self.mem = Memory(width=xlen, depth=len(data), init=data)
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def elaborate(self, _):
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m = Module()
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with m.If(self.addr[2:] < self.mem.depth):
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m.d.comb += self.out.eq(self.mem[self.addr[2:]])
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return m
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class Opcode(IntEnum):
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REG = 0b0110011 # Register-only inst
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IMM = 0b0010011 # Immediate inst
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class Funct3(IntEnum):
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IMM_ADDI = 0b000
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class Funct7(IntEnum):
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REG_ADD = 0b000_0000
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class InstructionDecoder(Elaboratable):
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def __init__(self, alu, regf, xlen=DEFAULT_XLEN):
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# Links
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self.alu = alu
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self.regf = regf
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# Inputs
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self.inst = Signal(xlen)
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# Outputs
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self.illegal = Signal()
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self.alu_en = Signal()
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self.rd = Signal(5)
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self.regwrite = Signal()
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def elaborate(self, _):
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m = Module()
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#
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# | 32 25 | 24 20 | 19 15 | 14 12 | 11 7 | 6 0 |
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# +--------------+---------+---------+--------+--------+--------------+
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# R | funct7 | rs2 | rs1 | funct3 | rd | opcode |
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# +--------------+---------+---------+--------+--------+--------------+
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# I | immediate [11:0] | rs1 | funct3 | rd | opcode |
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# +------------------------+---------+--------+--------+--------------+
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#
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#
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op = Signal(7)
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rs1 = Signal(5)
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rs2 = Signal(5)
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funct3 = Signal(3)
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funct7 = Signal(7)
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imm = Signal(12)
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m.d.comb += [
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op.eq(self.inst[:7]),
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rs1.eq(self.inst[15:20]),
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rs2.eq(self.inst[20:25]),
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funct3.eq(self.inst[12:15]),
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funct7.eq(self.inst[25:32]),
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imm.eq(self.inst[20:32]),
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self.regf.sel1.eq(rs1),
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self.alu.in1.eq(self.regf.out1),
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self.rd.eq(self.inst[7:12]),
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]
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with m.Switch(op):
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with m.Case(Opcode.REG):
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m.d.comb += self.regwrite.eq(1);
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with m.Switch(funct7):
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with m.Case(Funct7.REG_ADD): # add rd, rs1, rs2
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m.d.comb += [
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self.regf.sel2.eq(rs2),
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self.alu.in2.eq(self.regf.out2),
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self.alu.op.eq(AluOp.ADD),
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self.alu_en.eq(1),
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]
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with m.Default():
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m.d.comb += self.illegal.eq(1)
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with m.Case(Opcode.IMM):
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m.d.comb += self.regwrite.eq(1);
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with m.Switch(funct3):
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with m.Case(Funct3.IMM_ADDI):
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m.d.comb += [
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self.alu.in2.eq(imm),
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self.alu.op.eq(AluOp.ADD),
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self.alu_en.eq(1),
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]
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with m.Default():
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m.d.comb += self.illegal.eq(1)
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with m.Default():
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m.d.comb += self.illegal.eq(1)
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return m
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class PipelineStage(IntEnum):
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FETCH = 0
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DECODE = 1
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EXECUTE = 2
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MEMACCESS = 3
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REGWRITE = 4
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class Cpu(Elaboratable):
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def __init__(self, xlen=DEFAULT_XLEN):
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self.cycles = Signal(xlen)
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self.stage = Signal(range(len(PipelineStage)))
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self.halt = Signal()
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def elaborate(self, platform):
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m = Module()
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alu = m.submodules.alu = Alu()
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bootrom = m.submodules.bootrom = BootRom()
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regf = m.submodules.regf = Registeregf()
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dec = m.submodules.dec = InstructionDecoder(alu, regf)
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with m.If(self.halt == 0):
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with m.Switch(self.stage):
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with m.Case(PipelineStage.FETCH):
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m.d.sync += [
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# Reset possibly-modifiying state
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alu.en.eq(0),
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regf.wren.eq(0),
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regf.pc.eq(regf.pc + 4),
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bootrom.addr.eq(regf.pc),
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dec.inst.eq(bootrom.out),
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]
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with m.Case(PipelineStage.DECODE):
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# Fully halt in case there an illegal instruction is encountered
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m.d.sync += self.halt.eq(dec.illegal)
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with m.Case(PipelineStage.EXECUTE):
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m.d.sync += [
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alu.en.eq(dec.alu_en),
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]
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with m.Case(PipelineStage.MEMACCESS):
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m.d.sync += [
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# alu.en.eq(0),
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]
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with m.Case(PipelineStage.REGWRITE):
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with m.If(dec.regwrite):
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m.d.sync += [
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regf.wrsel.eq(dec.rd),
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regf.wrval.eq(alu.out),
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regf.wren.eq(1),
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]
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with m.If(self.stage == PipelineStage.REGWRITE):
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m.d.sync += [
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self.stage.eq(PipelineStage.FETCH),
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self.cycles.eq(self.cycles + 1),
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]
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with m.Else():
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m.d.sync += self.stage.eq(self.stage + 1)
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return m
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@ -1,13 +1,18 @@
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from amaranth import *
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from nmigen.back.pysim import Simulator, Delay, Settle
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def process():
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yield
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from . import Cpu, PipelineStage
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def start():
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m = Module()
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sim = Simulator(m)
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sim.add_clock(1e-6) # 1 MHz
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sim.add_process(process)
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cpu = Cpu()
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sim.run()
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def process():
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# Run for 10 cycles
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for _ in range(10 * len(PipelineStage)):
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yield
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sim = Simulator(cpu)
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sim.add_clock(1e-6) # 1 MHz
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sim.add_sync_process(process)
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with sim.write_vcd("teuthida.vcd", "teuthida.gtkw"):
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sim.run()
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