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An [WIP] in-order, 5-stage RISC-V (toy) implementation in Amaranth HDL.
3 commits 1 branch 0 tags 50 KiB
Python 100%
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Christoph Heiss 8cbd199e1e
feat: Add command to generate Verilog 
Signed-off-by: Christoph Heiss <contact@christoph-heiss.at>
2022-03-26 21:47:39 +01:00
teuthida feat: Add command to generate Verilog 2022-03-26 21:47:39 +01:00
.editorconfig Initial commit 2022-03-25 14:22:53 +01:00
.gitignore feat: Add command to generate Verilog 2022-03-26 21:47:39 +01:00
poetry.lock Initial commit 2022-03-25 14:22:53 +01:00
pyproject.toml feat: Add command to generate Verilog 2022-03-26 21:47:39 +01:00