An [WIP] in-order, 5-stage RISC-V (toy) implementation in Amaranth HDL.

Christoph Heiss 3fea46f4d6 feat: Implement simple base machine with add and addi instructions ... Signed-off-by: Christoph Heiss <contact@christoph-heiss.at>		2022-03-26 23:10:43 +01:00
teuthida	feat: Implement simple base machine with add and addi instructions	2022-03-26 23:10:43 +01:00
.editorconfig	Initial commit	2022-03-25 14:22:53 +01:00
.gitignore	feat: Add command to generate Verilog	2022-03-26 21:47:39 +01:00
poetry.lock	Initial commit	2022-03-25 14:22:53 +01:00
pyproject.toml	feat: Add command to generate Verilog	2022-03-26 21:47:39 +01:00