|
|
3fea46f4d6
|
feat: Implement simple base machine with add and addi instructions
Signed-off-by: Christoph Heiss <contact@christoph-heiss.at>
|
2022-03-26 23:10:43 +01:00 |
|
|
|
8cbd199e1e
|
feat: Add command to generate Verilog
Signed-off-by: Christoph Heiss <contact@christoph-heiss.at>
|
2022-03-26 21:47:39 +01:00 |
|
|
|
e5cc224fbc
|
chore: Add some common development files
Signed-off-by: Christoph Heiss <contact@christoph-heiss.at>
|
2022-03-26 21:24:10 +01:00 |
|
|
|
0ca5b8c12e
|
Initial commit
Signed-off-by: Christoph Heiss <contact@christoph-heiss.at>
|
2022-03-25 14:22:53 +01:00 |
|
