Commit graph

5402 commits

Author SHA1 Message Date
Lei Zhang
7d53fecb67 [spirv] Add more target and resource limit fields
These fields will be used to choose/influence patterns for
SPIR-V code generation.

Reviewed By: mravishankar

Differential Revision: https://reviews.llvm.org/D87106
2020-09-04 10:26:34 -04:00
Marius Brehler
4f7cdc10a8 [mlir] Refactor standalone-translate to use mlirTranslateMain()
This refactors the standalone-translate executable to use mlirTranslateMain() declared in Translation.h and further applies D87129.

Reviewed By: jpienaar

Differential Revision: https://reviews.llvm.org/D87131
2020-09-04 15:26:44 +02:00
Marius Brehler
c633842f13 [mlir] Fix includes in mlir-translate
Drops the include on InitAllDialects.h, as dialects are now initialized in the translation passes.

Differential Revision: https://reviews.llvm.org/D87129
2020-09-04 15:22:38 +02:00
Benjamin Kramer
0c2a4d3c1c [mlir][VectorOps] Simplify code. NFCI. 2020-09-04 11:10:20 +02:00
Alex Zinenko
aec9e20a3e [mlir] introduce type constraints for operands of LLVM dialect operations
Historically, the operations in the MLIR's LLVM dialect only checked that the
operand are of LLVM dialect type without more detailed constraints. This was
due to LLVM dialect types wrapping LLVM IR types and having clunky verification
methods. With the new first-class modeling, it is possible to define type
constraints similarly to other dialects and use them to enforce some
correctness rules in verifiers instead of having LLVM assert during translation
to LLVM IR. This hardening discovered several issues where MLIR was producing
LLVM dialect operations that cannot exist in LLVM IR.

Depends On D85900

Reviewed By: rriddle

Differential Revision: https://reviews.llvm.org/D85901
2020-09-04 10:01:59 +02:00
Mehdi Amini
23bcfbcc98 Add comment to describe a field member (NFC)
Address post-review comment.
2020-09-04 05:25:35 +00:00
aartbik
060c9dd1cc [mlir] [VectorOps] Improve SIMD compares with narrower indices
When allowed, use 32-bit indices rather than 64-bit indices in the
SIMD computation of masks. This runs up to 2x and 4x faster on
a number of AVX2 and AVX512 microbenchmarks.

Reviewed By: bkramer

Differential Revision: https://reviews.llvm.org/D87116
2020-09-03 21:43:38 -07:00
Lei Zhang
8d420fb3a0 [spirv][nfc] Simplify resource limit with default values
These deafult values are gotten from Vulkan required limits.

Reviewed By: hanchung

Differential Revision: https://reviews.llvm.org/D87090
2020-09-03 13:29:26 -04:00
Benjamin Kramer
dfb7b3fe02 [mlir][VectorOps] Fall back to a loop when accessing a vector from a strided memref
The scalar loop is slow but correct.

Differential Revision: https://reviews.llvm.org/D87082
2020-09-03 16:05:38 +02:00
Lei Zhang
7939b76e2a [mlir] Support default valued attribute in StructsGen
Its handling is similar to optional attributes, except for the
getter method.

Reviewed By: rsuderman

Differential Revision: https://reviews.llvm.org/D87055
2020-09-03 09:46:44 -04:00
Zhibin Li
1e21ca4d25 [spirv] Add SPIR-V GLSL extended Round op
Reviewed By: mravishankar, antiagainst

Differential Revision: https://reviews.llvm.org/D86914
2020-09-03 09:42:35 -04:00
Ling, Liyang
2860b2c14b [mlir] Add Acos, Asin, Atan, Sinh, Cosh, Pow to SPIRVGLSLOps
Reviewed By: mravishankar, antiagainst

Differential Revision: https://reviews.llvm.org/D86929
2020-09-03 09:28:34 -04:00
OCHyams
485e6db872 Revert "Adding GDB PrettyPrinter for mlir::Identifier."
This reverts commit 9e9e6e698d.

This commit is causing builds that include the 'debuginfo-tests' project to
fail.

Apple has a public bot which shows the failure:
http://green.lab.llvm.org/green/view/LLDB/job/lldb-cmake/23667/console
2020-09-03 08:28:15 +01:00
Christian Sigg
9e9e6e698d Adding GDB PrettyPrinter for mlir::Identifier.
This is the first bit from D73546. Primarily setting up the corresponding test. Will add more pretty printers in a separate revision.

Reviewed By: dblaikie

Differential Revision: https://reviews.llvm.org/D86937
2020-09-03 08:18:09 +02:00
Mehdi Amini
c0b6bc070e Decouple OpPassManager from the the MLIRContext (NFC)
This is allowing to build an OpPassManager from a StringRef instead of an
Identifier, which enables building pipelines without an MLIRContext.
An identifier is still cached on-demand on the OpPassManager for efficiency
during the IR traversal.
2020-09-03 06:02:05 +00:00
Jakub Lichman
8d35080ebb [mlir][Linalg] Wrong tile size for convolutions fixed
Sizes of tiles (subviews) are bigger by 1 than they should. Let's consider
1D convolution without batches or channels. Furthermore let m iterate over
the output and n over the kernel then input is accessed with m + n. In tiling
subview sizes for convolutions are computed by applying requested tile size
together with kernel size to the above mentioned expression thus let's say
for tile size of 2 the subview size is 2 + size(n), which is bigger by one
than it should since we move kernel only once. The problem behind it is that
range is not turned into closed interval before the composition. This commit
fixes the problem by turning ranges first into closed intervals by substracting
1 and after the composition back to half open by adding 1.

Differential Revision: https://reviews.llvm.org/D86638
2020-09-03 06:01:21 +00:00
Artur Bialas
d9b4245f56 [mlir][spirv] Add block read and write from SPV_INTEL_subgroups
Added support to OpSubgroupBlockReadINTEL and OpSubgroupBlockWriteINTEL

Differential Revision: https://reviews.llvm.org/D86876
2020-09-02 20:06:59 -07:00
Mehdi Amini
6478caa034 Tweak mlir-linalg-ods-gen library dependency: only MLIRIR is needed, not the entire parser (NFC) 2020-09-02 23:58:32 +00:00
Diego Caballero
46781630a3 [MLIR][Affine][VectorOps] Vectorize uniform values in SuperVectorizer
This patch adds basic support for vectorization of uniform values to SuperVectorizer.
For now, only invariant values to the target vector loops are considered uniform. This
enables the vectorization of loops that use function arguments and external definitions
to the vector loops. We could extend uniform support in the future if we implement some
kind of divergence analysis algorithm.

Reviewed By: nicolasvasilache, aartbik

Differential Revision: https://reviews.llvm.org/D86756
2020-09-03 01:17:06 +03:00
Mehdi Amini
1284dc34ab Use an Identifier instead of an OperationName internally for OpPassManager identification (NFC)
This allows to defers the check for traits to the execution instead of forcing it on the pipeline creation.
In particular, this is making our pipeline creation tolerant to dialects not being loaded in the context yet.

Reviewed By: rriddle, GMNGeoffrey

Differential Revision: https://reviews.llvm.org/D86915
2020-09-02 21:46:05 +00:00
Diego Caballero
553bfc8fa1 [mlir][Affine] Support affine vector loads/stores in LICM
Make use of affine memory op interfaces in AffineLoopInvariantCodeMotion so
that it can also work on affine.vector_load and affine.vector_store ops.

Reviewed By: bondhugula

Differential Revision: https://reviews.llvm.org/D86986
2020-09-03 00:43:24 +03:00
Diego Caballero
65f20ea113 [mlir][Affine] Fix AffineLoopInvariantCodeMotion
Make sure that memory ops that are defined inside the loop are registered
as such in 'defineOp'. In the test provided, the 'mulf' op was hoisted
outside the loop nest even when its 'affine.load' operand was not.

Reviewed By: bondhugula

Differential Revision: https://reviews.llvm.org/D86982
2020-09-03 00:06:41 +03:00
Mehdi Amini
01700c45eb Store an Identifier instead of a StringRef for the OperationName inside an AbstractOperation (NFC)
Instead of storing a StringRef, we keep an Identifier which otherwise requires a lock on the context to retrieve.
This will allow to get an Identifier for any registered Operation for "free".

Reviewed By: rriddle

Differential Revision: https://reviews.llvm.org/D86994
2020-09-02 19:10:56 +00:00
Ehsan Toosi
39cf83cc78 [mlir] Extend BufferAssignmentTypeConverter with result conversion callbacks
In this PR, the users of BufferPlacement can configure
BufferAssginmentTypeConverter. These new configurations would give the user more
freedom in the process of converting function signature, and return and call
operation conversions.

These are the new features:
    - Accepting callback functions for decomposing types (i.e. 1 to N type
    conversion such as unpacking tuple types).
    - Defining ResultConversionKind for specifying whether a function result
    with a certain type should be appended to the function arguments list or
    should be kept as function result. (Usage:
    converter.setResultConversionKind<MemRefType>(AppendToArgumentList))
    - Accepting callback functions for composing or decomposing values (i.e. N
    to 1 and 1 to N value conversion).

Differential Revision: https://reviews.llvm.org/D85133
2020-09-02 17:53:42 +02:00
Lei Zhang
1b88bbf5eb Revert "[mlir] Extend BufferAssignmentTypeConverter with result conversion callbacks"
This reverts commit 94f5d24877 because
of failing the following tests:

MLIR :: Dialect/Linalg/tensors-to-buffers.mlir
MLIR :: Transforms/buffer-placement-preparation-allowed-memref-results.mlir
MLIR :: Transforms/buffer-placement-preparation.mlir
2020-09-02 09:24:36 -04:00
Jakub Lichman
f5ed22f09d [mlir][VectorToSCF] 128 byte alignment of alloc ops
Added 128 byte alignment to alloc ops created in VectorToSCF pass.
128b alignment was already introduced to this pass but not to all alloc
ops. This commit changes that by adding 128b alignment to the remaining ops.
The point of specifying alignment is to prevent possible memory alignment errors
on weakly tested architectures.

Differential Revision: https://reviews.llvm.org/D86454
2020-09-02 12:37:35 +00:00
Ehsan Toosi
94f5d24877 [mlir] Extend BufferAssignmentTypeConverter with result conversion callbacks
In this PR, the users of BufferPlacement can configure
BufferAssginmentTypeConverter. These new configurations would give the user more
freedom in the process of converting function signature, and return and call
operation conversions.

These are the new features:
    - Accepting callback functions for decomposing types (i.e. 1 to N type
    conversion such as unpacking tuple types).
    - Defining ResultConversionKind for specifying whether a function result
    with a certain type should be appended to the function arguments list or
    should be kept as function result. (Usage:
    converter.setResultConversionKind<MemRefType>(AppendToArgumentList))
    - Accepting callback functions for composing or decomposing values (i.e. N
    to 1 and 1 to N value conversion).

Differential Revision: https://reviews.llvm.org/D85133
2020-09-02 13:26:55 +02:00
Benjamin Kramer
2bf491c729 [mlir][VectorOps] Fail fast when a strided memref is passed to vector_transfer
Otherwise we'll silently miscompile things.

Differential Revision: https://reviews.llvm.org/D86951
2020-09-02 10:34:36 +02:00
ZHANG Hongbin
1d99472875 [mlir] Add Complex Type, Vector Type and Tuple Type subclasses to python bindings
Based on the PyType and PyConcreteType classes, this patch implements the bindings of Complex Type, Vector Type and Tuple Type subclasses.
For the convenience of type checking, this patch defines a `mlirTypeIsAIntegerOrFloat` function to check whether the given type is an integer or float type.
These three subclasses in this patch have similar binding strategy:
- The function pointer `isaFunction` points to `mlirTypeIsA***`.
- The `mlir***TypeGet` C API is bound with the `get_***` method in the python side.
- The Complex Type and Vector Type check whether the given type is an integer or float type.

Reviewed By: mehdi_amini

Differential Revision: https://reviews.llvm.org/D86785
2020-09-02 05:46:00 +00:00
Thomas Raoux
8d65504223 [mlir][vulkan-runner] Explicitly export vulkan-runtime-wrapper entry points.
This ensure that the symbols are being exported no matter what default
visibility is set.
2020-09-01 15:37:54 -07:00
River Riddle
431bb8b318 [mlir][ODS] Use c++ types for integer attributes of fixed width when possible.
Unsigned and Signless attributes use uintN_t and signed attributes use intN_t, where N is the fixed width. The 1-bit variants use bool.

Differential Revision: https://reviews.llvm.org/D86739
2020-09-01 13:43:32 -07:00
Valentin Clement
2bbbcae782 [mlir][openacc] Add missing attributes and operands for acc.loop
This patch add the missing operands to the acc.loop operation. Only the device_type
information is not part of the operation for now.

Reviewed By: rriddle, kiranchandramohan

Differential Revision: https://reviews.llvm.org/D86753
2020-08-31 19:50:05 -04:00
Mehdi Amini
f54914081f Fix mlir-reduce to explicitly register dialects and disable the global dialect registry by default
Clients who rely on the Context loading dialects from the global
registry can call `mlir::enableGlobalDialectRegistry(true);` before
creating an MLIRContext

Differential Revision: https://reviews.llvm.org/D86897
2020-08-31 22:54:58 +00:00
River Riddle
2481846a30 [mlir][PDL] Move the formats for PatternOp and RewriteOp to the declarative form.
This is possible now that the declarative assembly form supports regions.

Differential Revision: https://reviews.llvm.org/D86830
2020-08-31 13:26:24 -07:00
River Riddle
eaeadce9bd [mlir][OpFormatGen] Add initial support for regions in the custom op assembly format
This adds some initial support for regions and does not support formatting the specific arguments of a region. For now this can be achieved by using a custom directive that formats the arguments and then parses the region.

Differential Revision: https://reviews.llvm.org/D86760
2020-08-31 13:26:24 -07:00
River Riddle
24b88920fe [mlir][ODS] Add new SymbolNameAttr and add support for in assemblyFormat
Symbol names are a special form of StringAttr that get treated specially in certain areas, such as formatting. This revision adds a special derived attr for them in ODS and adds support in the assemblyFormat for formatting them properly.

Differential Revision: https://reviews.llvm.org/D86759
2020-08-31 13:26:23 -07:00
River Riddle
88c6e25e4f [mlir][OpFormatGen] Add support for specifiy "custom" directives.
This revision adds support for custom directives to the declarative assembly format. This allows for users to use C++ for printing and parsing subsections of an otherwise declaratively specified format. The custom directive is structured as follows:

```
custom-directive ::= `custom` `<` UserDirective `>` `(` Params `)`
```

`user-directive` is used as a suffix when this directive is used during printing and parsing. When parsing, `parseUserDirective` will be invoked. When printing, `printUserDirective` will be invoked. The first parameter to these methods must be a reference to either the OpAsmParser, or OpAsmPrinter. The type of rest of the parameters is dependent on the `Params` specified in the assembly format.

Differential Revision: https://reviews.llvm.org/D84719
2020-08-31 13:26:23 -07:00
Mehdi Amini
719548d63d Fix gcc warning by explicitly initializing the base class copy ctor (NFC)
Full diagnostic was:

warning: base class ‘class mlir::OptReductionBase<mlir::OptReductionPass>’ should be explicitly initialized in the copy constructor [-Wextra]
2020-08-30 17:46:51 +00:00
Kamlesh Kumar
deb99610ab Improve doc comments for several methods returning bools
Differential Revision: https://reviews.llvm.org/D86848
2020-08-30 13:33:05 +05:30
Mehdi Amini
9f2fbfab8d Use report_fatal_error instead of llvm::errs() + abort() (NFC)
This is making the error reporting in line with other fatal errors.
2020-08-29 00:36:08 +00:00
Stella Laurenzo
2d1362e09a Add Location, Region and Block to MLIR Python bindings.
* This is just enough to create regions/blocks and iterate over them.
* Does not yet implement the preferred iteration strategy (python pseudo containers).
* Refinements need to come after doing basic mappings of operations and values so that the whole hierarchy can be used.

Differential Revision: https://reviews.llvm.org/D86683
2020-08-28 15:26:05 -07:00
Mehdi Amini
c39c21610d Rename AnalysisManager::slice in AnalysisManager::nest (NFC)
The naming wasn't reflecting the intent of this API, "nest" is aligning
it with the pass manager API.
2020-08-28 20:41:07 +00:00
Benjamin Kramer
8782c72765 Strength-reduce SmallVectors to arrays. NFCI. 2020-08-28 21:14:20 +02:00
David Sherwood
d761e456ce Fix more build failures caused by f4257c5832
MLIR build failed after ElementCount refactoring - updated code to
call isScalable() and getKnownMinValue().
2020-08-28 15:08:59 +01:00
David Sherwood
4b1a55a92f Fix build failures caused by f4257c5832 2020-08-28 14:56:01 +01:00
Hanhan Wang
eb4efa8832 [mlir][Linalg] Enhance Linalg fusion on generic op and tensor_reshape op.
The tensor_reshape op was only fusible only if it is a collapsing case. Now we
propagate the op to all the operands so there is a further chance to fuse it
with generic op. The pre-conditions are:

1) The producer is not an indexed_generic op.
2) All the shapes of the operands are the same.
3) All the indexing maps are identity.
4) All the loops are parallel loops.
5) The producer has a single user.

It is possible to fuse the ops if the producer is an indexed_generic op. We
still can compute the original indices. E.g., if the reshape op collapses the d0
and d1, we can use DimOp to get the width of d1, and calculate the index
`d0 * width + d1`. Then replace all the uses with it. However, this pattern is
not implemented in the patch.

Reviewed By: mravishankar

Differential Revision: https://reviews.llvm.org/D86314
2020-08-28 01:55:49 -07:00
Mehdi Amini
7b00c80888 Add a global flag to disable the global dialect registry "process wise"
This is intended to ease the transition for client with a lot of
dependencies. It'll be removed in the coming weeks.

Differential Revision: https://reviews.llvm.org/D86755
2020-08-28 03:17:15 +00:00
Vincent Zhao
28a7dfa33d [MLIR] Fixed missing constraint append when adding an AffineIfOp domain
The prior diff that introduced `addAffineIfOpDomain` missed appending
constraints from the ifOp domain. This revision fixes this problem.

Differential Revision: https://reviews.llvm.org/D86421
2020-08-28 00:34:23 +05:30
Kiran Chandramohan
875074c8a9 [OpenMP][MLIR] Conversion pattern for OpenMP to LLVM
Adding a conversion pattern for the parallel Operation. This will
help the conversion of parallel operation with standard dialect to
parallel operation with llvm dialect. The type conversion of the block
arguments in a parallel region are controlled by the pattern for the
parallel Operation. Without this pattern, a parallel Operation with
block arguments cannot be converted from standard to LLVM dialect.
Other OpenMP operations without regions are marked as legal. When
translation of OpenMP operations with regions are added then patterns
for these operations can also be added.
Also uses all the standard to llvm patterns. Patterns of other dialects
can be added later if needed.

Reviewed By: rriddle

Differential Revision: https://reviews.llvm.org/D86273
2020-08-27 19:32:15 +01:00
Benjamin Kramer
fddf543e6e [MLIR][GPUToSPIRV] Fix use-after-free. Found by asan. 2020-08-27 17:57:11 +02:00