teuthida/.gitignore
Christoph Heiss 8cbd199e1e
feat: Add command to generate Verilog
Signed-off-by: Christoph Heiss <contact@christoph-heiss.at>
2022-03-26 21:47:39 +01:00

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__pycache__/
dist/
*.o
*.gtkw
*.vcd
*.v