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Christoph Heiss
8cbd199e1e
feat: Add command to generate Verilog
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Signed-off-by: Christoph Heiss <contact@christoph-heiss.at>
2022-03-26 21:47:39 +01:00
Christoph Heiss
e5cc224fbc
chore: Add some common development files
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Signed-off-by: Christoph Heiss <contact@christoph-heiss.at>
2022-03-26 21:24:10 +01:00
Christoph Heiss
0ca5b8c12e
Initial commit
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Signed-off-by: Christoph Heiss <contact@christoph-heiss.at>
2022-03-25 14:22:53 +01:00