feat: Add command to generate Verilog
Signed-off-by: Christoph Heiss <contact@christoph-heiss.at>
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.gitignore
vendored
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.gitignore
vendored
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@ -3,3 +3,4 @@ dist/
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*.o
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*.o
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*.gtkw
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*.gtkw
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*.vcd
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*.vcd
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*.v
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@ -13,6 +13,7 @@ amaranth = "^0.3"
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[tool.poetry.scripts]
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[tool.poetry.scripts]
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sim = "teuthida.sim:start"
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sim = "teuthida.sim:start"
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verilog = "teuthida.gen:gen_verilog"
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[build-system]
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[build-system]
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requires = ["poetry-core>=1.0.0"]
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requires = ["poetry-core>=1.0.0"]
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9
teuthida/gen.py
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9
teuthida/gen.py
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@ -0,0 +1,9 @@
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from amaranth.back import verilog
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from . import Cpu
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def gen_verilog():
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cpu = Cpu()
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with open('teuthida.v', 'w') as f:
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f.write(verilog.convert(cpu))
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