Commit graph

396898 commits

Author SHA1 Message Date
Matthias Springer 08dbed8a57 [mlir][linalg] Canonicalize dim ops of tiled_loop block args
E.g.:
```
%y = ... : tensor<...>
linalg.tiled_loop ... ins(%x = %y : tensor<...>) {
  tensor.dim %x, %c0 : tensor<...>
}
```

is rewritten to:
```
%y = ... : tensor<...>
linalg.tiled_loop ... ins(%x = %y : tensor<...>) {
  tensor.dim %y, %c0 : tensor<...>
}
```

Differential Revision: https://reviews.llvm.org/D108272
2021-08-19 11:24:33 +09:00
Lang Hames 8a36750236 [ORC] Handle void and no-argument async wrapper calls. 2021-08-19 12:20:31 +10:00
Sam Clegg 12b1dc0467 [WebAssembly][lld] Convert signature-mismatch.ll test to asm. NFC
Differential Revision: https://reviews.llvm.org/D108346
2021-08-18 22:17:02 -04:00
Vitaly Buka 03bd05f0e8 [sanitizer] Use TMPDIR in Android test
TMPDIR was added long time ago, so no need to use EXTERNAL_STORAGE.
2021-08-18 19:05:21 -07:00
Matthias Springer 9329438244 [mlir][linalg] Remove ConstraintsSet class
The same functionality can be implemented with FlatAffineValueConstraints.

Differential Revision: https://reviews.llvm.org/D108179
2021-08-19 10:57:35 +09:00
LLVM GN Syncbot fe658c3f6e [gn build] Port 5fdaaf7fd8 2021-08-19 01:52:47 +00:00
Peter Collingbourne 6f85225ef3 StackLifetime: Remove asserts for multiple lifetime intrinsics.
According to the langref, it is valid to have multiple consecutive
lifetime start or end intrinsics on the same object.

For llvm.lifetime.start:
"If ptr [...] is a stack object that is already alive, it simply
fills all bytes of the object with poison."

For llvm.lifetime.end:
"Calling llvm.lifetime.end on an already dead alloca is no-op."

However, we currently fail an assertion in such cases. I've observed
the assertion failure when the loop vectorization pass duplicates
the intrinsic.

We can conservatively handle these intrinsics by ignoring all but
the first one, which can be implemented by removing the assertions.

Differential Revision: https://reviews.llvm.org/D108337
2021-08-18 18:45:28 -07:00
Rong Xu 5fdaaf7fd8 [SampleFDO] Flow Sensitive Sample FDO (FSAFDO) profile loader
This patch implements Flow Sensitive Sample FDO (FSAFDO) profile
loader. We have two profile loaders for FS profile,
one before RegAlloc and one before BlockPlacement.

To enable it, when -fprofile-sample-use=<profile> is specified,
add "-enable-fs-discriminator=true \
     -disable-ra-fsprofile-loader=false \
     -disable-layout-fsprofile-loader=false"
to turn on the FS profile loaders.

Differential Revision: https://reviews.llvm.org/D107878
2021-08-18 18:37:35 -07:00
Matthias Springer c777e51468 [mlir][Analysis][NFC] FlatAffineConstraints: Use BoundType enum in functions
Differential Revision: https://reviews.llvm.org/D108185
2021-08-19 10:33:42 +09:00
Vitaly Buka 3d4d1b9b29 [scudo] Don't build SCUDO for Android
Android 11 uses scudo_standalone as default
allocator making difficult to test legacy scudo.
2021-08-18 18:32:54 -07:00
Jon Chesterfield dbd7bad9ad [openmp] Annotate tmp variables with omp_thread_mem_alloc
Fixes miscompile of calls into ocml. Bug 51445.

The stack variable `double __tmp` is moved to dynamically allocated shared
memory by CGOpenMPRuntimeGPU. This is usually fine, but when the variable
is passed to a function that is explicitly annotated address_space(5) then
allocating the variable off-stack leads to a miscompile in the back end,
which cannot decide to move the variable back to the stack from shared.

This could be fixed by removing the AS(5) annotation from the math library
or by explicitly marking the variables as thread_mem_alloc. The cast to
AS(5) is still a no-op once IR is reached.

Reviewed By: jdoerfert

Differential Revision: https://reviews.llvm.org/D107971
2021-08-19 02:22:11 +01:00
Kyungwoo Lee 829616c241 [NFC][DebugInfo] getDwarfCompileUnitID
This is a refactoring for the use in https://reviews.llvm.org/D108261

Reviewed By: dblaikie

Differential Revision: https://reviews.llvm.org/D108271
2021-08-18 17:35:03 -07:00
Jon Chesterfield f420939b82 [libomptarget] Apply D106710 to amdgcn devicertl 2021-08-19 01:34:33 +01:00
Aart Bik d37d72eaf8 [mlir][sparse] use shared util for DimOp generation
This shares more code with existing utilities. Also, to be consistent,
we moved dimension permutation on the DimOp to the tensor lowering phase.
This way, both pre-existing DimOps on sparse tensors (not likely but
possible) as well as compiler generated DimOps are handled consistently.

Reviewed By: bixia

Differential Revision: https://reviews.llvm.org/D108309
2021-08-18 17:12:32 -07:00
Jon Chesterfield c480792b6a [libomptarget][nfc][devicertl] Delete unused enums 2021-08-19 00:14:34 +01:00
Daniel McIntosh f6ba6c3976 [NFC][libcxxabi] Run clang-format on libcxxabi/src/cxa_guard_impl.h
I'm about to submit a change which involves re-writing most of
cxa_guard_impl.h. Running clang-format on the whole file first seems like a
good idea.

Reviewed By: ldionne, #libc_abi

Differential Revision: https://reviews.llvm.org/D108231
2021-08-18 19:09:16 -04:00
Diego Caballero b7cac864b2 [mlir] Fix typo in SuperVectorizer
NFC.

Reviewed By: aartbik

Differential Revision: https://reviews.llvm.org/D108334
2021-08-18 22:55:12 +00:00
Omar Emara 82507f1798 [LLDB][GUI] Add Process Launch form
This patch adds a process launch form. Additionally, a LazyBoolean field
was implemented and numerous utility methods were added to various
fields to get the launch form working.

Differential Revision: https://reviews.llvm.org/D107869
2021-08-18 15:43:30 -07:00
owenca 643f2be7b6 [clang-format] Improve detection of parameter declarations in K&R C
Clean up the detection of parameter declarations in K&R C function
definitions. Also make it more precise by requiring the second
token after the r_paren to be either a star or keyword/identifier.

Differential Revision: https://reviews.llvm.org/D108094
2021-08-18 15:21:48 -07:00
Omar Emara 698e210636 [LLDB][GUI] Fix text field incorrect key handling
The isprint libc function was used to determine if the key code
represents a printable character. The problem is that the specification
leaves the behavior undefined if the key is not representable as an
unsigned char, which is the case for many ncurses keys. This patch adds
and explicit check for this undefined behavior and make it consistent.

The llvm::isPrint function didn't work correctly for some reason, most
likely because it takes a char instead of an int, which I guess makes it
unsuitable for checking ncurses key codes.

Reviewed By: clayborg

Differential Revision: https://reviews.llvm.org/D108327
2021-08-18 15:06:27 -07:00
LLVM GN Syncbot a0ed44943a [gn build] Port d8bbfe8a48 2021-08-18 21:58:30 +00:00
Rafael Auler d8bbfe8a48 [DWARF] Expose raw bytes in DWARFExpression
This information is necessary for clients of DebugInfo that
do not want to process a DWARF expression, but just treat it as a blob
of data. In BOLT, for example, we need to read these expressions in
CFIs and write them back to the binary, unchanged, so having access to
the original expression encoding is a shortcut to avoid the need to
re-encode the entire expression when re-writing exception handling
info (CFIs).

This patch is an alternative to https://reviews.llvm.org/D98301, in
which we implement the support to re-encode these expressions. But
since we don't really need to change anything in these expressions,
we can just copy their bytes.

Reviewed By: aprantl

Differential Revision: https://reviews.llvm.org/D107515
2021-08-18 14:41:20 -07:00
Chia-hung Duan 41e5dbe0fa Enables inferring return types for Shape op if possible
Reviewed By: jpienaar

Differential Revision: https://reviews.llvm.org/D102565
2021-08-18 21:36:55 +00:00
Jessica Paquette c22b64ef66 [AArch64][GlobalISel] Don't allow s128 for G_ISNAN
getAPFloatFromSize doesn't support s128, so we can't lower this without
asserting right now.

To fix the buildbots, don't allow any scalars other than s16, s32, and s64.
2021-08-18 13:59:00 -07:00
Peter Collingbourne b2e77cd095 gn build: Build libclang.so and libLTO.so on ELF platforms.
This requires changing the ELF build to enable -fPIC, consistent
with other platforms.

Differential Revision: https://reviews.llvm.org/D108223
2021-08-18 13:48:33 -07:00
Jessica Paquette 3d91d5b757 [AArch64][GlobalISel] Mark G_FMINNUM/G_FMAXNUM as floating point opcodes
We need to ensure that these end up on FPR to allow imported patterns to
select them.

This will also ensure that we get good regbank selection when dealing with
instructions like G_PHI/G_LOAD/G_STORE which deduce their banks from their
uses/users.

Differential Revision: https://reviews.llvm.org/D108260
2021-08-18 13:32:19 -07:00
Jessica Paquette 45e1a6bd25 [AArch64][GlobalISel] Legalize scalar G_FMINNUM + G_FMAXNUM
For subtargets with full FP16, this is legal for s16, s32, and s64. Without
full FP16, it's legal for s32 and s64.

For s128, this is a libcall.

We also support some vector types, but for now, let's just support scalars.

Differential Revision: https://reviews.llvm.org/D108259
2021-08-18 13:30:03 -07:00
Jon Chesterfield 21d91a8ef3 [libomptarget][devicertl] Replace lanemask with uint64 at interface
Use uint64_t for lanemask on all GPU architectures at the interface
with clang. Updates tests. The deviceRTL is always linked as IR so the zext
and trunc introduced for wave32 architectures will fold after inlining.

Simplification partly motivated by amdgpu gfx10 which will be wave32 and
is awkward to express in the current arch-dependant typedef interface.

Reviewed By: jdoerfert

Differential Revision: https://reviews.llvm.org/D108317
2021-08-18 20:47:33 +01:00
Anton Afanasyev cfb6dfcbd1 [AggressiveInstCombine] Add logical shift right instr to TruncInstCombine DAG
Add `lshr` instruction to the DAG post-dominated by `trunc`, allowing
TruncInstCombine to reduce bitwidth of expressions containing
these instructions.

We should be shifting by less than the target bitwidth.
Also it is sufficient to require that all truncated bits
of the value-to-be-shifted are zeros: https://alive2.llvm.org/ce/z/_LytbB

Alive2 variable-length proof:
https://godbolt.org/z/1srE1aqzf => s/32/8/ => https://alive2.llvm.org/ce/z/StwPia

Part of https://reviews.llvm.org/D107766

Differential Revision: https://reviews.llvm.org/D108201
2021-08-18 22:20:58 +03:00
Anton Afanasyev 2498c3edcd [Test][AggressiveInstCombine] Add one more tests for shifts 2021-08-18 22:20:57 +03:00
Robert Suderman 76c9712196 [mlir][tosa] Fix clamp to restrict only within valid bitwidth range
Its possible for the clamp to have invalid min/max values on its range. To fix
this we validate the range of the min/max and clamp to a valid range.

Reviewed By: NatashaKnk

Differential Revision: https://reviews.llvm.org/D108256
2021-08-18 12:14:01 -07:00
Michael Kruse 58e4e71fc8 [Polly] Introduce caching for the isErrorBlock function. NFC.
Compilation of the file insn-attrtab.c of the SPEC CPU 2017 502.gcc_r
benchmark takes excessive time (> 30min) with Polly enabled. Most time
is spent in the isErrorBlock function querying the DominatorTree.
The isErrorBlock is invoked redundantly over the course of ScopDetection
and ScopBuilder. This patch introduces a caching mechanism for its
result.

Instead of a free function, isErrorBlock is moved to ScopDetection where
its cache map resides. This also means that many functions directly or
indirectly calling isErrorBlock are not "const" anymore. The
DetectionContextMap was marked as "mutable", but IMHO it never should
have been since it stores the detection result.

502.gcc_r only takes excessive time with the new pass manager. The
reason seeams to be that it invalidates the ScopDetection analysis more
often than the legacy pass manager, for unknown reasons.
2021-08-18 14:05:50 -05:00
Ali Sedaghati cc7bcef3e3 Reapply: [NFC] factor out unrolling decision logic
reverting ffd8a268bd (reapplying
4d559837e8) - removed spurious inclusion
of <optional>

Differential Revision: https://reviews.llvm.org/D106001
2021-08-18 12:04:33 -07:00
Andrea Di Biagio 2d53e54f0e [X86][NFC] Pre-commit tests for PR51494 2021-08-18 19:55:21 +01:00
Simon Pilgrim ba1f6ffb8d [PowerPC] Regenerate 2007-09-08-unaligned.ll test checks 2021-08-18 19:54:11 +01:00
Azharuddin Mohammed b4b8e1446a [tsan] Disable all Trace unit tests on Mac
In an earlier commit (7338be0e6e), only the MemoryAccessSize unit test
was disabled whereas the other tests which are also failing were not.
2021-08-18 11:47:51 -07:00
Geoffrey Martin-Noble ffd8a268bd Revert "[NFC] factor out unrolling decision logic"
This patch added a requirement for C++17, while LLVM is supposed to
build with C++14
(https://llvm.org/docs/CodingStandards.html#c-standard-versions). Posted
a note to the original review thread (https://reviews.llvm.org/D106001).

This reverts commit 4d559837e8.

Differential Revision: https://reviews.llvm.org/D108314
2021-08-18 11:38:48 -07:00
Joe Nash 9dbc968ed9 [AMDGPU] Fix atomic float max/min intrinsics
Hooked up raw.buffer.atomic.fmin/max.f64
This instruction should be available on GFX6, GFX7, and GFX10.
It was implemented for GFX90a with a different name.

Added intrinsic def for image_atomic_fmin/fmax; the instruction
defs were already there.

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D108208

Change-Id: I473f98d28b2afbeeb2c27822d9686b5e86634e2f
2021-08-18 14:12:42 -04:00
Mitch Phillips fd51ab6341 [hwasan] Don't report short-granule shadow as overwritten.
The shadow for a short granule is stored in the last byte of the
granule. Currently, if there's a tail-overwrite report (a
buffer-overflow-write in uninstrumented code), we report the shadow byte
as a mismatch against the magic.

Fix this bug by slapping the shadow into the expected value. This also
makes sure that if the uninstrumented WRITE does clobber the shadow
byte, it reports the shadow was actually clobbered as well.

Reviewed By: eugenis, fmayer

Differential Revision: https://reviews.llvm.org/D107938
2021-08-18 11:25:57 -07:00
Nikita Popov 3dd8c9176b [LICM] Remove AST-based implementation
MSSA-based LICM has been enabled by default for a few years now.
This drops the old AST-based implementation. Using loop(licm) will
result in a fatal error, the use of loop-mssa(licm) is required
(or just licm, which defaults to loop-mssa).

Note that the core canSinkOrHoistInst() logic has to retain AST
support for now, because it is shared with LoopSink.

Differential Revision: https://reviews.llvm.org/D108244
2021-08-18 20:21:53 +02:00
Ali Sedaghati 4d559837e8 [NFC] factor out unrolling decision logic
Decoupling the unrolling logic into three different functions. The shouldPragmaUnroll() covers the 1st and 2nd priorities of the previous code, the shouldFullUnroll() covers the 3rd, and the shouldPartialUnroll() covers the 5th. The output of each function, Optional<unsigned>, could be a value for UP.Count, which means unrolling factor has been set, or None, which means decision hasn't been made yet and should try the next priority.

Reviewed By: mtrofin, jdoerfert

Differential Revision: https://reviews.llvm.org/D106001
2021-08-18 11:21:40 -07:00
Geoffrey Martin-Noble 811dbecaf5 [Bazel] Don't set HAVE_[DE]REGISTER_FRAME on Windows
This is also done based on OS in the GN build
(https://github.com/llvm/llvm-project/blob/24b0df8686/llvm/utils/gn/secondary/llvm/include/llvm/Config/BUILD.gn#L193-L203).
Of course the right way would be to set up platform detection, but that
remains TODO.

Reviewed By: csigg

Differential Revision: https://reviews.llvm.org/D107375
2021-08-18 11:20:25 -07:00
Arthur Eubanks fde0eb1f9a [NFC] A couple more removeAttribute() cleanups 2021-08-18 11:15:20 -07:00
Arthur Eubanks 2fc075948c [NFC] Remove some unnecessary AttributeList methods
These rely on methods I'm trying to cleanup.
2021-08-18 11:15:20 -07:00
Christopher Tetreault 2afb9394a7 [hwasan] Flag stack safety check as requiring aarch64
Reviewed By: fmayer

Differential Revision: https://reviews.llvm.org/D108241
2021-08-18 11:14:01 -07:00
Craig Topper 3f9b37ccb1 [RISCV] Remove sext_inreg+add/sub/mul/shl isel patterns.
Let the sext_inreg be selected to sext.w. Remove unneeded sext.w
during PostProcessISelDAG.

This gives opportunities for some other isel patterns to match
like the ADDIPair or matching mul with immediate to shXadd.

This becomes possible after D107658 started selecting W instructions
based on users. The sext.w will be considered a W user so isel
will often select a W instruction for the sext.w input and we can
just remove the sext.w. Otherwise we can combine the sext.w with
a ADD/SUB/MUL/SLLI to create a new W instruction in parallel
to the the original instruction.

Reviewed By: luismarques

Differential Revision: https://reviews.llvm.org/D107708
2021-08-18 11:07:11 -07:00
Jessica Paquette 791006fb8c [GlobalISel] Implement lowering for G_ISNAN + use it in AArch64
GlobalISel equivalent to `TargetLowering::expandISNAN`.

Use it in AArch64 and add a testcase.

Differential Revision: https://reviews.llvm.org/D108227
2021-08-18 10:54:25 -07:00
Han Zhu 687f046c97 [NFC][loop-idiom] Rename Stores to IgnoredInsts; Fix a typo
When dealing with memmove, we also add the load instruction to the ignored
instructions list passed to `mayLoopAccessLocation`. Renaming "Stores" to
"IgnoredInsts" to be more precise.

Differential Revision: https://reviews.llvm.org/D108275
2021-08-18 10:52:16 -07:00
Jessica Paquette d9873711cb [GlobalISel] Add IRTranslator support for G_ISNAN
Translate the `@llvm.isnan` intrinsic to G_ISNAN when we see it.

This is pretty much the same as the associated SelectionDAGBuilder code. Main
difference is that we don't expand it here. It makes more sense to do that
during legalization in GlobalISel. GlobalISel will just legalize the generated
illegal types.

Differential Revision: https://reviews.llvm.org/D108226
2021-08-18 10:48:10 -07:00
Jinsong Ji 66e2772e42 [InstrProfiling] Support relative CountersPtr for PlatformOther
D104556 change the CountersPtr to be relative, however, it did not
update the pointer initialization in  __llvm_profile_register_function,
so the platform (eg:AIX) that use __llvm_profile_register_function is now totaly
broken, any PGO code will SEGV.

This patch update the code to reflect that the Data->CountersPtr is now
relative.

Reviewed By: MaskRay, davidxl

Differential Revision: https://reviews.llvm.org/D108304
2021-08-18 17:45:39 +00:00