fix 32-bit ARM compilation error

This commit is contained in:
Jorge Aparicio 2021-05-15 21:28:39 +02:00
parent 736054a56f
commit 76a3dd54eb

View file

@ -14,7 +14,7 @@ pub mod nr;
#[inline(always)]
pub unsafe fn syscall0(n: usize) -> usize {
let ret: usize;
llvm_asm!("swi $$0"
llvm_asm!("swi 0"
: "={r0}"(ret)
: "{r7}"(n)
: "memory" "cc"
@ -25,7 +25,7 @@ pub unsafe fn syscall0(n: usize) -> usize {
#[inline(always)]
pub unsafe fn syscall1(n: usize, a1: usize) -> usize {
let ret: usize;
llvm_asm!("swi $$0"
llvm_asm!("swi 0"
: "={r0}"(ret)
: "{r7}"(n) "{r0}"(a1)
: "memory" "cc"
@ -36,7 +36,7 @@ pub unsafe fn syscall1(n: usize, a1: usize) -> usize {
#[inline(always)]
pub unsafe fn syscall2(n: usize, a1: usize, a2: usize) -> usize {
let ret: usize;
llvm_asm!("swi $$0"
llvm_asm!("swi 0"
: "={r0}"(ret)
: "{r7}"(n) "{r0}"(a1) "{r1}"(a2)
: "memory" "cc"
@ -47,7 +47,7 @@ pub unsafe fn syscall2(n: usize, a1: usize, a2: usize) -> usize {
#[inline(always)]
pub unsafe fn syscall3(n: usize, a1: usize, a2: usize, a3: usize) -> usize {
let ret: usize;
llvm_asm!("swi $$0"
llvm_asm!("swi 0"
: "={r0}"(ret)
: "{r7}"(n) "{r0}"(a1) "{r1}"(a2) "{r2}"(a3)
: "memory" "cc"
@ -63,7 +63,7 @@ pub unsafe fn syscall4(n: usize,
a4: usize)
-> usize {
let ret: usize;
llvm_asm!("swi $$0"
llvm_asm!("swi 0"
: "={r0}"(ret)
: "{r7}"(n) "{r0}"(a1) "{r1}"(a2) "{r2}"(a3) "{r3}"(a4)
: "memory" "cc"
@ -80,7 +80,7 @@ pub unsafe fn syscall5(n: usize,
a5: usize)
-> usize {
let ret: usize;
llvm_asm!("swi $$0" : "={r0}"(ret)
llvm_asm!("swi 0" : "={r0}"(ret)
: "{r7}"(n) "{r0}"(a1) "{r1}"(a2) "{r2}"(a3) "{r3}"(a4) "{r4}"(a5)
: "memory" "cc"
: "volatile");
@ -97,7 +97,7 @@ pub unsafe fn syscall6(n: usize,
a6: usize)
-> usize {
let ret: usize;
llvm_asm!("swi $$0"
llvm_asm!("swi 0"
: "={r0}"(ret)
: "{r7}"(n) "{r0}"(a1) "{r1}"(a2) "{r2}"(a3) "{r3}"(a4) "{r4}"(a5)
"{r5}"(a6)
@ -117,7 +117,7 @@ pub unsafe fn syscall7(n: usize,
a7: usize)
-> usize {
let ret: usize;
llvm_asm!("swi $$0"
llvm_asm!("swi 0"
: "={r0}"(ret)
: "{r7}"(n) "{r0}"(a1) "{r1}"(a2) "{r2}"(a3) "{r3}"(a4) "{r4}"(a5)
"{r5}"(a6) "{r6}"(a7)