rust/compiler/rustc_codegen_llvm
bors bb587b1a17 Auto merge of #80652 - calebzulawski:simd-lanes, r=nagisa
Improve SIMD type element count validation

Resolves rust-lang/stdsimd#53.

These changes are motivated by `stdsimd` moving in the direction of const generic vectors, e.g.:
```rust
#[repr(simd)]
struct SimdF32<const N: usize>([f32; N]);
```

This makes a few changes:
* Establishes a maximum SIMD lane count of 2^16 (65536).  This value is arbitrary, but attempts to validate lane count before hitting potential errors in the backend.  It's not clear what LLVM's maximum lane count is, but cranelift's appears to be much less than `usize::MAX`, at least.
* Expands some SIMD intrinsics to support arbitrary lane counts.  This resolves the ICE in the linked issue.
* Attempts to catch invalid-sized vectors during typeck when possible.

Unresolved questions:
* Generic-length vectors can't be validated in typeck and are only validated after monomorphization while computing layout.  This "works", but the errors simply bail out with no context beyond the name of the type.  Should these errors instead return `LayoutError` or otherwise provide context in some way?  As it stands, users of `stdsimd` could trivially produce monomorphization errors by making zero-length vectors.

cc `@bjorn3`
2021-02-07 22:25:14 +00:00
..
src Auto merge of #80652 - calebzulawski:simd-lanes, r=nagisa 2021-02-07 22:25:14 +00:00
Cargo.toml Upgrade to measureme 9.0.0 2020-10-24 22:39:42 -04:00
README.md mv compiler to compiler/ 2020-08-30 18:45:07 +03:00

The codegen crate contains the code to convert from MIR into LLVM IR, and then from LLVM IR into machine code. In general it contains code that runs towards the end of the compilation process.

For more information about how codegen works, see the rustc dev guide.