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Fix rustdoc lints

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This commit is contained in:
Mark Rousskov 2022-11-02 08:01:43 -04:00
parent 40290505fb
commit b3242f4f13
2 changed files with 2 additions and 2 deletions
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2
library/portable-simd/crates/core_simd/src/intrinsics.rs
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@ -103,7 +103,7 @@ extern "platform-intrinsic" {
/// val: vector of values to select if a lane is masked /// val: vector of values to select if a lane is masked
/// ptr: vector of pointers to read from /// ptr: vector of pointers to read from
/// mask: a "wide" mask of integers, selects as if simd_select(mask, read(ptr), val) /// mask: a "wide" mask of integers, selects as if simd_select(mask, read(ptr), val)
/// note, the LLVM intrinsic accepts a mask vector of <N x i1> /// note, the LLVM intrinsic accepts a mask vector of `<N x i1>`
/// FIXME: review this if/when we fix up our mask story in general? /// FIXME: review this if/when we fix up our mask story in general?
pub(crate) fn simd_gather<T, U, V>(val: T, ptr: U, mask: V) -> T; pub(crate) fn simd_gather<T, U, V>(val: T, ptr: U, mask: V) -> T;
/// llvm.masked.scatter /// llvm.masked.scatter

2
library/portable-simd/crates/core_simd/src/ops.rs
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@ -40,7 +40,7 @@ macro_rules! unsafe_base {
/// SAFETY: This macro should not be used for anything except Shl or Shr, and passed the appropriate shift intrinsic. /// SAFETY: This macro should not be used for anything except Shl or Shr, and passed the appropriate shift intrinsic.
/// It handles performing a bitand in addition to calling the shift operator, so that the result /// It handles performing a bitand in addition to calling the shift operator, so that the result
/// is well-defined: LLVM can return a poison value if you shl, lshr, or ashr if rhs >= <Int>::BITS /// is well-defined: LLVM can return a poison value if you shl, lshr, or ashr if `rhs >= <Int>::BITS`
/// At worst, this will maybe add another instruction and cycle, /// At worst, this will maybe add another instruction and cycle,
/// at best, it may open up more optimization opportunities, /// at best, it may open up more optimization opportunities,
/// or simply be elided entirely, especially for SIMD ISAs which default to this. /// or simply be elided entirely, especially for SIMD ISAs which default to this.