Fix handling of reserved registers for ARM inline asm
This commit is contained in:
parent
7adbc0dfef
commit
8d0e882065
6 changed files with 67 additions and 18 deletions
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@ -1004,6 +1004,7 @@ impl<'hir> LoweringContext<'_, 'hir> {
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asm::InlineAsmReg::parse(
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sess.asm_arch?,
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|feature| sess.target_features.contains(&Symbol::intern(feature)),
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&sess.target.target,
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s,
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)
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.map_err(|e| {
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@ -156,6 +156,10 @@ const ARM_WHITELIST: &[(&str, Option<Symbol>)] = &[
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("vfp2", Some(sym::arm_target_feature)),
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("vfp3", Some(sym::arm_target_feature)),
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("vfp4", Some(sym::arm_target_feature)),
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// This is needed for inline assembly, but shouldn't be stabilized as-is
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// since it should be enabled per-function using #[instruction_set], not
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// #[target_feature].
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("thumb-mode", Some(sym::arm_target_feature)),
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];
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const AARCH64_WHITELIST: &[(&str, Option<Symbol>)] = &[
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@ -1,4 +1,5 @@
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use super::{InlineAsmArch, InlineAsmType};
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use crate::spec::Target;
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use rustc_macros::HashStable_Generic;
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use std::fmt;
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@ -58,6 +59,37 @@ impl ArmInlineAsmRegClass {
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}
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}
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// This uses the same logic as useR7AsFramePointer in LLVM
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fn frame_pointer_is_r7(mut has_feature: impl FnMut(&str) -> bool, target: &Target) -> bool {
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target.options.is_like_osx || (!target.options.is_like_windows && has_feature("thumb-mode"))
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}
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fn frame_pointer_r11(
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_arch: InlineAsmArch,
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has_feature: impl FnMut(&str) -> bool,
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target: &Target,
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_allocating: bool,
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) -> Result<(), &'static str> {
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if !frame_pointer_is_r7(has_feature, target) {
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Err("the frame pointer (r11) cannot be used as an operand for inline asm")
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} else {
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Ok(())
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}
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}
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fn frame_pointer_r7(
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_arch: InlineAsmArch,
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has_feature: impl FnMut(&str) -> bool,
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target: &Target,
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_allocating: bool,
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) -> Result<(), &'static str> {
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if frame_pointer_is_r7(has_feature, target) {
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Err("the frame pointer (r7) cannot be used as an operand for inline asm")
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} else {
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Ok(())
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}
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}
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def_regs! {
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Arm ArmInlineAsmReg ArmInlineAsmRegClass {
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r0: reg, reg_thumb = ["r0", "a1"],
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@ -66,11 +98,11 @@ def_regs! {
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r3: reg, reg_thumb = ["r3", "a4"],
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r4: reg, reg_thumb = ["r4", "v1"],
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r5: reg, reg_thumb = ["r5", "v2"],
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r6: reg, reg_thumb = ["r6", "v3"],
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r7: reg, reg_thumb = ["r7", "v4"],
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r7: reg, reg_thumb = ["r7", "v4"] % frame_pointer_r7,
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r8: reg = ["r8", "v5"],
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r9: reg = ["r9", "v6", "rfp"],
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r10: reg = ["r10", "sl"],
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r11: reg = ["r11", "fp"] % frame_pointer_r11,
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r12: reg = ["r12", "ip"],
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r14: reg = ["r14", "lr"],
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s0: sreg, sreg_low16 = ["s0"],
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@ -153,8 +185,8 @@ def_regs! {
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q13: qreg = ["q13"],
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q14: qreg = ["q14"],
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q15: qreg = ["q15"],
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#error = ["r11", "fp"] =>
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"the frame pointer cannot be used as an operand for inline asm",
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#error = ["r6", "v3"] =>
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"r6 is used internally by LLVM and cannot be used as an operand for inline asm",
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#error = ["r13", "sp"] =>
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"the stack pointer cannot be used as an operand for inline asm",
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#error = ["r15", "pc"] =>
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@ -1,4 +1,5 @@
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use crate::abi::Size;
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use crate::spec::Target;
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use rustc_data_structures::fx::{FxHashMap, FxHashSet};
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use rustc_macros::HashStable_Generic;
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use rustc_span::Symbol;
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@ -83,12 +84,13 @@ macro_rules! def_regs {
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pub fn parse(
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_arch: super::InlineAsmArch,
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mut _has_feature: impl FnMut(&str) -> bool,
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_target: &crate::spec::Target,
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name: &str,
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) -> Result<Self, &'static str> {
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match name {
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$(
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$($alias)|* | $reg_name => {
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$($filter(_arch, &mut _has_feature, false)?;)?
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$($filter(_arch, &mut _has_feature, _target, false)?;)?
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Ok(Self::$reg)
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}
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)*
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@ -103,6 +105,7 @@ macro_rules! def_regs {
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pub(super) fn fill_reg_map(
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_arch: super::InlineAsmArch,
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mut _has_feature: impl FnMut(&str) -> bool,
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_target: &crate::spec::Target,
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_map: &mut rustc_data_structures::fx::FxHashMap<
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super::InlineAsmRegClass,
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rustc_data_structures::fx::FxHashSet<super::InlineAsmReg>,
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@ -111,7 +114,7 @@ macro_rules! def_regs {
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#[allow(unused_imports)]
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use super::{InlineAsmReg, InlineAsmRegClass};
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$(
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if $($filter(_arch, &mut _has_feature, true).is_ok() &&)? true {
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if $($filter(_arch, &mut _has_feature, _target, true).is_ok() &&)? true {
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if let Some(set) = _map.get_mut(&InlineAsmRegClass::$arch($arch_regclass::$class)) {
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set.insert(InlineAsmReg::$arch($arch_reg::$reg));
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}
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@ -234,6 +237,7 @@ impl InlineAsmReg {
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pub fn parse(
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arch: InlineAsmArch,
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has_feature: impl FnMut(&str) -> bool,
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target: &Target,
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name: Symbol,
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) -> Result<Self, &'static str> {
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// FIXME: use direct symbol comparison for register names
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@ -241,20 +245,22 @@ impl InlineAsmReg {
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let name = name.as_str();
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Ok(match arch {
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InlineAsmArch::X86 | InlineAsmArch::X86_64 => {
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Self::X86(X86InlineAsmReg::parse(arch, has_feature, &name)?)
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Self::X86(X86InlineAsmReg::parse(arch, has_feature, target, &name)?)
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}
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InlineAsmArch::Arm => {
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Self::Arm(ArmInlineAsmReg::parse(arch, has_feature, target, &name)?)
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}
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InlineAsmArch::Arm => Self::Arm(ArmInlineAsmReg::parse(arch, has_feature, &name)?),
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InlineAsmArch::AArch64 => {
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Self::AArch64(AArch64InlineAsmReg::parse(arch, has_feature, &name)?)
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Self::AArch64(AArch64InlineAsmReg::parse(arch, has_feature, target, &name)?)
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}
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InlineAsmArch::RiscV32 | InlineAsmArch::RiscV64 => {
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Self::RiscV(RiscVInlineAsmReg::parse(arch, has_feature, &name)?)
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Self::RiscV(RiscVInlineAsmReg::parse(arch, has_feature, target, &name)?)
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}
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InlineAsmArch::Nvptx64 => {
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Self::Nvptx(NvptxInlineAsmReg::parse(arch, has_feature, &name)?)
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Self::Nvptx(NvptxInlineAsmReg::parse(arch, has_feature, target, &name)?)
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}
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InlineAsmArch::Hexagon => {
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Self::Hexagon(HexagonInlineAsmReg::parse(arch, has_feature, &name)?)
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Self::Hexagon(HexagonInlineAsmReg::parse(arch, has_feature, target, &name)?)
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}
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})
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}
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@ -536,36 +542,37 @@ impl fmt::Display for InlineAsmType {
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pub fn allocatable_registers(
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arch: InlineAsmArch,
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has_feature: impl FnMut(&str) -> bool,
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target: &crate::spec::Target,
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) -> FxHashMap<InlineAsmRegClass, FxHashSet<InlineAsmReg>> {
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match arch {
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InlineAsmArch::X86 | InlineAsmArch::X86_64 => {
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let mut map = x86::regclass_map();
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x86::fill_reg_map(arch, has_feature, &mut map);
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x86::fill_reg_map(arch, has_feature, target, &mut map);
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map
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}
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InlineAsmArch::Arm => {
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let mut map = arm::regclass_map();
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arm::fill_reg_map(arch, has_feature, &mut map);
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arm::fill_reg_map(arch, has_feature, target, &mut map);
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map
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}
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InlineAsmArch::AArch64 => {
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let mut map = aarch64::regclass_map();
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aarch64::fill_reg_map(arch, has_feature, &mut map);
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aarch64::fill_reg_map(arch, has_feature, target, &mut map);
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map
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}
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InlineAsmArch::RiscV32 | InlineAsmArch::RiscV64 => {
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let mut map = riscv::regclass_map();
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riscv::fill_reg_map(arch, has_feature, &mut map);
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riscv::fill_reg_map(arch, has_feature, target, &mut map);
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map
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}
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InlineAsmArch::Nvptx64 => {
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let mut map = nvptx::regclass_map();
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nvptx::fill_reg_map(arch, has_feature, &mut map);
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nvptx::fill_reg_map(arch, has_feature, target, &mut map);
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map
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}
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InlineAsmArch::Hexagon => {
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let mut map = hexagon::regclass_map();
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hexagon::fill_reg_map(arch, has_feature, &mut map);
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hexagon::fill_reg_map(arch, has_feature, target, &mut map);
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map
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}
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}
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@ -1,4 +1,5 @@
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use super::{InlineAsmArch, InlineAsmType};
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use crate::spec::Target;
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use rustc_macros::HashStable_Generic;
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use std::fmt;
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@ -50,6 +51,7 @@ impl RiscVInlineAsmRegClass {
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fn not_e(
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_arch: InlineAsmArch,
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mut has_feature: impl FnMut(&str) -> bool,
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_target: &Target,
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_allocating: bool,
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) -> Result<(), &'static str> {
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if has_feature("e") {
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@ -1,4 +1,5 @@
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use super::{InlineAsmArch, InlineAsmType};
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use crate::spec::Target;
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use rustc_macros::HashStable_Generic;
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use std::fmt;
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@ -131,6 +132,7 @@ impl X86InlineAsmRegClass {
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fn x86_64_only(
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arch: InlineAsmArch,
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_has_feature: impl FnMut(&str) -> bool,
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_target: &Target,
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_allocating: bool,
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) -> Result<(), &'static str> {
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match arch {
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@ -143,6 +145,7 @@ fn x86_64_only(
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fn high_byte(
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arch: InlineAsmArch,
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_has_feature: impl FnMut(&str) -> bool,
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_target: &Target,
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allocating: bool,
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) -> Result<(), &'static str> {
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match arch {
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