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Implement float simd comparisons

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This commit is contained in:
bjorn3 2020-11-23 11:21:15 +01:00
parent 22c9623604
commit 47ff2e0932
2 changed files with 14 additions and 9 deletions
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6
src/intrinsics/mod.rs
View file

@ -287,7 +287,7 @@ fn bool_to_zero_or_max_uint<'tcx>(
} }
macro simd_cmp { macro simd_cmp {
($fx:expr, $cc:ident($x:ident, $y:ident) -> $ret:ident) => { ($fx:expr, $cc:ident|$cc_f:ident($x:ident, $y:ident) -> $ret:ident) => {
let vector_ty = clif_vector_type($fx.tcx, $x.layout()); let vector_ty = clif_vector_type($fx.tcx, $x.layout());
if let Some(vector_ty) = vector_ty { if let Some(vector_ty) = vector_ty {
@ -308,6 +308,7 @@ macro simd_cmp {
|fx, lane_layout, res_lane_layout, x_lane, y_lane| { |fx, lane_layout, res_lane_layout, x_lane, y_lane| {
let res_lane = match lane_layout.ty.kind() { let res_lane = match lane_layout.ty.kind() {
ty::Uint(_) | ty::Int(_) => fx.bcx.ins().icmp(IntCC::$cc, x_lane, y_lane), ty::Uint(_) | ty::Int(_) => fx.bcx.ins().icmp(IntCC::$cc, x_lane, y_lane),
ty::Float(_) => fx.bcx.ins().fcmp(FloatCC::$cc_f, x_lane, y_lane),
_ => unreachable!("{:?}", lane_layout.ty), _ => unreachable!("{:?}", lane_layout.ty),
}; };
bool_to_zero_or_max_uint(fx, res_lane_layout, res_lane) bool_to_zero_or_max_uint(fx, res_lane_layout, res_lane)
@ -315,7 +316,7 @@ macro simd_cmp {
); );
} }
}, },
($fx:expr, $cc_u:ident|$cc_s:ident($x:ident, $y:ident) -> $ret:ident) => { ($fx:expr, $cc_u:ident|$cc_s:ident|$cc_f:ident($x:ident, $y:ident) -> $ret:ident) => {
// FIXME use vector icmp when possible // FIXME use vector icmp when possible
simd_pair_for_each_lane( simd_pair_for_each_lane(
$fx, $fx,
@ -326,6 +327,7 @@ macro simd_cmp {
let res_lane = match lane_layout.ty.kind() { let res_lane = match lane_layout.ty.kind() {
ty::Uint(_) => fx.bcx.ins().icmp(IntCC::$cc_u, x_lane, y_lane), ty::Uint(_) => fx.bcx.ins().icmp(IntCC::$cc_u, x_lane, y_lane),
ty::Int(_) => fx.bcx.ins().icmp(IntCC::$cc_s, x_lane, y_lane), ty::Int(_) => fx.bcx.ins().icmp(IntCC::$cc_s, x_lane, y_lane),
ty::Float(_) => fx.bcx.ins().fcmp(FloatCC::$cc_f, x_lane, y_lane),
_ => unreachable!("{:?}", lane_layout.ty), _ => unreachable!("{:?}", lane_layout.ty),
}; };
bool_to_zero_or_max_uint(fx, res_lane_layout, res_lane) bool_to_zero_or_max_uint(fx, res_lane_layout, res_lane)

17
src/intrinsics/simd.rs
View file

@ -35,30 +35,33 @@ pub(super) fn codegen_simd_intrinsic_call<'tcx>(
}); });
}; };
// FIXME support float comparisons
simd_eq, (c x, c y) { simd_eq, (c x, c y) {
validate_simd_type!(fx, intrinsic, span, x.layout().ty); validate_simd_type!(fx, intrinsic, span, x.layout().ty);
simd_cmp!(fx, Equal(x, y) -> ret); simd_cmp!(fx, Equal|Equal(x, y) -> ret);
}; };
simd_ne, (c x, c y) { simd_ne, (c x, c y) {
validate_simd_type!(fx, intrinsic, span, x.layout().ty); validate_simd_type!(fx, intrinsic, span, x.layout().ty);
simd_cmp!(fx, NotEqual(x, y) -> ret); simd_cmp!(fx, NotEqual|NotEqual(x, y) -> ret);
}; };
simd_lt, (c x, c y) { simd_lt, (c x, c y) {
validate_simd_type!(fx, intrinsic, span, x.layout().ty); validate_simd_type!(fx, intrinsic, span, x.layout().ty);
simd_cmp!(fx, UnsignedLessThan|SignedLessThan(x, y) -> ret); simd_cmp!(fx, UnsignedLessThan|SignedLessThan|LessThan(x, y) -> ret);
}; };
simd_le, (c x, c y) { simd_le, (c x, c y) {
validate_simd_type!(fx, intrinsic, span, x.layout().ty); validate_simd_type!(fx, intrinsic, span, x.layout().ty);
simd_cmp!(fx, UnsignedLessThanOrEqual|SignedLessThanOrEqual(x, y) -> ret); simd_cmp!(fx, UnsignedLessThanOrEqual|SignedLessThanOrEqual|LessThanOrEqual(x, y) -> ret);
}; };
simd_gt, (c x, c y) { simd_gt, (c x, c y) {
validate_simd_type!(fx, intrinsic, span, x.layout().ty); validate_simd_type!(fx, intrinsic, span, x.layout().ty);
simd_cmp!(fx, UnsignedGreaterThan|SignedGreaterThan(x, y) -> ret); simd_cmp!(fx, UnsignedGreaterThan|SignedGreaterThan|GreaterThan(x, y) -> ret);
}; };
simd_ge, (c x, c y) { simd_ge, (c x, c y) {
validate_simd_type!(fx, intrinsic, span, x.layout().ty); validate_simd_type!(fx, intrinsic, span, x.layout().ty);
simd_cmp!(fx, UnsignedGreaterThanOrEqual|SignedGreaterThanOrEqual(x, y) -> ret); simd_cmp!(
fx,
UnsignedGreaterThanOrEqual|SignedGreaterThanOrEqual|GreaterThanOrEqual
(x, y) -> ret
);
}; };
// simd_shuffle32<T, U>(x: T, y: T, idx: [u32; 32]) -> U // simd_shuffle32<T, U>(x: T, y: T, idx: [u32; 32]) -> U