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Use new feature names in target feature lists

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This commit is contained in:
Nikita Popov 2019-07-07 18:10:12 +02:00
parent b57c499ea2
commit 3170b62cca
9 changed files with 12 additions and 12 deletions
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2
src/librustc_target/spec/armebv7r_none_eabihf.rs
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@ -21,7 +21,7 @@ pub fn target() -> TargetResult {
linker: Some("rust-lld".to_owned()),
relocation_model: "static".to_string(),
panic_strategy: PanicStrategy::Abort,
features: "+vfp3,+d16,+fp-only-sp".to_string(),
features: "+vfp3,-d32,-fp16".to_string(),
max_atomic_width: Some(32),
abi_blacklist: super::arm_base::abi_blacklist(),
emit_debug_gdb_scripts: false,

2
src/librustc_target/spec/armv7_linux_androideabi.rs
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@ -10,7 +10,7 @@ use crate::spec::{LinkerFlavor, Target, TargetOptions, TargetResult};
pub fn target() -> TargetResult {
let mut base = super::android_base::opts();
base.features = "+v7,+thumb-mode,+thumb2,+vfp3,+d16,-neon".to_string();
base.features = "+v7,+thumb-mode,+thumb2,+vfp3,-d32,-neon".to_string();
base.max_atomic_width = Some(64);
base.pre_link_args
.get_mut(&LinkerFlavor::Gcc).unwrap().push("-march=armv7-a".to_string());

2
src/librustc_target/spec/armv7_unknown_freebsd.rs
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@ -15,7 +15,7 @@ pub fn target() -> TargetResult {
linker_flavor: LinkerFlavor::Gcc,
options: TargetOptions {
features: "+v7,+vfp3,+d16,+thumb2,-neon".to_string(),
features: "+v7,+vfp3,-d32,+thumb2,-neon".to_string(),
max_atomic_width: Some(64),
abi_blacklist: super::arm_base::abi_blacklist(),
target_mcount: "\u{1}__gnu_mcount_nc".to_string(),

2
src/librustc_target/spec/armv7_unknown_linux_gnueabihf.rs
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@ -19,7 +19,7 @@ pub fn target() -> TargetResult {
options: TargetOptions {
// Info about features at https://wiki.debian.org/ArmHardFloatPort
features: "+v7,+vfp3,+d16,+thumb2,-neon".to_string(),
features: "+v7,+vfp3,-d32,+thumb2,-neon".to_string(),
cpu: "generic".to_string(),
max_atomic_width: Some(64),
abi_blacklist: super::arm_base::abi_blacklist(),

2
src/librustc_target/spec/armv7_unknown_linux_musleabihf.rs
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@ -22,7 +22,7 @@ pub fn target() -> TargetResult {
// Most of these settings are copied from the armv7_unknown_linux_gnueabihf
// target.
options: TargetOptions {
features: "+v7,+vfp3,+d16,+thumb2,-neon".to_string(),
features: "+v7,+vfp3,-d32,+thumb2,-neon".to_string(),
cpu: "generic".to_string(),
max_atomic_width: Some(64),
abi_blacklist: super::arm_base::abi_blacklist(),

2
src/librustc_target/spec/armv7_unknown_netbsd_eabihf.rs
View file

@ -15,7 +15,7 @@ pub fn target() -> TargetResult {
linker_flavor: LinkerFlavor::Gcc,
options: TargetOptions {
features: "+v7,+vfp3,+d16,+thumb2,-neon".to_string(),
features: "+v7,+vfp3,-d32,+thumb2,-neon".to_string(),
cpu: "generic".to_string(),
max_atomic_width: Some(64),
abi_blacklist: super::arm_base::abi_blacklist(),

2
src/librustc_target/spec/armv7r_none_eabihf.rs
View file

@ -21,7 +21,7 @@ pub fn target() -> TargetResult {
linker: Some("rust-lld".to_owned()),
relocation_model: "static".to_string(),
panic_strategy: PanicStrategy::Abort,
features: "+vfp3,+d16,+fp-only-sp".to_string(),
features: "+vfp3,-d32,-fp16".to_string(),
max_atomic_width: Some(32),
abi_blacklist: super::arm_base::abi_blacklist(),
emit_debug_gdb_scripts: false,

8
src/librustc_target/spec/thumbv7em_none_eabihf.rs
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@ -6,7 +6,7 @@
// Additionally, this target uses the "hard" floating convention (ABI) where floating point values
// are passed to/from subroutines via FPU registers (S0, S1, D0, D1, etc.).
//
// To opt into double precision hardware support, use the `-C target-feature=-fp-only-sp` flag.
// To opt into double precision hardware support, use the `-C target-feature=+fp64` flag.
use crate::spec::{LinkerFlavor, LldFlavor, Target, TargetOptions, TargetResult};
@ -26,14 +26,14 @@ pub fn target() -> TargetResult {
options: TargetOptions {
// `+vfp4` is the lowest common denominator between the Cortex-M4 (vfp4-16) and the
// Cortex-M7 (vfp5)
// `+d16` both the Cortex-M4 and the Cortex-M7 only have 16 double-precision registers
// `-d32` both the Cortex-M4 and the Cortex-M7 only have 16 double-precision registers
// available
// `+fp-only-sp` The Cortex-M4 only supports single precision floating point operations
// `-fp64` The Cortex-M4 only supports single precision floating point operations
// whereas in the Cortex-M7 double precision is optional
//
// Reference:
// ARMv7-M Architecture Reference Manual - A2.5 The optional floating-point extension
features: "+vfp4,+d16,+fp-only-sp".to_string(),
features: "+vfp4,-d32,-fp64".to_string(),
max_atomic_width: Some(32),
.. super::thumb_base::opts()
}

2
src/librustc_target/spec/thumbv8m_main_none_eabihf.rs
View file

@ -22,7 +22,7 @@ pub fn target() -> TargetResult {
// the FPU uses the FPv5 architecture, single-precision instructions
// and 16 D registers.
// These parameters map to the following LLVM features.
features: "+fp-armv8,+fp-only-sp,+d16".to_string(),
features: "+fp-armv8,-fp64,-d32".to_string(),
max_atomic_width: Some(32),
.. super::thumb_base::opts()
},