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Handle SysV64 abi

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bjorn3 2020-07-09 15:25:37 +02:00
parent ac77371852
commit 1987a3b6c0
1 changed files with 1 additions and 1 deletions
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src/abi/mod.rs
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@ -91,7 +91,7 @@ fn clif_sig_from_fn_sig<'tcx>(
}; };
let (call_conv, inputs, output): (CallConv, Vec<Ty<'tcx>>, Ty<'tcx>) = match abi { let (call_conv, inputs, output): (CallConv, Vec<Ty<'tcx>>, Ty<'tcx>) = match abi {
Abi::Rust => (CallConv::triple_default(triple), sig.inputs().to_vec(), sig.output()), Abi::Rust => (CallConv::triple_default(triple), sig.inputs().to_vec(), sig.output()),
Abi::C | Abi::Unadjusted => (CallConv::triple_default(triple), sig.inputs().to_vec(), sig.output()), Abi::C | Abi::Unadjusted | Abi::SysV64 => (CallConv::triple_default(triple), sig.inputs().to_vec(), sig.output()),
Abi::RustCall => { Abi::RustCall => {
assert_eq!(sig.inputs().len(), 2); assert_eq!(sig.inputs().len(), 2);
let extra_args = match sig.inputs().last().unwrap().kind { let extra_args = match sig.inputs().last().unwrap().kind {