From 1987a3b6c099e069368ac7caf30ea6d46595ca5f Mon Sep 17 00:00:00 2001
From: bjorn3 <bjorn3@users.noreply.github.com>
Date: Thu, 9 Jul 2020 15:25:37 +0200
Subject: [PATCH] Handle SysV64 abi

---
 src/abi/mod.rs | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/abi/mod.rs b/src/abi/mod.rs
index 2c1181c7575..2323dcc2083 100644
--- a/src/abi/mod.rs
+++ b/src/abi/mod.rs
@@ -91,7 +91,7 @@ fn clif_sig_from_fn_sig<'tcx>(
     };
     let (call_conv, inputs, output): (CallConv, Vec<Ty<'tcx>>, Ty<'tcx>) = match abi {
         Abi::Rust => (CallConv::triple_default(triple), sig.inputs().to_vec(), sig.output()),
-        Abi::C | Abi::Unadjusted => (CallConv::triple_default(triple), sig.inputs().to_vec(), sig.output()),
+        Abi::C | Abi::Unadjusted | Abi::SysV64 => (CallConv::triple_default(triple), sig.inputs().to_vec(), sig.output()),
         Abi::RustCall => {
             assert_eq!(sig.inputs().len(), 2);
             let extra_args = match sig.inputs().last().unwrap().kind {