llvm/mlir
Stephen Neuendorffer 628288658c [MLIR] Add RegionKindInterface
Some dialects have semantics which is not well represented by common
SSA structures with dominance constraints.  This patch allows
operations to declare the 'kind' of their contained regions.
Currently, two kinds are allowed: "SSACFG" and "Graph".  The only
difference between them at the moment is that SSACFG regions are
required to have dominance, while Graph regions are not required to
have dominance.  The intention is that this Interface would be
generated by ODS for existing operations, although this has not yet
been implemented. Presumably, if someone were interested in code
generation, we might also have a "CFG" dialect, which defines control
flow, but does not require SSA.

The new behavior is mostly identical to the previous behavior, since
registered operations without a RegionKindInterface are assumed to
contain SSACFG regions.  However, the behavior has changed for
unregistered operations.  Previously, these were checked for
dominance, however the new behavior allows dominance violations, in
order to allow the processing of unregistered dialects with Graph
regions.  One implication of this is that regions in unregistered
operations with more than one op are no longer CSE'd (since it
requires dominance info).

I've also reorganized the LangRef documentation to remove assertions
about "sequential execution", "SSA Values", and "Dominance".  Instead,
the core IR is simply "ordered" (i.e. totally ordered) and consists of
"Values".  I've also clarified some things about how control flow
passes between blocks in an SSACFG region. Control Flow must enter a
region at the entry block and follow terminator operation successors
or be returned to the containing op.  Graph regions do not define a
notion of control flow.

see discussion here:
https://llvm.discourse.group/t/rfc-allowing-dialects-to-relax-the-ssa-dominance-condition/833/53

Differential Revision: https://reviews.llvm.org/D80358
2020-07-15 14:27:05 -07:00
..
cmake/modules Install the MLIRTableGen static library. 2020-06-11 18:23:24 -07:00
docs [MLIR] Add RegionKindInterface 2020-07-15 14:27:05 -07:00
examples [MLIR] Add variadic isa<> for Type, Value, and Attribute 2020-06-29 15:04:48 -07:00
include [MLIR] Add RegionKindInterface 2020-07-15 14:27:05 -07:00
integration_test [mlir] Add alignment attribute to LLVM memory ops and use in vector.transfer 2020-07-13 17:35:20 -04:00
lib [MLIR] Add RegionKindInterface 2020-07-15 14:27:05 -07:00
test [MLIR] Add RegionKindInterface 2020-07-15 14:27:05 -07:00
tools [mlir] Add support for parsing optional Attribute values. 2020-07-14 13:14:59 -07:00
unittests [NFC] Fix comment style in MLIR unittests to conform to LLVM coding standards. 2020-07-12 07:27:02 -07:00
utils [mlir][NFC] Remove usernames and google bug numbers from TODO comments. 2020-07-07 01:40:52 -07:00
.clang-format
.clang-tidy
CMakeLists.txt Initial boiler-plate for python bindings. 2020-07-09 12:03:58 -07:00
LICENSE.TXT
README.md

Multi-Level Intermediate Representation

See https://mlir.llvm.org/ for more information.