0276db1416
The device runtime contains several calls to __kmpc_get_hardware_num_threads_in_block and __kmpc_get_hardware_num_blocks. If the thread_limit and the num_teams are constant, these calls can be folded to the constant value. In commit D106033 we have the optimization phase. This commit adds the attributes to the outlined function for the grid size. the two attributes are `omp_target_num_teams` and `omp_target_thread_limit`. These values are added as long as they are constant. Two functions are created `getNumThreadsExprForTargetDirective` and `getNumTeamsExprForTargetDirective`. The original functions `emitNumTeamsForTargetDirective` and `emitNumThreadsForTargetDirective` identify the expresion and emit the code. However, for the Device version of the outlined function, we cannot emit anything. Therefore, this is a first attempt to separate emision of code from deduction of the values. Reviewed By: jdoerfert Differential Revision: https://reviews.llvm.org/D106298
28459 lines
1.9 MiB
28459 lines
1.9 MiB
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _
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// Test host codegen.
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// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1
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// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
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// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK2
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// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK3
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// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
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// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK4
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// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=50 -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK5
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// RUN: %clang_cc1 -fopenmp -fopenmp-version=50 -DOMP5 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
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// RUN: %clang_cc1 -fopenmp -fopenmp-version=50 -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK6
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// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=50 -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK7
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// RUN: %clang_cc1 -fopenmp -fopenmp-version=50 -DOMP5 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
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// RUN: %clang_cc1 -fopenmp -fopenmp-version=50 -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK8
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// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9
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// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
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// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK10
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// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK11
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// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
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// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK12
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// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=50 -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK13
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// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -DOMP5 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
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// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK14
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// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=50 -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK15
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// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -DOMP5 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
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// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK16
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// Test target codegen - host bc file has to be created first.
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// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc
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// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK17
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// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s
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// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK18
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// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc
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// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK19
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// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s
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// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK20
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// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=50 -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc
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// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=50 -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK21
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// RUN: %clang_cc1 -fopenmp -fopenmp-version=50 -DOMP5 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s
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// RUN: %clang_cc1 -fopenmp -fopenmp-version=50 -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK22
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// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=50 -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc
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// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=50 -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK23
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// RUN: %clang_cc1 -fopenmp -fopenmp-version=50 -DOMP5 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s
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// RUN: %clang_cc1 -fopenmp -fopenmp-version=50 -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK24
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// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc
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// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK25
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// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s
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// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK26
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// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc
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// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK27
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// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s
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// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK28
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// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=50 -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc
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// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=50 -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK29
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// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -DOMP5 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s
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// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK30
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// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=50 -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc
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// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=50 -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK31
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// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -DOMP5 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s
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// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK32
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// expected-no-diagnostics
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#ifndef HEADER
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#define HEADER
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// We have 8 target regions, but only 7 that actually will generate offloading
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// code, only 6 will have mapped arguments, and only 4 have all-constant map
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// sizes.
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// Check target registration is registered as a Ctor.
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template<typename tx, typename ty>
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struct TT{
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tx X;
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ty Y;
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};
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long long get_val() { return 0; }
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int foo(int n) {
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int a = 0;
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short aa = 0;
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float b[10];
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float bn[n];
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double c[5][10];
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double cn[5][n];
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TT<long long, char> d;
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#pragma omp target parallel for simd nowait
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for (int i = 3; i < 32; i += 5) {
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}
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long long k = get_val();
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#pragma omp target parallel for simd if(target: 0) linear(k : 3) schedule(dynamic)
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for (int i = 10; i > 1; i--) {
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a += 1;
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}
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int lin = 12;
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#pragma omp target parallel for simd if(target: 1) linear(lin, a : get_val())
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for (unsigned long long it = 2000; it >= 600; it-=400) {
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aa += 1;
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}
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#pragma omp target parallel for simd if(target: n>10)
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for (short it = 6; it <= 20; it-=-4) {
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a += 1;
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aa += 1;
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}
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// We capture 3 VLA sizes in this target region
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// The names below are not necessarily consistent with the names used for the
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// addresses above as some are repeated.
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#pragma omp target parallel for simd if(target: n>20) schedule(static, a)
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for (unsigned char it = 'z'; it >= 'a'; it+=-1) {
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a += 1;
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b[2] += 1.0;
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bn[3] += 1.0;
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c[1][2] += 1.0;
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cn[1][3] += 1.0;
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d.X += 1;
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d.Y += 1;
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}
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return a;
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}
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// Check that the offloading functions are emitted and that the arguments are
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// correct and loaded correctly for the target regions in foo().
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// Create stack storage and store argument in there.
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// Create stack storage and store argument in there.
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// Create stack storage and store argument in there.
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// Create local storage for each capture.
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// To reduce complexity, we're only going as far as validating the signature of the outlined parallel function.
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template<typename tx>
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tx ftemplate(int n) {
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tx a = 0;
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short aa = 0;
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tx b[10];
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#pragma omp target parallel for simd if(target: n>40)
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for (long long i = -10; i < 10; i += 3) {
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a += 1;
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aa += 1;
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b[2] += 1;
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}
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return a;
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}
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static
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int fstatic(int n) {
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int a = 0;
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short aa = 0;
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char aaa = 0;
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int b[10];
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#pragma omp target parallel for simd if(target: n>50)
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for (unsigned i=100; i<10; i+=10) {
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a += 1;
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aa += 1;
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aaa += 1;
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b[2] += 1;
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}
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return a;
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}
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struct S1 {
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double a;
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int r1(int n){
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int b = n+1;
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short int c[2][n];
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#ifdef OMP5
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#pragma omp target parallel for simd if(n>60) nontemporal(a)
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#else
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#pragma omp target parallel for simd if(target: n>60)
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#endif // OMP5
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for (unsigned long long it = 2000; it >= 600; it -= 400) {
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this->a = (double)b + 1.5;
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c[1][1] = ++a;
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}
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return c[1][1] + (int)b;
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}
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};
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int bar(int n){
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int a = 0;
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a += foo(n);
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S1 S;
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a += S.r1(n);
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a += fstatic(n);
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a += ftemplate<int>(n);
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return a;
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}
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// We capture 2 VLA sizes in this target region
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// The names below are not necessarily consistent with the names used for the
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// addresses above as some are repeated.
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// Check that the offloading functions are emitted and that the arguments are
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// correct and loaded correctly for the target regions of the callees of bar().
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// Create local storage for each capture.
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// Store captures in the context.
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// To reduce complexity, we're only going as far as validating the signature of the outlined parallel function.
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// Create local storage for each capture.
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// Store captures in the context.
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// To reduce complexity, we're only going as far as validating the signature of the outlined parallel function.
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// Create local storage for each capture.
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// Store captures in the context.
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// To reduce complexity, we're only going as far as validating the signature of the outlined parallel function.
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#endif
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// CHECK1-LABEL: define {{[^@]+}}@_Z7get_valv
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// CHECK1-SAME: () #[[ATTR0:[0-9]+]] {
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// CHECK1-NEXT: entry:
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// CHECK1-NEXT: ret i64 0
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//
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//
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// CHECK1-LABEL: define {{[^@]+}}@_Z3fooi
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// CHECK1-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
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// CHECK1-NEXT: entry:
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// CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
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// CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4
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// CHECK1-NEXT: [[AA:%.*]] = alloca i16, align 2
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// CHECK1-NEXT: [[B:%.*]] = alloca [10 x float], align 4
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// CHECK1-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8
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// CHECK1-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8
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// CHECK1-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8
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// CHECK1-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8
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// CHECK1-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8
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// CHECK1-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 1
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// CHECK1-NEXT: [[K:%.*]] = alloca i64, align 8
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// CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
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// CHECK1-NEXT: [[K_CASTED:%.*]] = alloca i64, align 8
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// CHECK1-NEXT: [[LIN:%.*]] = alloca i32, align 4
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// CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
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// CHECK1-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8
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// CHECK1-NEXT: [[A_CASTED4:%.*]] = alloca i64, align 8
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// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8
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// CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8
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// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8
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// CHECK1-NEXT: [[A_CASTED6:%.*]] = alloca i64, align 8
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// CHECK1-NEXT: [[AA_CASTED8:%.*]] = alloca i64, align 8
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// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS10:%.*]] = alloca [2 x i8*], align 8
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// CHECK1-NEXT: [[DOTOFFLOAD_PTRS11:%.*]] = alloca [2 x i8*], align 8
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// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS12:%.*]] = alloca [2 x i8*], align 8
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// CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
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// CHECK1-NEXT: [[A_CASTED15:%.*]] = alloca i64, align 8
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// CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
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// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS20:%.*]] = alloca [10 x i8*], align 8
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// CHECK1-NEXT: [[DOTOFFLOAD_PTRS21:%.*]] = alloca [10 x i8*], align 8
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// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS22:%.*]] = alloca [10 x i8*], align 8
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// CHECK1-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 8
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// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]])
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// CHECK1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
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// CHECK1-NEXT: store i32 0, i32* [[A]], align 4
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// CHECK1-NEXT: store i16 0, i16* [[AA]], align 2
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// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
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// CHECK1-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
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// CHECK1-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave()
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// CHECK1-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8
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// CHECK1-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP2]], align 4
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// CHECK1-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8
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// CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
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// CHECK1-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64
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// CHECK1-NEXT: [[TMP6:%.*]] = mul nuw i64 5, [[TMP5]]
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// CHECK1-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP6]], align 8
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// CHECK1-NEXT: store i64 [[TMP5]], i64* [[__VLA_EXPR1]], align 8
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// CHECK1-NEXT: [[TMP7:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 1, i64 40, i64 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1)
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// CHECK1-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.kmp_task_t_with_privates*
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// CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP8]], i32 0, i32 0
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// CHECK1-NEXT: [[TMP10:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i8* [[TMP7]])
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// CHECK1-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv()
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// CHECK1-NEXT: store i64 [[CALL]], i64* [[K]], align 8
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// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[A]], align 4
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// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32*
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// CHECK1-NEXT: store i32 [[TMP11]], i32* [[CONV]], align 4
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// CHECK1-NEXT: [[TMP12:%.*]] = load i64, i64* [[A_CASTED]], align 8
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// CHECK1-NEXT: [[TMP13:%.*]] = load i64, i64* [[K]], align 8
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// CHECK1-NEXT: store i64 [[TMP13]], i64* [[K_CASTED]], align 8
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// CHECK1-NEXT: [[TMP14:%.*]] = load i64, i64* [[K_CASTED]], align 8
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// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101(i64 [[TMP12]], i64 [[TMP14]]) #[[ATTR4:[0-9]+]]
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// CHECK1-NEXT: store i32 12, i32* [[LIN]], align 4
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// CHECK1-NEXT: [[TMP15:%.*]] = load i16, i16* [[AA]], align 2
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// CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
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// CHECK1-NEXT: store i16 [[TMP15]], i16* [[CONV2]], align 2
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// CHECK1-NEXT: [[TMP16:%.*]] = load i64, i64* [[AA_CASTED]], align 8
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// CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[LIN]], align 4
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// CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[LIN_CASTED]] to i32*
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// CHECK1-NEXT: store i32 [[TMP17]], i32* [[CONV3]], align 4
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// CHECK1-NEXT: [[TMP18:%.*]] = load i64, i64* [[LIN_CASTED]], align 8
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// CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[A]], align 4
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// CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED4]] to i32*
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// CHECK1-NEXT: store i32 [[TMP19]], i32* [[CONV5]], align 4
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// CHECK1-NEXT: [[TMP20:%.*]] = load i64, i64* [[A_CASTED4]], align 8
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// CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
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// CHECK1-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i64*
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// CHECK1-NEXT: store i64 [[TMP16]], i64* [[TMP22]], align 8
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// CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
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// CHECK1-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i64*
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// CHECK1-NEXT: store i64 [[TMP16]], i64* [[TMP24]], align 8
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// CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
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// CHECK1-NEXT: store i8* null, i8** [[TMP25]], align 8
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// CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
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// CHECK1-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64*
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// CHECK1-NEXT: store i64 [[TMP18]], i64* [[TMP27]], align 8
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// CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
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// CHECK1-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i64*
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// CHECK1-NEXT: store i64 [[TMP18]], i64* [[TMP29]], align 8
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// CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
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// CHECK1-NEXT: store i8* null, i8** [[TMP30]], align 8
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// CHECK1-NEXT: [[TMP31:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
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// CHECK1-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i64*
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// CHECK1-NEXT: store i64 [[TMP20]], i64* [[TMP32]], align 8
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// CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
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// CHECK1-NEXT: [[TMP34:%.*]] = bitcast i8** [[TMP33]] to i64*
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// CHECK1-NEXT: store i64 [[TMP20]], i64* [[TMP34]], align 8
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// CHECK1-NEXT: [[TMP35:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
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// CHECK1-NEXT: store i8* null, i8** [[TMP35]], align 8
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// CHECK1-NEXT: [[TMP36:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
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// CHECK1-NEXT: [[TMP37:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
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// CHECK1-NEXT: [[TMP38:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108.region_id, i32 3, i8** [[TMP36]], i8** [[TMP37]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
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// CHECK1-NEXT: [[TMP39:%.*]] = icmp ne i32 [[TMP38]], 0
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// CHECK1-NEXT: br i1 [[TMP39]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
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// CHECK1: omp_offload.failed:
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// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108(i64 [[TMP16]], i64 [[TMP18]], i64 [[TMP20]]) #[[ATTR4]]
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// CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]]
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// CHECK1: omp_offload.cont:
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// CHECK1-NEXT: [[TMP40:%.*]] = load i32, i32* [[A]], align 4
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// CHECK1-NEXT: [[CONV7:%.*]] = bitcast i64* [[A_CASTED6]] to i32*
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// CHECK1-NEXT: store i32 [[TMP40]], i32* [[CONV7]], align 4
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// CHECK1-NEXT: [[TMP41:%.*]] = load i64, i64* [[A_CASTED6]], align 8
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// CHECK1-NEXT: [[TMP42:%.*]] = load i16, i16* [[AA]], align 2
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// CHECK1-NEXT: [[CONV9:%.*]] = bitcast i64* [[AA_CASTED8]] to i16*
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// CHECK1-NEXT: store i16 [[TMP42]], i16* [[CONV9]], align 2
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// CHECK1-NEXT: [[TMP43:%.*]] = load i64, i64* [[AA_CASTED8]], align 8
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// CHECK1-NEXT: [[TMP44:%.*]] = load i32, i32* [[N_ADDR]], align 4
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// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP44]], 10
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// CHECK1-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
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// CHECK1: omp_if.then:
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// CHECK1-NEXT: [[TMP45:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 0
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// CHECK1-NEXT: [[TMP46:%.*]] = bitcast i8** [[TMP45]] to i64*
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// CHECK1-NEXT: store i64 [[TMP41]], i64* [[TMP46]], align 8
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// CHECK1-NEXT: [[TMP47:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS11]], i32 0, i32 0
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// CHECK1-NEXT: [[TMP48:%.*]] = bitcast i8** [[TMP47]] to i64*
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// CHECK1-NEXT: store i64 [[TMP41]], i64* [[TMP48]], align 8
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// CHECK1-NEXT: [[TMP49:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS12]], i64 0, i64 0
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// CHECK1-NEXT: store i8* null, i8** [[TMP49]], align 8
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// CHECK1-NEXT: [[TMP50:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 1
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// CHECK1-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP50]] to i64*
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// CHECK1-NEXT: store i64 [[TMP43]], i64* [[TMP51]], align 8
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// CHECK1-NEXT: [[TMP52:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS11]], i32 0, i32 1
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// CHECK1-NEXT: [[TMP53:%.*]] = bitcast i8** [[TMP52]] to i64*
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// CHECK1-NEXT: store i64 [[TMP43]], i64* [[TMP53]], align 8
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// CHECK1-NEXT: [[TMP54:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS12]], i64 0, i64 1
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// CHECK1-NEXT: store i8* null, i8** [[TMP54]], align 8
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// CHECK1-NEXT: [[TMP55:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 0
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// CHECK1-NEXT: [[TMP56:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS11]], i32 0, i32 0
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// CHECK1-NEXT: [[TMP57:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116.region_id, i32 2, i8** [[TMP55]], i8** [[TMP56]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
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// CHECK1-NEXT: [[TMP58:%.*]] = icmp ne i32 [[TMP57]], 0
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// CHECK1-NEXT: br i1 [[TMP58]], label [[OMP_OFFLOAD_FAILED13:%.*]], label [[OMP_OFFLOAD_CONT14:%.*]]
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|
// CHECK1: omp_offload.failed13:
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// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116(i64 [[TMP41]], i64 [[TMP43]]) #[[ATTR4]]
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// CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT14]]
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// CHECK1: omp_offload.cont14:
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// CHECK1-NEXT: br label [[OMP_IF_END:%.*]]
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|
// CHECK1: omp_if.else:
|
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// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116(i64 [[TMP41]], i64 [[TMP43]]) #[[ATTR4]]
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// CHECK1-NEXT: br label [[OMP_IF_END]]
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|
// CHECK1: omp_if.end:
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|
// CHECK1-NEXT: [[TMP59:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK1-NEXT: store i32 [[TMP59]], i32* [[DOTCAPTURE_EXPR_]], align 4
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|
// CHECK1-NEXT: [[TMP60:%.*]] = load i32, i32* [[A]], align 4
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|
// CHECK1-NEXT: [[CONV16:%.*]] = bitcast i64* [[A_CASTED15]] to i32*
|
|
// CHECK1-NEXT: store i32 [[TMP60]], i32* [[CONV16]], align 4
|
|
// CHECK1-NEXT: [[TMP61:%.*]] = load i64, i64* [[A_CASTED15]], align 8
|
|
// CHECK1-NEXT: [[TMP62:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK1-NEXT: [[CONV17:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
|
|
// CHECK1-NEXT: store i32 [[TMP62]], i32* [[CONV17]], align 4
|
|
// CHECK1-NEXT: [[TMP63:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
|
|
// CHECK1-NEXT: [[TMP64:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK1-NEXT: [[CMP18:%.*]] = icmp sgt i32 [[TMP64]], 20
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|
// CHECK1-NEXT: br i1 [[CMP18]], label [[OMP_IF_THEN19:%.*]], label [[OMP_IF_ELSE25:%.*]]
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|
// CHECK1: omp_if.then19:
|
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// CHECK1-NEXT: [[TMP65:%.*]] = mul nuw i64 [[TMP2]], 4
|
|
// CHECK1-NEXT: [[TMP66:%.*]] = mul nuw i64 5, [[TMP5]]
|
|
// CHECK1-NEXT: [[TMP67:%.*]] = mul nuw i64 [[TMP66]], 8
|
|
// CHECK1-NEXT: [[TMP68:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[TMP69:%.*]] = bitcast i8** [[TMP68]] to i64*
|
|
// CHECK1-NEXT: store i64 [[TMP61]], i64* [[TMP69]], align 8
|
|
// CHECK1-NEXT: [[TMP70:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[TMP71:%.*]] = bitcast i8** [[TMP70]] to i64*
|
|
// CHECK1-NEXT: store i64 [[TMP61]], i64* [[TMP71]], align 8
|
|
// CHECK1-NEXT: [[TMP72:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
|
|
// CHECK1-NEXT: store i64 4, i64* [[TMP72]], align 8
|
|
// CHECK1-NEXT: [[TMP73:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 0
|
|
// CHECK1-NEXT: store i8* null, i8** [[TMP73]], align 8
|
|
// CHECK1-NEXT: [[TMP74:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 1
|
|
// CHECK1-NEXT: [[TMP75:%.*]] = bitcast i8** [[TMP74]] to [10 x float]**
|
|
// CHECK1-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP75]], align 8
|
|
// CHECK1-NEXT: [[TMP76:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 1
|
|
// CHECK1-NEXT: [[TMP77:%.*]] = bitcast i8** [[TMP76]] to [10 x float]**
|
|
// CHECK1-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP77]], align 8
|
|
// CHECK1-NEXT: [[TMP78:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1
|
|
// CHECK1-NEXT: store i64 40, i64* [[TMP78]], align 8
|
|
// CHECK1-NEXT: [[TMP79:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 1
|
|
// CHECK1-NEXT: store i8* null, i8** [[TMP79]], align 8
|
|
// CHECK1-NEXT: [[TMP80:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 2
|
|
// CHECK1-NEXT: [[TMP81:%.*]] = bitcast i8** [[TMP80]] to i64*
|
|
// CHECK1-NEXT: store i64 [[TMP2]], i64* [[TMP81]], align 8
|
|
// CHECK1-NEXT: [[TMP82:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 2
|
|
// CHECK1-NEXT: [[TMP83:%.*]] = bitcast i8** [[TMP82]] to i64*
|
|
// CHECK1-NEXT: store i64 [[TMP2]], i64* [[TMP83]], align 8
|
|
// CHECK1-NEXT: [[TMP84:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2
|
|
// CHECK1-NEXT: store i64 8, i64* [[TMP84]], align 8
|
|
// CHECK1-NEXT: [[TMP85:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 2
|
|
// CHECK1-NEXT: store i8* null, i8** [[TMP85]], align 8
|
|
// CHECK1-NEXT: [[TMP86:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 3
|
|
// CHECK1-NEXT: [[TMP87:%.*]] = bitcast i8** [[TMP86]] to float**
|
|
// CHECK1-NEXT: store float* [[VLA]], float** [[TMP87]], align 8
|
|
// CHECK1-NEXT: [[TMP88:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 3
|
|
// CHECK1-NEXT: [[TMP89:%.*]] = bitcast i8** [[TMP88]] to float**
|
|
// CHECK1-NEXT: store float* [[VLA]], float** [[TMP89]], align 8
|
|
// CHECK1-NEXT: [[TMP90:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3
|
|
// CHECK1-NEXT: store i64 [[TMP65]], i64* [[TMP90]], align 8
|
|
// CHECK1-NEXT: [[TMP91:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 3
|
|
// CHECK1-NEXT: store i8* null, i8** [[TMP91]], align 8
|
|
// CHECK1-NEXT: [[TMP92:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 4
|
|
// CHECK1-NEXT: [[TMP93:%.*]] = bitcast i8** [[TMP92]] to [5 x [10 x double]]**
|
|
// CHECK1-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP93]], align 8
|
|
// CHECK1-NEXT: [[TMP94:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 4
|
|
// CHECK1-NEXT: [[TMP95:%.*]] = bitcast i8** [[TMP94]] to [5 x [10 x double]]**
|
|
// CHECK1-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP95]], align 8
|
|
// CHECK1-NEXT: [[TMP96:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4
|
|
// CHECK1-NEXT: store i64 400, i64* [[TMP96]], align 8
|
|
// CHECK1-NEXT: [[TMP97:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 4
|
|
// CHECK1-NEXT: store i8* null, i8** [[TMP97]], align 8
|
|
// CHECK1-NEXT: [[TMP98:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 5
|
|
// CHECK1-NEXT: [[TMP99:%.*]] = bitcast i8** [[TMP98]] to i64*
|
|
// CHECK1-NEXT: store i64 5, i64* [[TMP99]], align 8
|
|
// CHECK1-NEXT: [[TMP100:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 5
|
|
// CHECK1-NEXT: [[TMP101:%.*]] = bitcast i8** [[TMP100]] to i64*
|
|
// CHECK1-NEXT: store i64 5, i64* [[TMP101]], align 8
|
|
// CHECK1-NEXT: [[TMP102:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 5
|
|
// CHECK1-NEXT: store i64 8, i64* [[TMP102]], align 8
|
|
// CHECK1-NEXT: [[TMP103:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 5
|
|
// CHECK1-NEXT: store i8* null, i8** [[TMP103]], align 8
|
|
// CHECK1-NEXT: [[TMP104:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 6
|
|
// CHECK1-NEXT: [[TMP105:%.*]] = bitcast i8** [[TMP104]] to i64*
|
|
// CHECK1-NEXT: store i64 [[TMP5]], i64* [[TMP105]], align 8
|
|
// CHECK1-NEXT: [[TMP106:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 6
|
|
// CHECK1-NEXT: [[TMP107:%.*]] = bitcast i8** [[TMP106]] to i64*
|
|
// CHECK1-NEXT: store i64 [[TMP5]], i64* [[TMP107]], align 8
|
|
// CHECK1-NEXT: [[TMP108:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 6
|
|
// CHECK1-NEXT: store i64 8, i64* [[TMP108]], align 8
|
|
// CHECK1-NEXT: [[TMP109:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 6
|
|
// CHECK1-NEXT: store i8* null, i8** [[TMP109]], align 8
|
|
// CHECK1-NEXT: [[TMP110:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 7
|
|
// CHECK1-NEXT: [[TMP111:%.*]] = bitcast i8** [[TMP110]] to double**
|
|
// CHECK1-NEXT: store double* [[VLA1]], double** [[TMP111]], align 8
|
|
// CHECK1-NEXT: [[TMP112:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 7
|
|
// CHECK1-NEXT: [[TMP113:%.*]] = bitcast i8** [[TMP112]] to double**
|
|
// CHECK1-NEXT: store double* [[VLA1]], double** [[TMP113]], align 8
|
|
// CHECK1-NEXT: [[TMP114:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7
|
|
// CHECK1-NEXT: store i64 [[TMP67]], i64* [[TMP114]], align 8
|
|
// CHECK1-NEXT: [[TMP115:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 7
|
|
// CHECK1-NEXT: store i8* null, i8** [[TMP115]], align 8
|
|
// CHECK1-NEXT: [[TMP116:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 8
|
|
// CHECK1-NEXT: [[TMP117:%.*]] = bitcast i8** [[TMP116]] to %struct.TT**
|
|
// CHECK1-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP117]], align 8
|
|
// CHECK1-NEXT: [[TMP118:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 8
|
|
// CHECK1-NEXT: [[TMP119:%.*]] = bitcast i8** [[TMP118]] to %struct.TT**
|
|
// CHECK1-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP119]], align 8
|
|
// CHECK1-NEXT: [[TMP120:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 8
|
|
// CHECK1-NEXT: store i64 16, i64* [[TMP120]], align 8
|
|
// CHECK1-NEXT: [[TMP121:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 8
|
|
// CHECK1-NEXT: store i8* null, i8** [[TMP121]], align 8
|
|
// CHECK1-NEXT: [[TMP122:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 9
|
|
// CHECK1-NEXT: [[TMP123:%.*]] = bitcast i8** [[TMP122]] to i64*
|
|
// CHECK1-NEXT: store i64 [[TMP63]], i64* [[TMP123]], align 8
|
|
// CHECK1-NEXT: [[TMP124:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 9
|
|
// CHECK1-NEXT: [[TMP125:%.*]] = bitcast i8** [[TMP124]] to i64*
|
|
// CHECK1-NEXT: store i64 [[TMP63]], i64* [[TMP125]], align 8
|
|
// CHECK1-NEXT: [[TMP126:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 9
|
|
// CHECK1-NEXT: store i64 4, i64* [[TMP126]], align 8
|
|
// CHECK1-NEXT: [[TMP127:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 9
|
|
// CHECK1-NEXT: store i8* null, i8** [[TMP127]], align 8
|
|
// CHECK1-NEXT: [[TMP128:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[TMP129:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[TMP130:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[TMP131:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140.region_id, i32 10, i8** [[TMP128]], i8** [[TMP129]], i64* [[TMP130]], i64* getelementptr inbounds ([10 x i64], [10 x i64]* @.offload_maptypes.8, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
|
|
// CHECK1-NEXT: [[TMP132:%.*]] = icmp ne i32 [[TMP131]], 0
|
|
// CHECK1-NEXT: br i1 [[TMP132]], label [[OMP_OFFLOAD_FAILED23:%.*]], label [[OMP_OFFLOAD_CONT24:%.*]]
|
|
// CHECK1: omp_offload.failed23:
|
|
// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140(i64 [[TMP61]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]], i64 [[TMP63]]) #[[ATTR4]]
|
|
// CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT24]]
|
|
// CHECK1: omp_offload.cont24:
|
|
// CHECK1-NEXT: br label [[OMP_IF_END26:%.*]]
|
|
// CHECK1: omp_if.else25:
|
|
// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140(i64 [[TMP61]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]], i64 [[TMP63]]) #[[ATTR4]]
|
|
// CHECK1-NEXT: br label [[OMP_IF_END26]]
|
|
// CHECK1: omp_if.end26:
|
|
// CHECK1-NEXT: [[TMP133:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK1-NEXT: [[TMP134:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
|
|
// CHECK1-NEXT: call void @llvm.stackrestore(i8* [[TMP134]])
|
|
// CHECK1-NEXT: ret i32 [[TMP133]]
|
|
//
|
|
//
|
|
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96
|
|
// CHECK1-SAME: () #[[ATTR2:[0-9]+]] {
|
|
// CHECK1-NEXT: entry:
|
|
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
|
|
// CHECK1-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined.
|
|
// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] {
|
|
// CHECK1-NEXT: entry:
|
|
// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK1-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
|
|
// CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
|
|
// CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5
|
|
// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK1: cond.true:
|
|
// CHECK1-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK1: cond.false:
|
|
// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK1-NEXT: br label [[COND_END]]
|
|
// CHECK1: cond.end:
|
|
// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
|
|
// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK1: omp.inner.for.cond:
|
|
// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
|
|
// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !10
|
|
// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
|
|
// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK1: omp.inner.for.body:
|
|
// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
|
|
// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5
|
|
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]]
|
|
// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10
|
|
// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK1: omp.body.continue:
|
|
// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK1: omp.inner.for.inc:
|
|
// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
|
|
// CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
|
|
// CHECK1-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
|
|
// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]
|
|
// CHECK1: omp.inner.for.end:
|
|
// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK1: omp.loop.exit:
|
|
// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
|
|
// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK1-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0
|
|
// CHECK1-NEXT: br i1 [[TMP10]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
|
|
// CHECK1: .omp.final.then:
|
|
// CHECK1-NEXT: store i32 33, i32* [[I]], align 4
|
|
// CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]]
|
|
// CHECK1: .omp.final.done:
|
|
// CHECK1-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK1-LABEL: define {{[^@]+}}@.omp_task_entry.
|
|
// CHECK1-SAME: (i32 signext [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] {
|
|
// CHECK1-NEXT: entry:
|
|
// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8
|
|
// CHECK1-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8
|
|
// CHECK1-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8
|
|
// CHECK1-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8
|
|
// CHECK1-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 8
|
|
// CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8
|
|
// CHECK1-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4
|
|
// CHECK1-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8
|
|
// CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4
|
|
// CHECK1-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8
|
|
// CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
|
|
// CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8
|
|
// CHECK1-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon*
|
|
// CHECK1-NEXT: [[TMP9:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8*
|
|
// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META16:![0-9]+]])
|
|
// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]])
|
|
// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META21:![0-9]+]])
|
|
// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META23:![0-9]+]])
|
|
// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !25
|
|
// CHECK1-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !25
|
|
// CHECK1-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !25
|
|
// CHECK1-NEXT: store void (i8*, ...)* null, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !25
|
|
// CHECK1-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !25
|
|
// CHECK1-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !25
|
|
// CHECK1-NEXT: [[TMP10:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !25
|
|
// CHECK1-NEXT: [[TMP11:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 0, i32 0, i8* null, i32 0, i8* null) #[[ATTR4]]
|
|
// CHECK1-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
|
|
// CHECK1-NEXT: br i1 [[TMP12]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]]
|
|
// CHECK1: omp_offload.failed.i:
|
|
// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96() #[[ATTR4]]
|
|
// CHECK1-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]]
|
|
// CHECK1: .omp_outlined..1.exit:
|
|
// CHECK1-NEXT: ret i32 0
|
|
//
|
|
//
|
|
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101
|
|
// CHECK1-SAME: (i64 [[A:%.*]], i64 [[K:%.*]]) #[[ATTR3]] {
|
|
// CHECK1-NEXT: entry:
|
|
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[K_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[K_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK1-NEXT: store i64 [[K]], i64* [[K_ADDR]], align 8
|
|
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
|
|
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32*
|
|
// CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
|
|
// CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
|
|
// CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[K_ADDR]], align 8
|
|
// CHECK1-NEXT: store i64 [[TMP2]], i64* [[K_CASTED]], align 8
|
|
// CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[K_CASTED]], align 8
|
|
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
|
|
// CHECK1-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..2
|
|
// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[K:%.*]]) #[[ATTR3]] {
|
|
// CHECK1-NEXT: entry:
|
|
// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[K_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[DOTLINEAR_START:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[K1:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK1-NEXT: store i64 [[K]], i64* [[K_ADDR]], align 8
|
|
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK1-NEXT: [[TMP0:%.*]] = load i64, i64* [[K_ADDR]], align 8
|
|
// CHECK1-NEXT: store i64 [[TMP0]], i64* [[DOTLINEAR_START]], align 8
|
|
// CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK1-NEXT: store i32 8, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK1-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
|
|
// CHECK1-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP2]])
|
|
// CHECK1-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32 35, i32 0, i32 8, i32 1, i32 1)
|
|
// CHECK1-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
|
|
// CHECK1: omp.dispatch.cond:
|
|
// CHECK1-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
|
|
// CHECK1-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP3]], 0
|
|
// CHECK1-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
|
|
// CHECK1: omp.dispatch.body:
|
|
// CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK1: omp.inner.for.cond:
|
|
// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !26
|
|
// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !26
|
|
// CHECK1-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
|
|
// CHECK1-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK1: omp.inner.for.body:
|
|
// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !26
|
|
// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
|
|
// CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL]]
|
|
// CHECK1-NEXT: store i32 [[SUB]], i32* [[I]], align 4, !llvm.access.group !26
|
|
// CHECK1-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8, !llvm.access.group !26
|
|
// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !26
|
|
// CHECK1-NEXT: [[MUL2:%.*]] = mul nsw i32 [[TMP9]], 3
|
|
// CHECK1-NEXT: [[CONV3:%.*]] = sext i32 [[MUL2]] to i64
|
|
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP8]], [[CONV3]]
|
|
// CHECK1-NEXT: store i64 [[ADD]], i64* [[K1]], align 8, !llvm.access.group !26
|
|
// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !26
|
|
// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], 1
|
|
// CHECK1-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 8, !llvm.access.group !26
|
|
// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK1: omp.body.continue:
|
|
// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK1: omp.inner.for.inc:
|
|
// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !26
|
|
// CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1
|
|
// CHECK1-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !26
|
|
// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP27:![0-9]+]]
|
|
// CHECK1: omp.inner.for.end:
|
|
// CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
|
|
// CHECK1: omp.dispatch.inc:
|
|
// CHECK1-NEXT: br label [[OMP_DISPATCH_COND]]
|
|
// CHECK1: omp.dispatch.end:
|
|
// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK1-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0
|
|
// CHECK1-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
|
|
// CHECK1: .omp.final.then:
|
|
// CHECK1-NEXT: store i32 1, i32* [[I]], align 4
|
|
// CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]]
|
|
// CHECK1: .omp.final.done:
|
|
// CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK1-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0
|
|
// CHECK1-NEXT: br i1 [[TMP15]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
|
|
// CHECK1: .omp.linear.pu:
|
|
// CHECK1-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8
|
|
// CHECK1-NEXT: [[ADD6:%.*]] = add nsw i64 [[TMP16]], 27
|
|
// CHECK1-NEXT: store i64 [[ADD6]], i64* [[K_ADDR]], align 8
|
|
// CHECK1-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]]
|
|
// CHECK1: .omp.linear.pu.done:
|
|
// CHECK1-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108
|
|
// CHECK1-SAME: (i64 [[AA:%.*]], i64 [[LIN:%.*]], i64 [[A:%.*]]) #[[ATTR2]] {
|
|
// CHECK1-NEXT: entry:
|
|
// CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
|
|
// CHECK1-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8
|
|
// CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
|
|
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32*
|
|
// CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK1-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8
|
|
// CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
|
|
// CHECK1-NEXT: store i16 [[TMP0]], i16* [[CONV3]], align 2
|
|
// CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
|
|
// CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8
|
|
// CHECK1-NEXT: [[CONV4:%.*]] = bitcast i64* [[LIN_CASTED]] to i32*
|
|
// CHECK1-NEXT: store i32 [[TMP2]], i32* [[CONV4]], align 4
|
|
// CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[LIN_CASTED]], align 8
|
|
// CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV2]], align 8
|
|
// CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
|
|
// CHECK1-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4
|
|
// CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[A_CASTED]], align 8
|
|
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]])
|
|
// CHECK1-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..3
|
|
// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]], i64 [[LIN:%.*]], i64 [[A:%.*]]) #[[ATTR3]] {
|
|
// CHECK1-NEXT: entry:
|
|
// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[TMP:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[DOTLINEAR_START3:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[IT:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[LIN4:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[A5:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
|
|
// CHECK1-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8
|
|
// CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
|
|
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32*
|
|
// CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV1]], align 8
|
|
// CHECK1-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4
|
|
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 8
|
|
// CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START3]], align 4
|
|
// CHECK1-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv()
|
|
// CHECK1-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8
|
|
// CHECK1-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK1-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK1-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
|
|
// CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK1-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
|
|
// CHECK1-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3]], i32 [[TMP3]])
|
|
// CHECK1-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
|
|
// CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK1-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3
|
|
// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK1: cond.true:
|
|
// CHECK1-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK1: cond.false:
|
|
// CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK1-NEXT: br label [[COND_END]]
|
|
// CHECK1: cond.end:
|
|
// CHECK1-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
|
|
// CHECK1-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
|
|
// CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK1-NEXT: store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK1: omp.inner.for.cond:
|
|
// CHECK1-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !29
|
|
// CHECK1-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !29
|
|
// CHECK1-NEXT: [[CMP6:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]]
|
|
// CHECK1-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK1: omp.inner.for.body:
|
|
// CHECK1-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !29
|
|
// CHECK1-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400
|
|
// CHECK1-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]
|
|
// CHECK1-NEXT: store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !29
|
|
// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4, !llvm.access.group !29
|
|
// CHECK1-NEXT: [[CONV7:%.*]] = sext i32 [[TMP10]] to i64
|
|
// CHECK1-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !29
|
|
// CHECK1-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !29
|
|
// CHECK1-NEXT: [[MUL8:%.*]] = mul i64 [[TMP11]], [[TMP12]]
|
|
// CHECK1-NEXT: [[ADD:%.*]] = add i64 [[CONV7]], [[MUL8]]
|
|
// CHECK1-NEXT: [[CONV9:%.*]] = trunc i64 [[ADD]] to i32
|
|
// CHECK1-NEXT: store i32 [[CONV9]], i32* [[LIN4]], align 4, !llvm.access.group !29
|
|
// CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START3]], align 4, !llvm.access.group !29
|
|
// CHECK1-NEXT: [[CONV10:%.*]] = sext i32 [[TMP13]] to i64
|
|
// CHECK1-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !29
|
|
// CHECK1-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !29
|
|
// CHECK1-NEXT: [[MUL11:%.*]] = mul i64 [[TMP14]], [[TMP15]]
|
|
// CHECK1-NEXT: [[ADD12:%.*]] = add i64 [[CONV10]], [[MUL11]]
|
|
// CHECK1-NEXT: [[CONV13:%.*]] = trunc i64 [[ADD12]] to i32
|
|
// CHECK1-NEXT: store i32 [[CONV13]], i32* [[A5]], align 4, !llvm.access.group !29
|
|
// CHECK1-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 8, !llvm.access.group !29
|
|
// CHECK1-NEXT: [[CONV14:%.*]] = sext i16 [[TMP16]] to i32
|
|
// CHECK1-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1
|
|
// CHECK1-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16
|
|
// CHECK1-NEXT: store i16 [[CONV16]], i16* [[CONV]], align 8, !llvm.access.group !29
|
|
// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK1: omp.body.continue:
|
|
// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK1: omp.inner.for.inc:
|
|
// CHECK1-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !29
|
|
// CHECK1-NEXT: [[ADD17:%.*]] = add i64 [[TMP17]], 1
|
|
// CHECK1-NEXT: store i64 [[ADD17]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !29
|
|
// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP30:![0-9]+]]
|
|
// CHECK1: omp.inner.for.end:
|
|
// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK1: omp.loop.exit:
|
|
// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
|
|
// CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK1-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
|
|
// CHECK1-NEXT: br i1 [[TMP19]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
|
|
// CHECK1: .omp.final.then:
|
|
// CHECK1-NEXT: store i64 400, i64* [[IT]], align 8
|
|
// CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]]
|
|
// CHECK1: .omp.final.done:
|
|
// CHECK1-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK1-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0
|
|
// CHECK1-NEXT: br i1 [[TMP21]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
|
|
// CHECK1: .omp.linear.pu:
|
|
// CHECK1-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4
|
|
// CHECK1-NEXT: [[CONV18:%.*]] = sext i32 [[TMP22]] to i64
|
|
// CHECK1-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
|
|
// CHECK1-NEXT: [[MUL19:%.*]] = mul i64 4, [[TMP23]]
|
|
// CHECK1-NEXT: [[ADD20:%.*]] = add i64 [[CONV18]], [[MUL19]]
|
|
// CHECK1-NEXT: [[CONV21:%.*]] = trunc i64 [[ADD20]] to i32
|
|
// CHECK1-NEXT: store i32 [[CONV21]], i32* [[CONV1]], align 8
|
|
// CHECK1-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTLINEAR_START3]], align 4
|
|
// CHECK1-NEXT: [[CONV22:%.*]] = sext i32 [[TMP24]] to i64
|
|
// CHECK1-NEXT: [[TMP25:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
|
|
// CHECK1-NEXT: [[MUL23:%.*]] = mul i64 4, [[TMP25]]
|
|
// CHECK1-NEXT: [[ADD24:%.*]] = add i64 [[CONV22]], [[MUL23]]
|
|
// CHECK1-NEXT: [[CONV25:%.*]] = trunc i64 [[ADD24]] to i32
|
|
// CHECK1-NEXT: store i32 [[CONV25]], i32* [[CONV2]], align 8
|
|
// CHECK1-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]]
|
|
// CHECK1: .omp.linear.pu.done:
|
|
// CHECK1-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116
|
|
// CHECK1-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] {
|
|
// CHECK1-NEXT: entry:
|
|
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
|
|
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
|
|
// CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
|
|
// CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
|
|
// CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4
|
|
// CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
|
|
// CHECK1-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
|
|
// CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
|
|
// CHECK1-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2
|
|
// CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
|
|
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
|
|
// CHECK1-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..4
|
|
// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR3]] {
|
|
// CHECK1-NEXT: entry:
|
|
// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[TMP:%.*]] = alloca i16, align 2
|
|
// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[IT:%.*]] = alloca i16, align 2
|
|
// CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
|
|
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
|
|
// CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK1-NEXT: store i32 3, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
|
|
// CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
|
|
// CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3
|
|
// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK1: cond.true:
|
|
// CHECK1-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK1: cond.false:
|
|
// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK1-NEXT: br label [[COND_END]]
|
|
// CHECK1: cond.end:
|
|
// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
|
|
// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK1: omp.inner.for.cond:
|
|
// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !32
|
|
// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !32
|
|
// CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
|
|
// CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK1: omp.inner.for.body:
|
|
// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !32
|
|
// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4
|
|
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]]
|
|
// CHECK1-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD]] to i16
|
|
// CHECK1-NEXT: store i16 [[CONV3]], i16* [[IT]], align 2, !llvm.access.group !32
|
|
// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !32
|
|
// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1
|
|
// CHECK1-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 8, !llvm.access.group !32
|
|
// CHECK1-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 8, !llvm.access.group !32
|
|
// CHECK1-NEXT: [[CONV5:%.*]] = sext i16 [[TMP9]] to i32
|
|
// CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1
|
|
// CHECK1-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16
|
|
// CHECK1-NEXT: store i16 [[CONV7]], i16* [[CONV1]], align 8, !llvm.access.group !32
|
|
// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK1: omp.body.continue:
|
|
// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK1: omp.inner.for.inc:
|
|
// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !32
|
|
// CHECK1-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP10]], 1
|
|
// CHECK1-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !32
|
|
// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP33:![0-9]+]]
|
|
// CHECK1: omp.inner.for.end:
|
|
// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK1: omp.loop.exit:
|
|
// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
|
|
// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK1-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
|
|
// CHECK1-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
|
|
// CHECK1: .omp.final.then:
|
|
// CHECK1-NEXT: store i16 22, i16* [[IT]], align 2
|
|
// CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]]
|
|
// CHECK1: .omp.final.done:
|
|
// CHECK1-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140
|
|
// CHECK1-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] {
|
|
// CHECK1-NEXT: entry:
|
|
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
|
|
// CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8
|
|
// CHECK1-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
|
|
// CHECK1-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8
|
|
// CHECK1-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
|
|
// CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK1-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
|
|
// CHECK1-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
|
|
// CHECK1-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8
|
|
// CHECK1-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
|
|
// CHECK1-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
|
|
// CHECK1-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
|
|
// CHECK1-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8
|
|
// CHECK1-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
|
|
// CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
|
|
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK1-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
|
|
// CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
|
|
// CHECK1-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
|
|
// CHECK1-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
|
|
// CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
|
|
// CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
|
|
// CHECK1-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
|
|
// CHECK1-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
|
|
// CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
|
|
// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
|
|
// CHECK1-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32*
|
|
// CHECK1-NEXT: store i32 [[TMP8]], i32* [[CONV6]], align 4
|
|
// CHECK1-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
|
|
// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 8
|
|
// CHECK1-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
|
|
// CHECK1-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4
|
|
// CHECK1-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
|
|
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]])
|
|
// CHECK1-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..7
|
|
// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] {
|
|
// CHECK1-NEXT: entry:
|
|
// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
|
|
// CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8
|
|
// CHECK1-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
|
|
// CHECK1-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8
|
|
// CHECK1-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
|
|
// CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[TMP:%.*]] = alloca i8, align 1
|
|
// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[IT:%.*]] = alloca i8, align 1
|
|
// CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK1-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
|
|
// CHECK1-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
|
|
// CHECK1-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8
|
|
// CHECK1-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
|
|
// CHECK1-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
|
|
// CHECK1-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
|
|
// CHECK1-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8
|
|
// CHECK1-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
|
|
// CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
|
|
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK1-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
|
|
// CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
|
|
// CHECK1-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
|
|
// CHECK1-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
|
|
// CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
|
|
// CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
|
|
// CHECK1-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
|
|
// CHECK1-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
|
|
// CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
|
|
// CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK1-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 8
|
|
// CHECK1-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
|
|
// CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
|
|
// CHECK1-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
|
|
// CHECK1: omp.dispatch.cond:
|
|
// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25
|
|
// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK1: cond.true:
|
|
// CHECK1-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK1: cond.false:
|
|
// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK1-NEXT: br label [[COND_END]]
|
|
// CHECK1: cond.end:
|
|
// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
|
|
// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK1-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK1-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
|
|
// CHECK1-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
|
|
// CHECK1: omp.dispatch.body:
|
|
// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK1: omp.inner.for.cond:
|
|
// CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !35
|
|
// CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !35
|
|
// CHECK1-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
|
|
// CHECK1-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK1: omp.inner.for.body:
|
|
// CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !35
|
|
// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
|
|
// CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]]
|
|
// CHECK1-NEXT: [[CONV8:%.*]] = trunc i32 [[SUB]] to i8
|
|
// CHECK1-NEXT: store i8 [[CONV8]], i8* [[IT]], align 1, !llvm.access.group !35
|
|
// CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !35
|
|
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1
|
|
// CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8, !llvm.access.group !35
|
|
// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
|
|
// CHECK1-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !35
|
|
// CHECK1-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double
|
|
// CHECK1-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00
|
|
// CHECK1-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float
|
|
// CHECK1-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4, !llvm.access.group !35
|
|
// CHECK1-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3
|
|
// CHECK1-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4, !llvm.access.group !35
|
|
// CHECK1-NEXT: [[CONV13:%.*]] = fpext float [[TMP21]] to double
|
|
// CHECK1-NEXT: [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00
|
|
// CHECK1-NEXT: [[CONV15:%.*]] = fptrunc double [[ADD14]] to float
|
|
// CHECK1-NEXT: store float [[CONV15]], float* [[ARRAYIDX12]], align 4, !llvm.access.group !35
|
|
// CHECK1-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1
|
|
// CHECK1-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX16]], i64 0, i64 2
|
|
// CHECK1-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX17]], align 8, !llvm.access.group !35
|
|
// CHECK1-NEXT: [[ADD18:%.*]] = fadd double [[TMP22]], 1.000000e+00
|
|
// CHECK1-NEXT: store double [[ADD18]], double* [[ARRAYIDX17]], align 8, !llvm.access.group !35
|
|
// CHECK1-NEXT: [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]]
|
|
// CHECK1-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP23]]
|
|
// CHECK1-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX19]], i64 3
|
|
// CHECK1-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX20]], align 8, !llvm.access.group !35
|
|
// CHECK1-NEXT: [[ADD21:%.*]] = fadd double [[TMP24]], 1.000000e+00
|
|
// CHECK1-NEXT: store double [[ADD21]], double* [[ARRAYIDX20]], align 8, !llvm.access.group !35
|
|
// CHECK1-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 8, !llvm.access.group !35
|
|
// CHECK1-NEXT: [[ADD22:%.*]] = add nsw i64 [[TMP25]], 1
|
|
// CHECK1-NEXT: store i64 [[ADD22]], i64* [[X]], align 8, !llvm.access.group !35
|
|
// CHECK1-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1
|
|
// CHECK1-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 8, !llvm.access.group !35
|
|
// CHECK1-NEXT: [[CONV23:%.*]] = sext i8 [[TMP26]] to i32
|
|
// CHECK1-NEXT: [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1
|
|
// CHECK1-NEXT: [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8
|
|
// CHECK1-NEXT: store i8 [[CONV25]], i8* [[Y]], align 8, !llvm.access.group !35
|
|
// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK1: omp.body.continue:
|
|
// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK1: omp.inner.for.inc:
|
|
// CHECK1-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !35
|
|
// CHECK1-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP27]], 1
|
|
// CHECK1-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !35
|
|
// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP36:![0-9]+]]
|
|
// CHECK1: omp.inner.for.end:
|
|
// CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
|
|
// CHECK1: omp.dispatch.inc:
|
|
// CHECK1-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK1-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK1-NEXT: [[ADD27:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]
|
|
// CHECK1-NEXT: store i32 [[ADD27]], i32* [[DOTOMP_LB]], align 4
|
|
// CHECK1-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK1-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK1-NEXT: [[ADD28:%.*]] = add nsw i32 [[TMP30]], [[TMP31]]
|
|
// CHECK1-NEXT: store i32 [[ADD28]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK1-NEXT: br label [[OMP_DISPATCH_COND]]
|
|
// CHECK1: omp.dispatch.end:
|
|
// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]])
|
|
// CHECK1-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK1-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0
|
|
// CHECK1-NEXT: br i1 [[TMP33]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
|
|
// CHECK1: .omp.final.then:
|
|
// CHECK1-NEXT: store i8 96, i8* [[IT]], align 1
|
|
// CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]]
|
|
// CHECK1: .omp.final.done:
|
|
// CHECK1-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK1-LABEL: define {{[^@]+}}@_Z3bari
|
|
// CHECK1-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
|
|
// CHECK1-NEXT: entry:
|
|
// CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8
|
|
// CHECK1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK1-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK1-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]])
|
|
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
|
|
// CHECK1-NEXT: store i32 [[ADD]], i32* [[A]], align 4
|
|
// CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK1-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]])
|
|
// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
|
|
// CHECK1-NEXT: store i32 [[ADD2]], i32* [[A]], align 4
|
|
// CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK1-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]])
|
|
// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
|
|
// CHECK1-NEXT: store i32 [[ADD4]], i32* [[A]], align 4
|
|
// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK1-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]])
|
|
// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
|
|
// CHECK1-NEXT: store i32 [[ADD6]], i32* [[A]], align 4
|
|
// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK1-NEXT: ret i32 [[TMP8]]
|
|
//
|
|
//
|
|
// CHECK1-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
|
|
// CHECK1-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 {
|
|
// CHECK1-NEXT: entry:
|
|
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
|
|
// CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[B:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8
|
|
// CHECK1-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8
|
|
// CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8
|
|
// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8
|
|
// CHECK1-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 8
|
|
// CHECK1-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
|
|
// CHECK1-NEXT: store i32 [[ADD]], i32* [[B]], align 4
|
|
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK1-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
|
|
// CHECK1-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave()
|
|
// CHECK1-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8
|
|
// CHECK1-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]]
|
|
// CHECK1-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2
|
|
// CHECK1-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8
|
|
// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4
|
|
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i32*
|
|
// CHECK1-NEXT: store i32 [[TMP5]], i32* [[CONV]], align 4
|
|
// CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8
|
|
// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 60
|
|
// CHECK1-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
|
|
// CHECK1: omp_if.then:
|
|
// CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[TMP8:%.*]] = mul nuw i64 2, [[TMP2]]
|
|
// CHECK1-NEXT: [[TMP9:%.*]] = mul nuw i64 [[TMP8]], 2
|
|
// CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to %struct.S1**
|
|
// CHECK1-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP11]], align 8
|
|
// CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to double**
|
|
// CHECK1-NEXT: store double* [[A]], double** [[TMP13]], align 8
|
|
// CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
|
|
// CHECK1-NEXT: store i64 8, i64* [[TMP14]], align 8
|
|
// CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
|
|
// CHECK1-NEXT: store i8* null, i8** [[TMP15]], align 8
|
|
// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
|
|
// CHECK1-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64*
|
|
// CHECK1-NEXT: store i64 [[TMP6]], i64* [[TMP17]], align 8
|
|
// CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
|
|
// CHECK1-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64*
|
|
// CHECK1-NEXT: store i64 [[TMP6]], i64* [[TMP19]], align 8
|
|
// CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1
|
|
// CHECK1-NEXT: store i64 4, i64* [[TMP20]], align 8
|
|
// CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
|
|
// CHECK1-NEXT: store i8* null, i8** [[TMP21]], align 8
|
|
// CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
|
|
// CHECK1-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i64*
|
|
// CHECK1-NEXT: store i64 2, i64* [[TMP23]], align 8
|
|
// CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
|
|
// CHECK1-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i64*
|
|
// CHECK1-NEXT: store i64 2, i64* [[TMP25]], align 8
|
|
// CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2
|
|
// CHECK1-NEXT: store i64 8, i64* [[TMP26]], align 8
|
|
// CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
|
|
// CHECK1-NEXT: store i8* null, i8** [[TMP27]], align 8
|
|
// CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
|
|
// CHECK1-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i64*
|
|
// CHECK1-NEXT: store i64 [[TMP2]], i64* [[TMP29]], align 8
|
|
// CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
|
|
// CHECK1-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i64*
|
|
// CHECK1-NEXT: store i64 [[TMP2]], i64* [[TMP31]], align 8
|
|
// CHECK1-NEXT: [[TMP32:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3
|
|
// CHECK1-NEXT: store i64 8, i64* [[TMP32]], align 8
|
|
// CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
|
|
// CHECK1-NEXT: store i8* null, i8** [[TMP33]], align 8
|
|
// CHECK1-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
|
|
// CHECK1-NEXT: [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i16**
|
|
// CHECK1-NEXT: store i16* [[VLA]], i16** [[TMP35]], align 8
|
|
// CHECK1-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
|
|
// CHECK1-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i16**
|
|
// CHECK1-NEXT: store i16* [[VLA]], i16** [[TMP37]], align 8
|
|
// CHECK1-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4
|
|
// CHECK1-NEXT: store i64 [[TMP9]], i64* [[TMP38]], align 8
|
|
// CHECK1-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4
|
|
// CHECK1-NEXT: store i8* null, i8** [[TMP39]], align 8
|
|
// CHECK1-NEXT: [[TMP40:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[TMP41:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[TMP42:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[TMP43:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216.region_id, i32 5, i8** [[TMP40]], i8** [[TMP41]], i64* [[TMP42]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
|
|
// CHECK1-NEXT: [[TMP44:%.*]] = icmp ne i32 [[TMP43]], 0
|
|
// CHECK1-NEXT: br i1 [[TMP44]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
|
// CHECK1: omp_offload.failed:
|
|
// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR4]]
|
|
// CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
|
// CHECK1: omp_offload.cont:
|
|
// CHECK1-NEXT: br label [[OMP_IF_END:%.*]]
|
|
// CHECK1: omp_if.else:
|
|
// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR4]]
|
|
// CHECK1-NEXT: br label [[OMP_IF_END]]
|
|
// CHECK1: omp_if.end:
|
|
// CHECK1-NEXT: [[TMP45:%.*]] = mul nsw i64 1, [[TMP2]]
|
|
// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP45]]
|
|
// CHECK1-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
|
|
// CHECK1-NEXT: [[TMP46:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2
|
|
// CHECK1-NEXT: [[CONV3:%.*]] = sext i16 [[TMP46]] to i32
|
|
// CHECK1-NEXT: [[TMP47:%.*]] = load i32, i32* [[B]], align 4
|
|
// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], [[TMP47]]
|
|
// CHECK1-NEXT: [[TMP48:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
|
|
// CHECK1-NEXT: call void @llvm.stackrestore(i8* [[TMP48]])
|
|
// CHECK1-NEXT: ret i32 [[ADD4]]
|
|
//
|
|
//
|
|
// CHECK1-LABEL: define {{[^@]+}}@_ZL7fstatici
|
|
// CHECK1-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
|
|
// CHECK1-NEXT: entry:
|
|
// CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[AA:%.*]] = alloca i16, align 2
|
|
// CHECK1-NEXT: [[AAA:%.*]] = alloca i8, align 1
|
|
// CHECK1-NEXT: [[B:%.*]] = alloca [10 x i32], align 4
|
|
// CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8
|
|
// CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8
|
|
// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8
|
|
// CHECK1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK1-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK1-NEXT: store i16 0, i16* [[AA]], align 2
|
|
// CHECK1-NEXT: store i8 0, i8* [[AAA]], align 1
|
|
// CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32*
|
|
// CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4
|
|
// CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
|
|
// CHECK1-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
|
|
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
|
|
// CHECK1-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
|
|
// CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
|
|
// CHECK1-NEXT: [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1
|
|
// CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
|
|
// CHECK1-NEXT: store i8 [[TMP4]], i8* [[CONV2]], align 1
|
|
// CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
|
|
// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50
|
|
// CHECK1-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
|
|
// CHECK1: omp_if.then:
|
|
// CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64*
|
|
// CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8
|
|
// CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64*
|
|
// CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP10]], align 8
|
|
// CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
|
|
// CHECK1-NEXT: store i8* null, i8** [[TMP11]], align 8
|
|
// CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
|
|
// CHECK1-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64*
|
|
// CHECK1-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8
|
|
// CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
|
|
// CHECK1-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64*
|
|
// CHECK1-NEXT: store i64 [[TMP3]], i64* [[TMP15]], align 8
|
|
// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
|
|
// CHECK1-NEXT: store i8* null, i8** [[TMP16]], align 8
|
|
// CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
|
|
// CHECK1-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64*
|
|
// CHECK1-NEXT: store i64 [[TMP5]], i64* [[TMP18]], align 8
|
|
// CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
|
|
// CHECK1-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64*
|
|
// CHECK1-NEXT: store i64 [[TMP5]], i64* [[TMP20]], align 8
|
|
// CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
|
|
// CHECK1-NEXT: store i8* null, i8** [[TMP21]], align 8
|
|
// CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
|
|
// CHECK1-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]**
|
|
// CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 8
|
|
// CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
|
|
// CHECK1-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]**
|
|
// CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 8
|
|
// CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
|
|
// CHECK1-NEXT: store i8* null, i8** [[TMP26]], align 8
|
|
// CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
|
|
// CHECK1-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0
|
|
// CHECK1-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
|
// CHECK1: omp_offload.failed:
|
|
// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]]
|
|
// CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
|
// CHECK1: omp_offload.cont:
|
|
// CHECK1-NEXT: br label [[OMP_IF_END:%.*]]
|
|
// CHECK1: omp_if.else:
|
|
// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]]
|
|
// CHECK1-NEXT: br label [[OMP_IF_END]]
|
|
// CHECK1: omp_if.end:
|
|
// CHECK1-NEXT: [[TMP31:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK1-NEXT: ret i32 [[TMP31]]
|
|
//
|
|
//
|
|
// CHECK1-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
|
|
// CHECK1-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat {
|
|
// CHECK1-NEXT: entry:
|
|
// CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[AA:%.*]] = alloca i16, align 2
|
|
// CHECK1-NEXT: [[B:%.*]] = alloca [10 x i32], align 4
|
|
// CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8
|
|
// CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8
|
|
// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8
|
|
// CHECK1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK1-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK1-NEXT: store i16 0, i16* [[AA]], align 2
|
|
// CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32*
|
|
// CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4
|
|
// CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
|
|
// CHECK1-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
|
|
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
|
|
// CHECK1-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
|
|
// CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
|
|
// CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40
|
|
// CHECK1-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
|
|
// CHECK1: omp_if.then:
|
|
// CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64*
|
|
// CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP6]], align 8
|
|
// CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64*
|
|
// CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8
|
|
// CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
|
|
// CHECK1-NEXT: store i8* null, i8** [[TMP9]], align 8
|
|
// CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
|
|
// CHECK1-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i64*
|
|
// CHECK1-NEXT: store i64 [[TMP3]], i64* [[TMP11]], align 8
|
|
// CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
|
|
// CHECK1-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64*
|
|
// CHECK1-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8
|
|
// CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
|
|
// CHECK1-NEXT: store i8* null, i8** [[TMP14]], align 8
|
|
// CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
|
|
// CHECK1-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]**
|
|
// CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 8
|
|
// CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
|
|
// CHECK1-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]**
|
|
// CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 8
|
|
// CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
|
|
// CHECK1-NEXT: store i8* null, i8** [[TMP19]], align 8
|
|
// CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.15, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.16, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
|
|
// CHECK1-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0
|
|
// CHECK1-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
|
// CHECK1: omp_offload.failed:
|
|
// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]]
|
|
// CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
|
// CHECK1: omp_offload.cont:
|
|
// CHECK1-NEXT: br label [[OMP_IF_END:%.*]]
|
|
// CHECK1: omp_if.else:
|
|
// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]]
|
|
// CHECK1-NEXT: br label [[OMP_IF_END]]
|
|
// CHECK1: omp_if.end:
|
|
// CHECK1-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK1-NEXT: ret i32 [[TMP24]]
|
|
//
|
|
//
|
|
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216
|
|
// CHECK1-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {
|
|
// CHECK1-NEXT: entry:
|
|
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
|
|
// CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8
|
|
// CHECK1-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK1-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
|
|
// CHECK1-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
|
|
// CHECK1-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
|
|
// CHECK1-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8
|
|
// CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
|
|
// CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
|
|
// CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
|
|
// CHECK1-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
|
|
// CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
|
|
// CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32*
|
|
// CHECK1-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
|
|
// CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
|
|
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]])
|
|
// CHECK1-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..9
|
|
// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR3]] {
|
|
// CHECK1-NEXT: entry:
|
|
// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
|
|
// CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8
|
|
// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[TMP:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[IT:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK1-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK1-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
|
|
// CHECK1-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
|
|
// CHECK1-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
|
|
// CHECK1-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8
|
|
// CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
|
|
// CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
|
|
// CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
|
|
// CHECK1-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
|
|
// CHECK1-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK1-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK1-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
|
|
// CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK1-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
|
|
// CHECK1-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
|
|
// CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK1-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 3
|
|
// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK1: cond.true:
|
|
// CHECK1-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK1: cond.false:
|
|
// CHECK1-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK1-NEXT: br label [[COND_END]]
|
|
// CHECK1: cond.end:
|
|
// CHECK1-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
|
|
// CHECK1-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
|
|
// CHECK1-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK1-NEXT: store i64 [[TMP8]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK1: omp.inner.for.cond:
|
|
// CHECK1-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !38
|
|
// CHECK1-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !38
|
|
// CHECK1-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]]
|
|
// CHECK1-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK1: omp.inner.for.body:
|
|
// CHECK1-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !38
|
|
// CHECK1-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400
|
|
// CHECK1-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]
|
|
// CHECK1-NEXT: store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !38
|
|
// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !38
|
|
// CHECK1-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double
|
|
// CHECK1-NEXT: [[ADD:%.*]] = fadd double [[CONV4]], 1.500000e+00
|
|
// CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
|
|
// CHECK1-NEXT: store double [[ADD]], double* [[A]], align 8, !llvm.access.group !38
|
|
// CHECK1-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[TMP13:%.*]] = load double, double* [[A5]], align 8, !llvm.access.group !38
|
|
// CHECK1-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00
|
|
// CHECK1-NEXT: store double [[INC]], double* [[A5]], align 8, !llvm.access.group !38
|
|
// CHECK1-NEXT: [[CONV6:%.*]] = fptosi double [[INC]] to i16
|
|
// CHECK1-NEXT: [[TMP14:%.*]] = mul nsw i64 1, [[TMP2]]
|
|
// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP14]]
|
|
// CHECK1-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
|
|
// CHECK1-NEXT: store i16 [[CONV6]], i16* [[ARRAYIDX7]], align 2, !llvm.access.group !38
|
|
// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK1: omp.body.continue:
|
|
// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK1: omp.inner.for.inc:
|
|
// CHECK1-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !38
|
|
// CHECK1-NEXT: [[ADD8:%.*]] = add i64 [[TMP15]], 1
|
|
// CHECK1-NEXT: store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !38
|
|
// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP39:![0-9]+]]
|
|
// CHECK1: omp.inner.for.end:
|
|
// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK1: omp.loop.exit:
|
|
// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
|
|
// CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK1-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0
|
|
// CHECK1-NEXT: br i1 [[TMP17]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
|
|
// CHECK1: .omp.final.then:
|
|
// CHECK1-NEXT: store i64 400, i64* [[IT]], align 8
|
|
// CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]]
|
|
// CHECK1: .omp.final.done:
|
|
// CHECK1-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195
|
|
// CHECK1-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
|
|
// CHECK1-NEXT: entry:
|
|
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
|
|
// CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
|
|
// CHECK1-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
|
|
// CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
|
|
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
|
|
// CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
|
|
// CHECK1-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
|
|
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
|
|
// CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
|
|
// CHECK1-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4
|
|
// CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
|
|
// CHECK1-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
|
|
// CHECK1-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
|
|
// CHECK1-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2
|
|
// CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
|
|
// CHECK1-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 8
|
|
// CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
|
|
// CHECK1-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1
|
|
// CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
|
|
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]])
|
|
// CHECK1-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..11
|
|
// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] {
|
|
// CHECK1-NEXT: entry:
|
|
// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
|
|
// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
|
|
// CHECK1-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
|
|
// CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
|
|
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
|
|
// CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
|
|
// CHECK1-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
|
|
// CHECK1-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178
|
|
// CHECK1-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
|
|
// CHECK1-NEXT: entry:
|
|
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
|
|
// CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
|
|
// CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
|
|
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
|
|
// CHECK1-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
|
|
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
|
|
// CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
|
|
// CHECK1-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4
|
|
// CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
|
|
// CHECK1-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
|
|
// CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
|
|
// CHECK1-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
|
|
// CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
|
|
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]])
|
|
// CHECK1-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..14
|
|
// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] {
|
|
// CHECK1-NEXT: entry:
|
|
// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
|
|
// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[TMP:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[I:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
|
|
// CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
|
|
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
|
|
// CHECK1-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
|
|
// CHECK1-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK1-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK1-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
|
|
// CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK1-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
|
|
// CHECK1-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
|
|
// CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6
|
|
// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK1: cond.true:
|
|
// CHECK1-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK1: cond.false:
|
|
// CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK1-NEXT: br label [[COND_END]]
|
|
// CHECK1: cond.end:
|
|
// CHECK1-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
|
|
// CHECK1-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
|
|
// CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK1-NEXT: store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK1: omp.inner.for.cond:
|
|
// CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !41
|
|
// CHECK1-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !41
|
|
// CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]]
|
|
// CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK1: omp.inner.for.body:
|
|
// CHECK1-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !41
|
|
// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3
|
|
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
|
|
// CHECK1-NEXT: store i64 [[ADD]], i64* [[I]], align 8, !llvm.access.group !41
|
|
// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !41
|
|
// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1
|
|
// CHECK1-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 8, !llvm.access.group !41
|
|
// CHECK1-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 8, !llvm.access.group !41
|
|
// CHECK1-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32
|
|
// CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
|
|
// CHECK1-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
|
|
// CHECK1-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 8, !llvm.access.group !41
|
|
// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
|
|
// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !41
|
|
// CHECK1-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1
|
|
// CHECK1-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !41
|
|
// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK1: omp.body.continue:
|
|
// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK1: omp.inner.for.inc:
|
|
// CHECK1-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !41
|
|
// CHECK1-NEXT: [[ADD8:%.*]] = add nsw i64 [[TMP12]], 1
|
|
// CHECK1-NEXT: store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !41
|
|
// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP42:![0-9]+]]
|
|
// CHECK1: omp.inner.for.end:
|
|
// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK1: omp.loop.exit:
|
|
// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
|
|
// CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK1-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
|
|
// CHECK1-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
|
|
// CHECK1: .omp.final.then:
|
|
// CHECK1-NEXT: store i64 11, i64* [[I]], align 8
|
|
// CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]]
|
|
// CHECK1: .omp.final.done:
|
|
// CHECK1-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
|
|
// CHECK1-SAME: () #[[ATTR7:[0-9]+]] {
|
|
// CHECK1-NEXT: entry:
|
|
// CHECK1-NEXT: call void @__tgt_register_requires(i64 1)
|
|
// CHECK1-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK2-LABEL: define {{[^@]+}}@_Z7get_valv
|
|
// CHECK2-SAME: () #[[ATTR0:[0-9]+]] {
|
|
// CHECK2-NEXT: entry:
|
|
// CHECK2-NEXT: ret i64 0
|
|
//
|
|
//
|
|
// CHECK2-LABEL: define {{[^@]+}}@_Z3fooi
|
|
// CHECK2-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
|
|
// CHECK2-NEXT: entry:
|
|
// CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK2-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK2-NEXT: [[AA:%.*]] = alloca i16, align 2
|
|
// CHECK2-NEXT: [[B:%.*]] = alloca [10 x float], align 4
|
|
// CHECK2-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8
|
|
// CHECK2-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8
|
|
// CHECK2-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8
|
|
// CHECK2-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 1
|
|
// CHECK2-NEXT: [[K:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[K_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[LIN:%.*]] = alloca i32, align 4
|
|
// CHECK2-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[A_CASTED4:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8
|
|
// CHECK2-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8
|
|
// CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8
|
|
// CHECK2-NEXT: [[A_CASTED6:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[AA_CASTED8:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS10:%.*]] = alloca [2 x i8*], align 8
|
|
// CHECK2-NEXT: [[DOTOFFLOAD_PTRS11:%.*]] = alloca [2 x i8*], align 8
|
|
// CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS12:%.*]] = alloca [2 x i8*], align 8
|
|
// CHECK2-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
|
// CHECK2-NEXT: [[A_CASTED15:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS20:%.*]] = alloca [10 x i8*], align 8
|
|
// CHECK2-NEXT: [[DOTOFFLOAD_PTRS21:%.*]] = alloca [10 x i8*], align 8
|
|
// CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS22:%.*]] = alloca [10 x i8*], align 8
|
|
// CHECK2-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 8
|
|
// CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]])
|
|
// CHECK2-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK2-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK2-NEXT: store i16 0, i16* [[AA]], align 2
|
|
// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK2-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
|
|
// CHECK2-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave()
|
|
// CHECK2-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8
|
|
// CHECK2-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP2]], align 4
|
|
// CHECK2-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8
|
|
// CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK2-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64
|
|
// CHECK2-NEXT: [[TMP6:%.*]] = mul nuw i64 5, [[TMP5]]
|
|
// CHECK2-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP6]], align 8
|
|
// CHECK2-NEXT: store i64 [[TMP5]], i64* [[__VLA_EXPR1]], align 8
|
|
// CHECK2-NEXT: [[TMP7:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 1, i64 40, i64 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1)
|
|
// CHECK2-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.kmp_task_t_with_privates*
|
|
// CHECK2-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP8]], i32 0, i32 0
|
|
// CHECK2-NEXT: [[TMP10:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i8* [[TMP7]])
|
|
// CHECK2-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv()
|
|
// CHECK2-NEXT: store i64 [[CALL]], i64* [[K]], align 8
|
|
// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32*
|
|
// CHECK2-NEXT: store i32 [[TMP11]], i32* [[CONV]], align 4
|
|
// CHECK2-NEXT: [[TMP12:%.*]] = load i64, i64* [[A_CASTED]], align 8
|
|
// CHECK2-NEXT: [[TMP13:%.*]] = load i64, i64* [[K]], align 8
|
|
// CHECK2-NEXT: store i64 [[TMP13]], i64* [[K_CASTED]], align 8
|
|
// CHECK2-NEXT: [[TMP14:%.*]] = load i64, i64* [[K_CASTED]], align 8
|
|
// CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101(i64 [[TMP12]], i64 [[TMP14]]) #[[ATTR4:[0-9]+]]
|
|
// CHECK2-NEXT: store i32 12, i32* [[LIN]], align 4
|
|
// CHECK2-NEXT: [[TMP15:%.*]] = load i16, i16* [[AA]], align 2
|
|
// CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
|
|
// CHECK2-NEXT: store i16 [[TMP15]], i16* [[CONV2]], align 2
|
|
// CHECK2-NEXT: [[TMP16:%.*]] = load i64, i64* [[AA_CASTED]], align 8
|
|
// CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[LIN]], align 4
|
|
// CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[LIN_CASTED]] to i32*
|
|
// CHECK2-NEXT: store i32 [[TMP17]], i32* [[CONV3]], align 4
|
|
// CHECK2-NEXT: [[TMP18:%.*]] = load i64, i64* [[LIN_CASTED]], align 8
|
|
// CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK2-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED4]] to i32*
|
|
// CHECK2-NEXT: store i32 [[TMP19]], i32* [[CONV5]], align 4
|
|
// CHECK2-NEXT: [[TMP20:%.*]] = load i64, i64* [[A_CASTED4]], align 8
|
|
// CHECK2-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK2-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i64*
|
|
// CHECK2-NEXT: store i64 [[TMP16]], i64* [[TMP22]], align 8
|
|
// CHECK2-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK2-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i64*
|
|
// CHECK2-NEXT: store i64 [[TMP16]], i64* [[TMP24]], align 8
|
|
// CHECK2-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
|
|
// CHECK2-NEXT: store i8* null, i8** [[TMP25]], align 8
|
|
// CHECK2-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
|
|
// CHECK2-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64*
|
|
// CHECK2-NEXT: store i64 [[TMP18]], i64* [[TMP27]], align 8
|
|
// CHECK2-NEXT: [[TMP28:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
|
|
// CHECK2-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i64*
|
|
// CHECK2-NEXT: store i64 [[TMP18]], i64* [[TMP29]], align 8
|
|
// CHECK2-NEXT: [[TMP30:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
|
|
// CHECK2-NEXT: store i8* null, i8** [[TMP30]], align 8
|
|
// CHECK2-NEXT: [[TMP31:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
|
|
// CHECK2-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i64*
|
|
// CHECK2-NEXT: store i64 [[TMP20]], i64* [[TMP32]], align 8
|
|
// CHECK2-NEXT: [[TMP33:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
|
|
// CHECK2-NEXT: [[TMP34:%.*]] = bitcast i8** [[TMP33]] to i64*
|
|
// CHECK2-NEXT: store i64 [[TMP20]], i64* [[TMP34]], align 8
|
|
// CHECK2-NEXT: [[TMP35:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
|
|
// CHECK2-NEXT: store i8* null, i8** [[TMP35]], align 8
|
|
// CHECK2-NEXT: [[TMP36:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK2-NEXT: [[TMP37:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK2-NEXT: [[TMP38:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108.region_id, i32 3, i8** [[TMP36]], i8** [[TMP37]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
|
|
// CHECK2-NEXT: [[TMP39:%.*]] = icmp ne i32 [[TMP38]], 0
|
|
// CHECK2-NEXT: br i1 [[TMP39]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
|
// CHECK2: omp_offload.failed:
|
|
// CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108(i64 [[TMP16]], i64 [[TMP18]], i64 [[TMP20]]) #[[ATTR4]]
|
|
// CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
|
// CHECK2: omp_offload.cont:
|
|
// CHECK2-NEXT: [[TMP40:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK2-NEXT: [[CONV7:%.*]] = bitcast i64* [[A_CASTED6]] to i32*
|
|
// CHECK2-NEXT: store i32 [[TMP40]], i32* [[CONV7]], align 4
|
|
// CHECK2-NEXT: [[TMP41:%.*]] = load i64, i64* [[A_CASTED6]], align 8
|
|
// CHECK2-NEXT: [[TMP42:%.*]] = load i16, i16* [[AA]], align 2
|
|
// CHECK2-NEXT: [[CONV9:%.*]] = bitcast i64* [[AA_CASTED8]] to i16*
|
|
// CHECK2-NEXT: store i16 [[TMP42]], i16* [[CONV9]], align 2
|
|
// CHECK2-NEXT: [[TMP43:%.*]] = load i64, i64* [[AA_CASTED8]], align 8
|
|
// CHECK2-NEXT: [[TMP44:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP44]], 10
|
|
// CHECK2-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
|
|
// CHECK2: omp_if.then:
|
|
// CHECK2-NEXT: [[TMP45:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 0
|
|
// CHECK2-NEXT: [[TMP46:%.*]] = bitcast i8** [[TMP45]] to i64*
|
|
// CHECK2-NEXT: store i64 [[TMP41]], i64* [[TMP46]], align 8
|
|
// CHECK2-NEXT: [[TMP47:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS11]], i32 0, i32 0
|
|
// CHECK2-NEXT: [[TMP48:%.*]] = bitcast i8** [[TMP47]] to i64*
|
|
// CHECK2-NEXT: store i64 [[TMP41]], i64* [[TMP48]], align 8
|
|
// CHECK2-NEXT: [[TMP49:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS12]], i64 0, i64 0
|
|
// CHECK2-NEXT: store i8* null, i8** [[TMP49]], align 8
|
|
// CHECK2-NEXT: [[TMP50:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 1
|
|
// CHECK2-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP50]] to i64*
|
|
// CHECK2-NEXT: store i64 [[TMP43]], i64* [[TMP51]], align 8
|
|
// CHECK2-NEXT: [[TMP52:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS11]], i32 0, i32 1
|
|
// CHECK2-NEXT: [[TMP53:%.*]] = bitcast i8** [[TMP52]] to i64*
|
|
// CHECK2-NEXT: store i64 [[TMP43]], i64* [[TMP53]], align 8
|
|
// CHECK2-NEXT: [[TMP54:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS12]], i64 0, i64 1
|
|
// CHECK2-NEXT: store i8* null, i8** [[TMP54]], align 8
|
|
// CHECK2-NEXT: [[TMP55:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 0
|
|
// CHECK2-NEXT: [[TMP56:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS11]], i32 0, i32 0
|
|
// CHECK2-NEXT: [[TMP57:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116.region_id, i32 2, i8** [[TMP55]], i8** [[TMP56]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
|
|
// CHECK2-NEXT: [[TMP58:%.*]] = icmp ne i32 [[TMP57]], 0
|
|
// CHECK2-NEXT: br i1 [[TMP58]], label [[OMP_OFFLOAD_FAILED13:%.*]], label [[OMP_OFFLOAD_CONT14:%.*]]
|
|
// CHECK2: omp_offload.failed13:
|
|
// CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116(i64 [[TMP41]], i64 [[TMP43]]) #[[ATTR4]]
|
|
// CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT14]]
|
|
// CHECK2: omp_offload.cont14:
|
|
// CHECK2-NEXT: br label [[OMP_IF_END:%.*]]
|
|
// CHECK2: omp_if.else:
|
|
// CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116(i64 [[TMP41]], i64 [[TMP43]]) #[[ATTR4]]
|
|
// CHECK2-NEXT: br label [[OMP_IF_END]]
|
|
// CHECK2: omp_if.end:
|
|
// CHECK2-NEXT: [[TMP59:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK2-NEXT: store i32 [[TMP59]], i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK2-NEXT: [[TMP60:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK2-NEXT: [[CONV16:%.*]] = bitcast i64* [[A_CASTED15]] to i32*
|
|
// CHECK2-NEXT: store i32 [[TMP60]], i32* [[CONV16]], align 4
|
|
// CHECK2-NEXT: [[TMP61:%.*]] = load i64, i64* [[A_CASTED15]], align 8
|
|
// CHECK2-NEXT: [[TMP62:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK2-NEXT: [[CONV17:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
|
|
// CHECK2-NEXT: store i32 [[TMP62]], i32* [[CONV17]], align 4
|
|
// CHECK2-NEXT: [[TMP63:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
|
|
// CHECK2-NEXT: [[TMP64:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK2-NEXT: [[CMP18:%.*]] = icmp sgt i32 [[TMP64]], 20
|
|
// CHECK2-NEXT: br i1 [[CMP18]], label [[OMP_IF_THEN19:%.*]], label [[OMP_IF_ELSE25:%.*]]
|
|
// CHECK2: omp_if.then19:
|
|
// CHECK2-NEXT: [[TMP65:%.*]] = mul nuw i64 [[TMP2]], 4
|
|
// CHECK2-NEXT: [[TMP66:%.*]] = mul nuw i64 5, [[TMP5]]
|
|
// CHECK2-NEXT: [[TMP67:%.*]] = mul nuw i64 [[TMP66]], 8
|
|
// CHECK2-NEXT: [[TMP68:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0
|
|
// CHECK2-NEXT: [[TMP69:%.*]] = bitcast i8** [[TMP68]] to i64*
|
|
// CHECK2-NEXT: store i64 [[TMP61]], i64* [[TMP69]], align 8
|
|
// CHECK2-NEXT: [[TMP70:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 0
|
|
// CHECK2-NEXT: [[TMP71:%.*]] = bitcast i8** [[TMP70]] to i64*
|
|
// CHECK2-NEXT: store i64 [[TMP61]], i64* [[TMP71]], align 8
|
|
// CHECK2-NEXT: [[TMP72:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
|
|
// CHECK2-NEXT: store i64 4, i64* [[TMP72]], align 8
|
|
// CHECK2-NEXT: [[TMP73:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 0
|
|
// CHECK2-NEXT: store i8* null, i8** [[TMP73]], align 8
|
|
// CHECK2-NEXT: [[TMP74:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 1
|
|
// CHECK2-NEXT: [[TMP75:%.*]] = bitcast i8** [[TMP74]] to [10 x float]**
|
|
// CHECK2-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP75]], align 8
|
|
// CHECK2-NEXT: [[TMP76:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 1
|
|
// CHECK2-NEXT: [[TMP77:%.*]] = bitcast i8** [[TMP76]] to [10 x float]**
|
|
// CHECK2-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP77]], align 8
|
|
// CHECK2-NEXT: [[TMP78:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1
|
|
// CHECK2-NEXT: store i64 40, i64* [[TMP78]], align 8
|
|
// CHECK2-NEXT: [[TMP79:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 1
|
|
// CHECK2-NEXT: store i8* null, i8** [[TMP79]], align 8
|
|
// CHECK2-NEXT: [[TMP80:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 2
|
|
// CHECK2-NEXT: [[TMP81:%.*]] = bitcast i8** [[TMP80]] to i64*
|
|
// CHECK2-NEXT: store i64 [[TMP2]], i64* [[TMP81]], align 8
|
|
// CHECK2-NEXT: [[TMP82:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 2
|
|
// CHECK2-NEXT: [[TMP83:%.*]] = bitcast i8** [[TMP82]] to i64*
|
|
// CHECK2-NEXT: store i64 [[TMP2]], i64* [[TMP83]], align 8
|
|
// CHECK2-NEXT: [[TMP84:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2
|
|
// CHECK2-NEXT: store i64 8, i64* [[TMP84]], align 8
|
|
// CHECK2-NEXT: [[TMP85:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 2
|
|
// CHECK2-NEXT: store i8* null, i8** [[TMP85]], align 8
|
|
// CHECK2-NEXT: [[TMP86:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 3
|
|
// CHECK2-NEXT: [[TMP87:%.*]] = bitcast i8** [[TMP86]] to float**
|
|
// CHECK2-NEXT: store float* [[VLA]], float** [[TMP87]], align 8
|
|
// CHECK2-NEXT: [[TMP88:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 3
|
|
// CHECK2-NEXT: [[TMP89:%.*]] = bitcast i8** [[TMP88]] to float**
|
|
// CHECK2-NEXT: store float* [[VLA]], float** [[TMP89]], align 8
|
|
// CHECK2-NEXT: [[TMP90:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3
|
|
// CHECK2-NEXT: store i64 [[TMP65]], i64* [[TMP90]], align 8
|
|
// CHECK2-NEXT: [[TMP91:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 3
|
|
// CHECK2-NEXT: store i8* null, i8** [[TMP91]], align 8
|
|
// CHECK2-NEXT: [[TMP92:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 4
|
|
// CHECK2-NEXT: [[TMP93:%.*]] = bitcast i8** [[TMP92]] to [5 x [10 x double]]**
|
|
// CHECK2-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP93]], align 8
|
|
// CHECK2-NEXT: [[TMP94:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 4
|
|
// CHECK2-NEXT: [[TMP95:%.*]] = bitcast i8** [[TMP94]] to [5 x [10 x double]]**
|
|
// CHECK2-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP95]], align 8
|
|
// CHECK2-NEXT: [[TMP96:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4
|
|
// CHECK2-NEXT: store i64 400, i64* [[TMP96]], align 8
|
|
// CHECK2-NEXT: [[TMP97:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 4
|
|
// CHECK2-NEXT: store i8* null, i8** [[TMP97]], align 8
|
|
// CHECK2-NEXT: [[TMP98:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 5
|
|
// CHECK2-NEXT: [[TMP99:%.*]] = bitcast i8** [[TMP98]] to i64*
|
|
// CHECK2-NEXT: store i64 5, i64* [[TMP99]], align 8
|
|
// CHECK2-NEXT: [[TMP100:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 5
|
|
// CHECK2-NEXT: [[TMP101:%.*]] = bitcast i8** [[TMP100]] to i64*
|
|
// CHECK2-NEXT: store i64 5, i64* [[TMP101]], align 8
|
|
// CHECK2-NEXT: [[TMP102:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 5
|
|
// CHECK2-NEXT: store i64 8, i64* [[TMP102]], align 8
|
|
// CHECK2-NEXT: [[TMP103:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 5
|
|
// CHECK2-NEXT: store i8* null, i8** [[TMP103]], align 8
|
|
// CHECK2-NEXT: [[TMP104:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 6
|
|
// CHECK2-NEXT: [[TMP105:%.*]] = bitcast i8** [[TMP104]] to i64*
|
|
// CHECK2-NEXT: store i64 [[TMP5]], i64* [[TMP105]], align 8
|
|
// CHECK2-NEXT: [[TMP106:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 6
|
|
// CHECK2-NEXT: [[TMP107:%.*]] = bitcast i8** [[TMP106]] to i64*
|
|
// CHECK2-NEXT: store i64 [[TMP5]], i64* [[TMP107]], align 8
|
|
// CHECK2-NEXT: [[TMP108:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 6
|
|
// CHECK2-NEXT: store i64 8, i64* [[TMP108]], align 8
|
|
// CHECK2-NEXT: [[TMP109:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 6
|
|
// CHECK2-NEXT: store i8* null, i8** [[TMP109]], align 8
|
|
// CHECK2-NEXT: [[TMP110:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 7
|
|
// CHECK2-NEXT: [[TMP111:%.*]] = bitcast i8** [[TMP110]] to double**
|
|
// CHECK2-NEXT: store double* [[VLA1]], double** [[TMP111]], align 8
|
|
// CHECK2-NEXT: [[TMP112:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 7
|
|
// CHECK2-NEXT: [[TMP113:%.*]] = bitcast i8** [[TMP112]] to double**
|
|
// CHECK2-NEXT: store double* [[VLA1]], double** [[TMP113]], align 8
|
|
// CHECK2-NEXT: [[TMP114:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7
|
|
// CHECK2-NEXT: store i64 [[TMP67]], i64* [[TMP114]], align 8
|
|
// CHECK2-NEXT: [[TMP115:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 7
|
|
// CHECK2-NEXT: store i8* null, i8** [[TMP115]], align 8
|
|
// CHECK2-NEXT: [[TMP116:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 8
|
|
// CHECK2-NEXT: [[TMP117:%.*]] = bitcast i8** [[TMP116]] to %struct.TT**
|
|
// CHECK2-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP117]], align 8
|
|
// CHECK2-NEXT: [[TMP118:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 8
|
|
// CHECK2-NEXT: [[TMP119:%.*]] = bitcast i8** [[TMP118]] to %struct.TT**
|
|
// CHECK2-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP119]], align 8
|
|
// CHECK2-NEXT: [[TMP120:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 8
|
|
// CHECK2-NEXT: store i64 16, i64* [[TMP120]], align 8
|
|
// CHECK2-NEXT: [[TMP121:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 8
|
|
// CHECK2-NEXT: store i8* null, i8** [[TMP121]], align 8
|
|
// CHECK2-NEXT: [[TMP122:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 9
|
|
// CHECK2-NEXT: [[TMP123:%.*]] = bitcast i8** [[TMP122]] to i64*
|
|
// CHECK2-NEXT: store i64 [[TMP63]], i64* [[TMP123]], align 8
|
|
// CHECK2-NEXT: [[TMP124:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 9
|
|
// CHECK2-NEXT: [[TMP125:%.*]] = bitcast i8** [[TMP124]] to i64*
|
|
// CHECK2-NEXT: store i64 [[TMP63]], i64* [[TMP125]], align 8
|
|
// CHECK2-NEXT: [[TMP126:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 9
|
|
// CHECK2-NEXT: store i64 4, i64* [[TMP126]], align 8
|
|
// CHECK2-NEXT: [[TMP127:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 9
|
|
// CHECK2-NEXT: store i8* null, i8** [[TMP127]], align 8
|
|
// CHECK2-NEXT: [[TMP128:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0
|
|
// CHECK2-NEXT: [[TMP129:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 0
|
|
// CHECK2-NEXT: [[TMP130:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
|
|
// CHECK2-NEXT: [[TMP131:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140.region_id, i32 10, i8** [[TMP128]], i8** [[TMP129]], i64* [[TMP130]], i64* getelementptr inbounds ([10 x i64], [10 x i64]* @.offload_maptypes.8, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
|
|
// CHECK2-NEXT: [[TMP132:%.*]] = icmp ne i32 [[TMP131]], 0
|
|
// CHECK2-NEXT: br i1 [[TMP132]], label [[OMP_OFFLOAD_FAILED23:%.*]], label [[OMP_OFFLOAD_CONT24:%.*]]
|
|
// CHECK2: omp_offload.failed23:
|
|
// CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140(i64 [[TMP61]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]], i64 [[TMP63]]) #[[ATTR4]]
|
|
// CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT24]]
|
|
// CHECK2: omp_offload.cont24:
|
|
// CHECK2-NEXT: br label [[OMP_IF_END26:%.*]]
|
|
// CHECK2: omp_if.else25:
|
|
// CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140(i64 [[TMP61]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]], i64 [[TMP63]]) #[[ATTR4]]
|
|
// CHECK2-NEXT: br label [[OMP_IF_END26]]
|
|
// CHECK2: omp_if.end26:
|
|
// CHECK2-NEXT: [[TMP133:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK2-NEXT: [[TMP134:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
|
|
// CHECK2-NEXT: call void @llvm.stackrestore(i8* [[TMP134]])
|
|
// CHECK2-NEXT: ret i32 [[TMP133]]
|
|
//
|
|
//
|
|
// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96
|
|
// CHECK2-SAME: () #[[ATTR2:[0-9]+]] {
|
|
// CHECK2-NEXT: entry:
|
|
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
|
|
// CHECK2-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined.
|
|
// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] {
|
|
// CHECK2-NEXT: entry:
|
|
// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4
|
|
// CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK2-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK2-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK2-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
|
|
// CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
|
|
// CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5
|
|
// CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK2: cond.true:
|
|
// CHECK2-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK2: cond.false:
|
|
// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK2-NEXT: br label [[COND_END]]
|
|
// CHECK2: cond.end:
|
|
// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
|
|
// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK2-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK2: omp.inner.for.cond:
|
|
// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
|
|
// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !10
|
|
// CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
|
|
// CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK2: omp.inner.for.body:
|
|
// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
|
|
// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5
|
|
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]]
|
|
// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10
|
|
// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK2: omp.body.continue:
|
|
// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK2: omp.inner.for.inc:
|
|
// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
|
|
// CHECK2-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
|
|
// CHECK2-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
|
|
// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]
|
|
// CHECK2: omp.inner.for.end:
|
|
// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK2: omp.loop.exit:
|
|
// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
|
|
// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK2-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0
|
|
// CHECK2-NEXT: br i1 [[TMP10]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
|
|
// CHECK2: .omp.final.then:
|
|
// CHECK2-NEXT: store i32 33, i32* [[I]], align 4
|
|
// CHECK2-NEXT: br label [[DOTOMP_FINAL_DONE]]
|
|
// CHECK2: .omp.final.done:
|
|
// CHECK2-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK2-LABEL: define {{[^@]+}}@.omp_task_entry.
|
|
// CHECK2-SAME: (i32 signext [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] {
|
|
// CHECK2-NEXT: entry:
|
|
// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
|
|
// CHECK2-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8
|
|
// CHECK2-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8
|
|
// CHECK2-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8
|
|
// CHECK2-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8
|
|
// CHECK2-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 8
|
|
// CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4
|
|
// CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8
|
|
// CHECK2-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4
|
|
// CHECK2-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8
|
|
// CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4
|
|
// CHECK2-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8
|
|
// CHECK2-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
|
|
// CHECK2-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
|
|
// CHECK2-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0
|
|
// CHECK2-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8
|
|
// CHECK2-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon*
|
|
// CHECK2-NEXT: [[TMP9:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8*
|
|
// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META16:![0-9]+]])
|
|
// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]])
|
|
// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META21:![0-9]+]])
|
|
// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META23:![0-9]+]])
|
|
// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !25
|
|
// CHECK2-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !25
|
|
// CHECK2-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !25
|
|
// CHECK2-NEXT: store void (i8*, ...)* null, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !25
|
|
// CHECK2-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !25
|
|
// CHECK2-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !25
|
|
// CHECK2-NEXT: [[TMP10:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !25
|
|
// CHECK2-NEXT: [[TMP11:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 0, i32 0, i8* null, i32 0, i8* null) #[[ATTR4]]
|
|
// CHECK2-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
|
|
// CHECK2-NEXT: br i1 [[TMP12]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]]
|
|
// CHECK2: omp_offload.failed.i:
|
|
// CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96() #[[ATTR4]]
|
|
// CHECK2-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]]
|
|
// CHECK2: .omp_outlined..1.exit:
|
|
// CHECK2-NEXT: ret i32 0
|
|
//
|
|
//
|
|
// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101
|
|
// CHECK2-SAME: (i64 [[A:%.*]], i64 [[K:%.*]]) #[[ATTR3]] {
|
|
// CHECK2-NEXT: entry:
|
|
// CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[K_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[K_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK2-NEXT: store i64 [[K]], i64* [[K_ADDR]], align 8
|
|
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
|
|
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32*
|
|
// CHECK2-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
|
|
// CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
|
|
// CHECK2-NEXT: [[TMP2:%.*]] = load i64, i64* [[K_ADDR]], align 8
|
|
// CHECK2-NEXT: store i64 [[TMP2]], i64* [[K_CASTED]], align 8
|
|
// CHECK2-NEXT: [[TMP3:%.*]] = load i64, i64* [[K_CASTED]], align 8
|
|
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
|
|
// CHECK2-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..2
|
|
// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[K:%.*]]) #[[ATTR3]] {
|
|
// CHECK2-NEXT: entry:
|
|
// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[K_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK2-NEXT: [[DOTLINEAR_START:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4
|
|
// CHECK2-NEXT: [[K1:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK2-NEXT: store i64 [[K]], i64* [[K_ADDR]], align 8
|
|
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK2-NEXT: [[TMP0:%.*]] = load i64, i64* [[K_ADDR]], align 8
|
|
// CHECK2-NEXT: store i64 [[TMP0]], i64* [[DOTLINEAR_START]], align 8
|
|
// CHECK2-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK2-NEXT: store i32 8, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK2-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
|
|
// CHECK2-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP2]])
|
|
// CHECK2-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32 35, i32 0, i32 8, i32 1, i32 1)
|
|
// CHECK2-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
|
|
// CHECK2: omp.dispatch.cond:
|
|
// CHECK2-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
|
|
// CHECK2-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP3]], 0
|
|
// CHECK2-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
|
|
// CHECK2: omp.dispatch.body:
|
|
// CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK2-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK2: omp.inner.for.cond:
|
|
// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !26
|
|
// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !26
|
|
// CHECK2-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
|
|
// CHECK2-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK2: omp.inner.for.body:
|
|
// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !26
|
|
// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
|
|
// CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL]]
|
|
// CHECK2-NEXT: store i32 [[SUB]], i32* [[I]], align 4, !llvm.access.group !26
|
|
// CHECK2-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8, !llvm.access.group !26
|
|
// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !26
|
|
// CHECK2-NEXT: [[MUL2:%.*]] = mul nsw i32 [[TMP9]], 3
|
|
// CHECK2-NEXT: [[CONV3:%.*]] = sext i32 [[MUL2]] to i64
|
|
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP8]], [[CONV3]]
|
|
// CHECK2-NEXT: store i64 [[ADD]], i64* [[K1]], align 8, !llvm.access.group !26
|
|
// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !26
|
|
// CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], 1
|
|
// CHECK2-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 8, !llvm.access.group !26
|
|
// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK2: omp.body.continue:
|
|
// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK2: omp.inner.for.inc:
|
|
// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !26
|
|
// CHECK2-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1
|
|
// CHECK2-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !26
|
|
// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP27:![0-9]+]]
|
|
// CHECK2: omp.inner.for.end:
|
|
// CHECK2-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
|
|
// CHECK2: omp.dispatch.inc:
|
|
// CHECK2-NEXT: br label [[OMP_DISPATCH_COND]]
|
|
// CHECK2: omp.dispatch.end:
|
|
// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK2-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0
|
|
// CHECK2-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
|
|
// CHECK2: .omp.final.then:
|
|
// CHECK2-NEXT: store i32 1, i32* [[I]], align 4
|
|
// CHECK2-NEXT: br label [[DOTOMP_FINAL_DONE]]
|
|
// CHECK2: .omp.final.done:
|
|
// CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK2-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0
|
|
// CHECK2-NEXT: br i1 [[TMP15]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
|
|
// CHECK2: .omp.linear.pu:
|
|
// CHECK2-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8
|
|
// CHECK2-NEXT: [[ADD6:%.*]] = add nsw i64 [[TMP16]], 27
|
|
// CHECK2-NEXT: store i64 [[ADD6]], i64* [[K_ADDR]], align 8
|
|
// CHECK2-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]]
|
|
// CHECK2: .omp.linear.pu.done:
|
|
// CHECK2-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108
|
|
// CHECK2-SAME: (i64 [[AA:%.*]], i64 [[LIN:%.*]], i64 [[A:%.*]]) #[[ATTR2]] {
|
|
// CHECK2-NEXT: entry:
|
|
// CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
|
|
// CHECK2-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8
|
|
// CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
|
|
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32*
|
|
// CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK2-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8
|
|
// CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
|
|
// CHECK2-NEXT: store i16 [[TMP0]], i16* [[CONV3]], align 2
|
|
// CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
|
|
// CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8
|
|
// CHECK2-NEXT: [[CONV4:%.*]] = bitcast i64* [[LIN_CASTED]] to i32*
|
|
// CHECK2-NEXT: store i32 [[TMP2]], i32* [[CONV4]], align 4
|
|
// CHECK2-NEXT: [[TMP3:%.*]] = load i64, i64* [[LIN_CASTED]], align 8
|
|
// CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV2]], align 8
|
|
// CHECK2-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
|
|
// CHECK2-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4
|
|
// CHECK2-NEXT: [[TMP5:%.*]] = load i64, i64* [[A_CASTED]], align 8
|
|
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]])
|
|
// CHECK2-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..3
|
|
// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]], i64 [[LIN:%.*]], i64 [[A:%.*]]) #[[ATTR3]] {
|
|
// CHECK2-NEXT: entry:
|
|
// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[TMP:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4
|
|
// CHECK2-NEXT: [[DOTLINEAR_START3:%.*]] = alloca i32, align 4
|
|
// CHECK2-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK2-NEXT: [[IT:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[LIN4:%.*]] = alloca i32, align 4
|
|
// CHECK2-NEXT: [[A5:%.*]] = alloca i32, align 4
|
|
// CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
|
|
// CHECK2-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8
|
|
// CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
|
|
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32*
|
|
// CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV1]], align 8
|
|
// CHECK2-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4
|
|
// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 8
|
|
// CHECK2-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START3]], align 4
|
|
// CHECK2-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv()
|
|
// CHECK2-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8
|
|
// CHECK2-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK2-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK2-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
|
|
// CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK2-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
|
|
// CHECK2-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3]], i32 [[TMP3]])
|
|
// CHECK2-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
|
|
// CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK2-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3
|
|
// CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK2: cond.true:
|
|
// CHECK2-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK2: cond.false:
|
|
// CHECK2-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK2-NEXT: br label [[COND_END]]
|
|
// CHECK2: cond.end:
|
|
// CHECK2-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
|
|
// CHECK2-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
|
|
// CHECK2-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK2-NEXT: store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK2: omp.inner.for.cond:
|
|
// CHECK2-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !29
|
|
// CHECK2-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !29
|
|
// CHECK2-NEXT: [[CMP6:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]]
|
|
// CHECK2-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK2: omp.inner.for.body:
|
|
// CHECK2-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !29
|
|
// CHECK2-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400
|
|
// CHECK2-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]
|
|
// CHECK2-NEXT: store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !29
|
|
// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4, !llvm.access.group !29
|
|
// CHECK2-NEXT: [[CONV7:%.*]] = sext i32 [[TMP10]] to i64
|
|
// CHECK2-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !29
|
|
// CHECK2-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !29
|
|
// CHECK2-NEXT: [[MUL8:%.*]] = mul i64 [[TMP11]], [[TMP12]]
|
|
// CHECK2-NEXT: [[ADD:%.*]] = add i64 [[CONV7]], [[MUL8]]
|
|
// CHECK2-NEXT: [[CONV9:%.*]] = trunc i64 [[ADD]] to i32
|
|
// CHECK2-NEXT: store i32 [[CONV9]], i32* [[LIN4]], align 4, !llvm.access.group !29
|
|
// CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START3]], align 4, !llvm.access.group !29
|
|
// CHECK2-NEXT: [[CONV10:%.*]] = sext i32 [[TMP13]] to i64
|
|
// CHECK2-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !29
|
|
// CHECK2-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !29
|
|
// CHECK2-NEXT: [[MUL11:%.*]] = mul i64 [[TMP14]], [[TMP15]]
|
|
// CHECK2-NEXT: [[ADD12:%.*]] = add i64 [[CONV10]], [[MUL11]]
|
|
// CHECK2-NEXT: [[CONV13:%.*]] = trunc i64 [[ADD12]] to i32
|
|
// CHECK2-NEXT: store i32 [[CONV13]], i32* [[A5]], align 4, !llvm.access.group !29
|
|
// CHECK2-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 8, !llvm.access.group !29
|
|
// CHECK2-NEXT: [[CONV14:%.*]] = sext i16 [[TMP16]] to i32
|
|
// CHECK2-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1
|
|
// CHECK2-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16
|
|
// CHECK2-NEXT: store i16 [[CONV16]], i16* [[CONV]], align 8, !llvm.access.group !29
|
|
// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK2: omp.body.continue:
|
|
// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK2: omp.inner.for.inc:
|
|
// CHECK2-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !29
|
|
// CHECK2-NEXT: [[ADD17:%.*]] = add i64 [[TMP17]], 1
|
|
// CHECK2-NEXT: store i64 [[ADD17]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !29
|
|
// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP30:![0-9]+]]
|
|
// CHECK2: omp.inner.for.end:
|
|
// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK2: omp.loop.exit:
|
|
// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
|
|
// CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK2-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
|
|
// CHECK2-NEXT: br i1 [[TMP19]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
|
|
// CHECK2: .omp.final.then:
|
|
// CHECK2-NEXT: store i64 400, i64* [[IT]], align 8
|
|
// CHECK2-NEXT: br label [[DOTOMP_FINAL_DONE]]
|
|
// CHECK2: .omp.final.done:
|
|
// CHECK2-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK2-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0
|
|
// CHECK2-NEXT: br i1 [[TMP21]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
|
|
// CHECK2: .omp.linear.pu:
|
|
// CHECK2-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4
|
|
// CHECK2-NEXT: [[CONV18:%.*]] = sext i32 [[TMP22]] to i64
|
|
// CHECK2-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
|
|
// CHECK2-NEXT: [[MUL19:%.*]] = mul i64 4, [[TMP23]]
|
|
// CHECK2-NEXT: [[ADD20:%.*]] = add i64 [[CONV18]], [[MUL19]]
|
|
// CHECK2-NEXT: [[CONV21:%.*]] = trunc i64 [[ADD20]] to i32
|
|
// CHECK2-NEXT: store i32 [[CONV21]], i32* [[CONV1]], align 8
|
|
// CHECK2-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTLINEAR_START3]], align 4
|
|
// CHECK2-NEXT: [[CONV22:%.*]] = sext i32 [[TMP24]] to i64
|
|
// CHECK2-NEXT: [[TMP25:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
|
|
// CHECK2-NEXT: [[MUL23:%.*]] = mul i64 4, [[TMP25]]
|
|
// CHECK2-NEXT: [[ADD24:%.*]] = add i64 [[CONV22]], [[MUL23]]
|
|
// CHECK2-NEXT: [[CONV25:%.*]] = trunc i64 [[ADD24]] to i32
|
|
// CHECK2-NEXT: store i32 [[CONV25]], i32* [[CONV2]], align 8
|
|
// CHECK2-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]]
|
|
// CHECK2: .omp.linear.pu.done:
|
|
// CHECK2-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116
|
|
// CHECK2-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] {
|
|
// CHECK2-NEXT: entry:
|
|
// CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
|
|
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
|
|
// CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
|
|
// CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
|
|
// CHECK2-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4
|
|
// CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
|
|
// CHECK2-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
|
|
// CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
|
|
// CHECK2-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2
|
|
// CHECK2-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
|
|
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
|
|
// CHECK2-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..4
|
|
// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR3]] {
|
|
// CHECK2-NEXT: entry:
|
|
// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK2-NEXT: [[TMP:%.*]] = alloca i16, align 2
|
|
// CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK2-NEXT: [[IT:%.*]] = alloca i16, align 2
|
|
// CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
|
|
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
|
|
// CHECK2-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK2-NEXT: store i32 3, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK2-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
|
|
// CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
|
|
// CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3
|
|
// CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK2: cond.true:
|
|
// CHECK2-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK2: cond.false:
|
|
// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK2-NEXT: br label [[COND_END]]
|
|
// CHECK2: cond.end:
|
|
// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
|
|
// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK2-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK2: omp.inner.for.cond:
|
|
// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !32
|
|
// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !32
|
|
// CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
|
|
// CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK2: omp.inner.for.body:
|
|
// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !32
|
|
// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4
|
|
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]]
|
|
// CHECK2-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD]] to i16
|
|
// CHECK2-NEXT: store i16 [[CONV3]], i16* [[IT]], align 2, !llvm.access.group !32
|
|
// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !32
|
|
// CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1
|
|
// CHECK2-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 8, !llvm.access.group !32
|
|
// CHECK2-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 8, !llvm.access.group !32
|
|
// CHECK2-NEXT: [[CONV5:%.*]] = sext i16 [[TMP9]] to i32
|
|
// CHECK2-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1
|
|
// CHECK2-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16
|
|
// CHECK2-NEXT: store i16 [[CONV7]], i16* [[CONV1]], align 8, !llvm.access.group !32
|
|
// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK2: omp.body.continue:
|
|
// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK2: omp.inner.for.inc:
|
|
// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !32
|
|
// CHECK2-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP10]], 1
|
|
// CHECK2-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !32
|
|
// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP33:![0-9]+]]
|
|
// CHECK2: omp.inner.for.end:
|
|
// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK2: omp.loop.exit:
|
|
// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
|
|
// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK2-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
|
|
// CHECK2-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
|
|
// CHECK2: .omp.final.then:
|
|
// CHECK2-NEXT: store i16 22, i16* [[IT]], align 2
|
|
// CHECK2-NEXT: br label [[DOTOMP_FINAL_DONE]]
|
|
// CHECK2: .omp.final.done:
|
|
// CHECK2-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140
|
|
// CHECK2-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] {
|
|
// CHECK2-NEXT: entry:
|
|
// CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
|
|
// CHECK2-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8
|
|
// CHECK2-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
|
|
// CHECK2-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8
|
|
// CHECK2-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
|
|
// CHECK2-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK2-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
|
|
// CHECK2-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
|
|
// CHECK2-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8
|
|
// CHECK2-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
|
|
// CHECK2-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
|
|
// CHECK2-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
|
|
// CHECK2-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8
|
|
// CHECK2-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
|
|
// CHECK2-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
|
|
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK2-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
|
|
// CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
|
|
// CHECK2-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
|
|
// CHECK2-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
|
|
// CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
|
|
// CHECK2-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
|
|
// CHECK2-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
|
|
// CHECK2-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
|
|
// CHECK2-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
|
|
// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
|
|
// CHECK2-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32*
|
|
// CHECK2-NEXT: store i32 [[TMP8]], i32* [[CONV6]], align 4
|
|
// CHECK2-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
|
|
// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 8
|
|
// CHECK2-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
|
|
// CHECK2-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4
|
|
// CHECK2-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
|
|
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]])
|
|
// CHECK2-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..7
|
|
// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] {
|
|
// CHECK2-NEXT: entry:
|
|
// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
|
|
// CHECK2-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8
|
|
// CHECK2-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
|
|
// CHECK2-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8
|
|
// CHECK2-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
|
|
// CHECK2-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK2-NEXT: [[TMP:%.*]] = alloca i8, align 1
|
|
// CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK2-NEXT: [[IT:%.*]] = alloca i8, align 1
|
|
// CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK2-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
|
|
// CHECK2-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
|
|
// CHECK2-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8
|
|
// CHECK2-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
|
|
// CHECK2-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
|
|
// CHECK2-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
|
|
// CHECK2-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8
|
|
// CHECK2-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
|
|
// CHECK2-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
|
|
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK2-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
|
|
// CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
|
|
// CHECK2-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
|
|
// CHECK2-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
|
|
// CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
|
|
// CHECK2-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
|
|
// CHECK2-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
|
|
// CHECK2-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
|
|
// CHECK2-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
|
|
// CHECK2-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK2-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 8
|
|
// CHECK2-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
|
|
// CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
|
|
// CHECK2-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
|
|
// CHECK2: omp.dispatch.cond:
|
|
// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25
|
|
// CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK2: cond.true:
|
|
// CHECK2-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK2: cond.false:
|
|
// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK2-NEXT: br label [[COND_END]]
|
|
// CHECK2: cond.end:
|
|
// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
|
|
// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK2-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK2-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
|
|
// CHECK2-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
|
|
// CHECK2: omp.dispatch.body:
|
|
// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK2: omp.inner.for.cond:
|
|
// CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !35
|
|
// CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !35
|
|
// CHECK2-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
|
|
// CHECK2-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK2: omp.inner.for.body:
|
|
// CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !35
|
|
// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
|
|
// CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]]
|
|
// CHECK2-NEXT: [[CONV8:%.*]] = trunc i32 [[SUB]] to i8
|
|
// CHECK2-NEXT: store i8 [[CONV8]], i8* [[IT]], align 1, !llvm.access.group !35
|
|
// CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !35
|
|
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1
|
|
// CHECK2-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8, !llvm.access.group !35
|
|
// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
|
|
// CHECK2-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !35
|
|
// CHECK2-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double
|
|
// CHECK2-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00
|
|
// CHECK2-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float
|
|
// CHECK2-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4, !llvm.access.group !35
|
|
// CHECK2-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3
|
|
// CHECK2-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4, !llvm.access.group !35
|
|
// CHECK2-NEXT: [[CONV13:%.*]] = fpext float [[TMP21]] to double
|
|
// CHECK2-NEXT: [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00
|
|
// CHECK2-NEXT: [[CONV15:%.*]] = fptrunc double [[ADD14]] to float
|
|
// CHECK2-NEXT: store float [[CONV15]], float* [[ARRAYIDX12]], align 4, !llvm.access.group !35
|
|
// CHECK2-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1
|
|
// CHECK2-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX16]], i64 0, i64 2
|
|
// CHECK2-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX17]], align 8, !llvm.access.group !35
|
|
// CHECK2-NEXT: [[ADD18:%.*]] = fadd double [[TMP22]], 1.000000e+00
|
|
// CHECK2-NEXT: store double [[ADD18]], double* [[ARRAYIDX17]], align 8, !llvm.access.group !35
|
|
// CHECK2-NEXT: [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]]
|
|
// CHECK2-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP23]]
|
|
// CHECK2-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX19]], i64 3
|
|
// CHECK2-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX20]], align 8, !llvm.access.group !35
|
|
// CHECK2-NEXT: [[ADD21:%.*]] = fadd double [[TMP24]], 1.000000e+00
|
|
// CHECK2-NEXT: store double [[ADD21]], double* [[ARRAYIDX20]], align 8, !llvm.access.group !35
|
|
// CHECK2-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0
|
|
// CHECK2-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 8, !llvm.access.group !35
|
|
// CHECK2-NEXT: [[ADD22:%.*]] = add nsw i64 [[TMP25]], 1
|
|
// CHECK2-NEXT: store i64 [[ADD22]], i64* [[X]], align 8, !llvm.access.group !35
|
|
// CHECK2-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1
|
|
// CHECK2-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 8, !llvm.access.group !35
|
|
// CHECK2-NEXT: [[CONV23:%.*]] = sext i8 [[TMP26]] to i32
|
|
// CHECK2-NEXT: [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1
|
|
// CHECK2-NEXT: [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8
|
|
// CHECK2-NEXT: store i8 [[CONV25]], i8* [[Y]], align 8, !llvm.access.group !35
|
|
// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK2: omp.body.continue:
|
|
// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK2: omp.inner.for.inc:
|
|
// CHECK2-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !35
|
|
// CHECK2-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP27]], 1
|
|
// CHECK2-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !35
|
|
// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP36:![0-9]+]]
|
|
// CHECK2: omp.inner.for.end:
|
|
// CHECK2-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
|
|
// CHECK2: omp.dispatch.inc:
|
|
// CHECK2-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK2-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK2-NEXT: [[ADD27:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]
|
|
// CHECK2-NEXT: store i32 [[ADD27]], i32* [[DOTOMP_LB]], align 4
|
|
// CHECK2-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK2-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK2-NEXT: [[ADD28:%.*]] = add nsw i32 [[TMP30]], [[TMP31]]
|
|
// CHECK2-NEXT: store i32 [[ADD28]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK2-NEXT: br label [[OMP_DISPATCH_COND]]
|
|
// CHECK2: omp.dispatch.end:
|
|
// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]])
|
|
// CHECK2-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK2-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0
|
|
// CHECK2-NEXT: br i1 [[TMP33]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
|
|
// CHECK2: .omp.final.then:
|
|
// CHECK2-NEXT: store i8 96, i8* [[IT]], align 1
|
|
// CHECK2-NEXT: br label [[DOTOMP_FINAL_DONE]]
|
|
// CHECK2: .omp.final.done:
|
|
// CHECK2-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK2-LABEL: define {{[^@]+}}@_Z3bari
|
|
// CHECK2-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
|
|
// CHECK2-NEXT: entry:
|
|
// CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK2-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK2-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8
|
|
// CHECK2-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK2-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK2-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]])
|
|
// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
|
|
// CHECK2-NEXT: store i32 [[ADD]], i32* [[A]], align 4
|
|
// CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK2-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]])
|
|
// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK2-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
|
|
// CHECK2-NEXT: store i32 [[ADD2]], i32* [[A]], align 4
|
|
// CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK2-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]])
|
|
// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
|
|
// CHECK2-NEXT: store i32 [[ADD4]], i32* [[A]], align 4
|
|
// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK2-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]])
|
|
// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK2-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
|
|
// CHECK2-NEXT: store i32 [[ADD6]], i32* [[A]], align 4
|
|
// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK2-NEXT: ret i32 [[TMP8]]
|
|
//
|
|
//
|
|
// CHECK2-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
|
|
// CHECK2-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 {
|
|
// CHECK2-NEXT: entry:
|
|
// CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
|
|
// CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK2-NEXT: [[B:%.*]] = alloca i32, align 4
|
|
// CHECK2-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8
|
|
// CHECK2-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8
|
|
// CHECK2-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8
|
|
// CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8
|
|
// CHECK2-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 8
|
|
// CHECK2-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK2-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
|
|
// CHECK2-NEXT: store i32 [[ADD]], i32* [[B]], align 4
|
|
// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK2-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
|
|
// CHECK2-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave()
|
|
// CHECK2-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8
|
|
// CHECK2-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]]
|
|
// CHECK2-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2
|
|
// CHECK2-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8
|
|
// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4
|
|
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i32*
|
|
// CHECK2-NEXT: store i32 [[TMP5]], i32* [[CONV]], align 4
|
|
// CHECK2-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8
|
|
// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 60
|
|
// CHECK2-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
|
|
// CHECK2: omp_if.then:
|
|
// CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
|
|
// CHECK2-NEXT: [[TMP8:%.*]] = mul nuw i64 2, [[TMP2]]
|
|
// CHECK2-NEXT: [[TMP9:%.*]] = mul nuw i64 [[TMP8]], 2
|
|
// CHECK2-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK2-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to %struct.S1**
|
|
// CHECK2-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP11]], align 8
|
|
// CHECK2-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK2-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to double**
|
|
// CHECK2-NEXT: store double* [[A]], double** [[TMP13]], align 8
|
|
// CHECK2-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
|
|
// CHECK2-NEXT: store i64 8, i64* [[TMP14]], align 8
|
|
// CHECK2-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
|
|
// CHECK2-NEXT: store i8* null, i8** [[TMP15]], align 8
|
|
// CHECK2-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
|
|
// CHECK2-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64*
|
|
// CHECK2-NEXT: store i64 [[TMP6]], i64* [[TMP17]], align 8
|
|
// CHECK2-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
|
|
// CHECK2-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64*
|
|
// CHECK2-NEXT: store i64 [[TMP6]], i64* [[TMP19]], align 8
|
|
// CHECK2-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1
|
|
// CHECK2-NEXT: store i64 4, i64* [[TMP20]], align 8
|
|
// CHECK2-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
|
|
// CHECK2-NEXT: store i8* null, i8** [[TMP21]], align 8
|
|
// CHECK2-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
|
|
// CHECK2-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i64*
|
|
// CHECK2-NEXT: store i64 2, i64* [[TMP23]], align 8
|
|
// CHECK2-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
|
|
// CHECK2-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i64*
|
|
// CHECK2-NEXT: store i64 2, i64* [[TMP25]], align 8
|
|
// CHECK2-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2
|
|
// CHECK2-NEXT: store i64 8, i64* [[TMP26]], align 8
|
|
// CHECK2-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
|
|
// CHECK2-NEXT: store i8* null, i8** [[TMP27]], align 8
|
|
// CHECK2-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
|
|
// CHECK2-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i64*
|
|
// CHECK2-NEXT: store i64 [[TMP2]], i64* [[TMP29]], align 8
|
|
// CHECK2-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
|
|
// CHECK2-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i64*
|
|
// CHECK2-NEXT: store i64 [[TMP2]], i64* [[TMP31]], align 8
|
|
// CHECK2-NEXT: [[TMP32:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3
|
|
// CHECK2-NEXT: store i64 8, i64* [[TMP32]], align 8
|
|
// CHECK2-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
|
|
// CHECK2-NEXT: store i8* null, i8** [[TMP33]], align 8
|
|
// CHECK2-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
|
|
// CHECK2-NEXT: [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i16**
|
|
// CHECK2-NEXT: store i16* [[VLA]], i16** [[TMP35]], align 8
|
|
// CHECK2-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
|
|
// CHECK2-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i16**
|
|
// CHECK2-NEXT: store i16* [[VLA]], i16** [[TMP37]], align 8
|
|
// CHECK2-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4
|
|
// CHECK2-NEXT: store i64 [[TMP9]], i64* [[TMP38]], align 8
|
|
// CHECK2-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4
|
|
// CHECK2-NEXT: store i8* null, i8** [[TMP39]], align 8
|
|
// CHECK2-NEXT: [[TMP40:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK2-NEXT: [[TMP41:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK2-NEXT: [[TMP42:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
|
|
// CHECK2-NEXT: [[TMP43:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216.region_id, i32 5, i8** [[TMP40]], i8** [[TMP41]], i64* [[TMP42]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
|
|
// CHECK2-NEXT: [[TMP44:%.*]] = icmp ne i32 [[TMP43]], 0
|
|
// CHECK2-NEXT: br i1 [[TMP44]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
|
// CHECK2: omp_offload.failed:
|
|
// CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR4]]
|
|
// CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
|
// CHECK2: omp_offload.cont:
|
|
// CHECK2-NEXT: br label [[OMP_IF_END:%.*]]
|
|
// CHECK2: omp_if.else:
|
|
// CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR4]]
|
|
// CHECK2-NEXT: br label [[OMP_IF_END]]
|
|
// CHECK2: omp_if.end:
|
|
// CHECK2-NEXT: [[TMP45:%.*]] = mul nsw i64 1, [[TMP2]]
|
|
// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP45]]
|
|
// CHECK2-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
|
|
// CHECK2-NEXT: [[TMP46:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2
|
|
// CHECK2-NEXT: [[CONV3:%.*]] = sext i16 [[TMP46]] to i32
|
|
// CHECK2-NEXT: [[TMP47:%.*]] = load i32, i32* [[B]], align 4
|
|
// CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], [[TMP47]]
|
|
// CHECK2-NEXT: [[TMP48:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
|
|
// CHECK2-NEXT: call void @llvm.stackrestore(i8* [[TMP48]])
|
|
// CHECK2-NEXT: ret i32 [[ADD4]]
|
|
//
|
|
//
|
|
// CHECK2-LABEL: define {{[^@]+}}@_ZL7fstatici
|
|
// CHECK2-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
|
|
// CHECK2-NEXT: entry:
|
|
// CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK2-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK2-NEXT: [[AA:%.*]] = alloca i16, align 2
|
|
// CHECK2-NEXT: [[AAA:%.*]] = alloca i8, align 1
|
|
// CHECK2-NEXT: [[B:%.*]] = alloca [10 x i32], align 4
|
|
// CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8
|
|
// CHECK2-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8
|
|
// CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8
|
|
// CHECK2-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK2-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK2-NEXT: store i16 0, i16* [[AA]], align 2
|
|
// CHECK2-NEXT: store i8 0, i8* [[AAA]], align 1
|
|
// CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32*
|
|
// CHECK2-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4
|
|
// CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
|
|
// CHECK2-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
|
|
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
|
|
// CHECK2-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
|
|
// CHECK2-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
|
|
// CHECK2-NEXT: [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1
|
|
// CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
|
|
// CHECK2-NEXT: store i8 [[TMP4]], i8* [[CONV2]], align 1
|
|
// CHECK2-NEXT: [[TMP5:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
|
|
// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50
|
|
// CHECK2-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
|
|
// CHECK2: omp_if.then:
|
|
// CHECK2-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK2-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64*
|
|
// CHECK2-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8
|
|
// CHECK2-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK2-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64*
|
|
// CHECK2-NEXT: store i64 [[TMP1]], i64* [[TMP10]], align 8
|
|
// CHECK2-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
|
|
// CHECK2-NEXT: store i8* null, i8** [[TMP11]], align 8
|
|
// CHECK2-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
|
|
// CHECK2-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64*
|
|
// CHECK2-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8
|
|
// CHECK2-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
|
|
// CHECK2-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64*
|
|
// CHECK2-NEXT: store i64 [[TMP3]], i64* [[TMP15]], align 8
|
|
// CHECK2-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
|
|
// CHECK2-NEXT: store i8* null, i8** [[TMP16]], align 8
|
|
// CHECK2-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
|
|
// CHECK2-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64*
|
|
// CHECK2-NEXT: store i64 [[TMP5]], i64* [[TMP18]], align 8
|
|
// CHECK2-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
|
|
// CHECK2-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64*
|
|
// CHECK2-NEXT: store i64 [[TMP5]], i64* [[TMP20]], align 8
|
|
// CHECK2-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
|
|
// CHECK2-NEXT: store i8* null, i8** [[TMP21]], align 8
|
|
// CHECK2-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
|
|
// CHECK2-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]**
|
|
// CHECK2-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 8
|
|
// CHECK2-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
|
|
// CHECK2-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]**
|
|
// CHECK2-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 8
|
|
// CHECK2-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
|
|
// CHECK2-NEXT: store i8* null, i8** [[TMP26]], align 8
|
|
// CHECK2-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK2-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK2-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
|
|
// CHECK2-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0
|
|
// CHECK2-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
|
// CHECK2: omp_offload.failed:
|
|
// CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]]
|
|
// CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
|
// CHECK2: omp_offload.cont:
|
|
// CHECK2-NEXT: br label [[OMP_IF_END:%.*]]
|
|
// CHECK2: omp_if.else:
|
|
// CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]]
|
|
// CHECK2-NEXT: br label [[OMP_IF_END]]
|
|
// CHECK2: omp_if.end:
|
|
// CHECK2-NEXT: [[TMP31:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK2-NEXT: ret i32 [[TMP31]]
|
|
//
|
|
//
|
|
// CHECK2-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
|
|
// CHECK2-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat {
|
|
// CHECK2-NEXT: entry:
|
|
// CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK2-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK2-NEXT: [[AA:%.*]] = alloca i16, align 2
|
|
// CHECK2-NEXT: [[B:%.*]] = alloca [10 x i32], align 4
|
|
// CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8
|
|
// CHECK2-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8
|
|
// CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8
|
|
// CHECK2-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK2-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK2-NEXT: store i16 0, i16* [[AA]], align 2
|
|
// CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32*
|
|
// CHECK2-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4
|
|
// CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
|
|
// CHECK2-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
|
|
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
|
|
// CHECK2-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
|
|
// CHECK2-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
|
|
// CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40
|
|
// CHECK2-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
|
|
// CHECK2: omp_if.then:
|
|
// CHECK2-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK2-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64*
|
|
// CHECK2-NEXT: store i64 [[TMP1]], i64* [[TMP6]], align 8
|
|
// CHECK2-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK2-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64*
|
|
// CHECK2-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8
|
|
// CHECK2-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
|
|
// CHECK2-NEXT: store i8* null, i8** [[TMP9]], align 8
|
|
// CHECK2-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
|
|
// CHECK2-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i64*
|
|
// CHECK2-NEXT: store i64 [[TMP3]], i64* [[TMP11]], align 8
|
|
// CHECK2-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
|
|
// CHECK2-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64*
|
|
// CHECK2-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8
|
|
// CHECK2-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
|
|
// CHECK2-NEXT: store i8* null, i8** [[TMP14]], align 8
|
|
// CHECK2-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
|
|
// CHECK2-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]**
|
|
// CHECK2-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 8
|
|
// CHECK2-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
|
|
// CHECK2-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]**
|
|
// CHECK2-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 8
|
|
// CHECK2-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
|
|
// CHECK2-NEXT: store i8* null, i8** [[TMP19]], align 8
|
|
// CHECK2-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK2-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK2-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.15, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.16, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
|
|
// CHECK2-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0
|
|
// CHECK2-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
|
// CHECK2: omp_offload.failed:
|
|
// CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]]
|
|
// CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
|
// CHECK2: omp_offload.cont:
|
|
// CHECK2-NEXT: br label [[OMP_IF_END:%.*]]
|
|
// CHECK2: omp_if.else:
|
|
// CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]]
|
|
// CHECK2-NEXT: br label [[OMP_IF_END]]
|
|
// CHECK2: omp_if.end:
|
|
// CHECK2-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK2-NEXT: ret i32 [[TMP24]]
|
|
//
|
|
//
|
|
// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216
|
|
// CHECK2-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {
|
|
// CHECK2-NEXT: entry:
|
|
// CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
|
|
// CHECK2-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8
|
|
// CHECK2-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK2-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
|
|
// CHECK2-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
|
|
// CHECK2-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
|
|
// CHECK2-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8
|
|
// CHECK2-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
|
|
// CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
|
|
// CHECK2-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
|
|
// CHECK2-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
|
|
// CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
|
|
// CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32*
|
|
// CHECK2-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
|
|
// CHECK2-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
|
|
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]])
|
|
// CHECK2-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..9
|
|
// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR3]] {
|
|
// CHECK2-NEXT: entry:
|
|
// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
|
|
// CHECK2-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8
|
|
// CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[TMP:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK2-NEXT: [[IT:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK2-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK2-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
|
|
// CHECK2-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
|
|
// CHECK2-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
|
|
// CHECK2-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8
|
|
// CHECK2-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
|
|
// CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
|
|
// CHECK2-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
|
|
// CHECK2-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
|
|
// CHECK2-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK2-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK2-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
|
|
// CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK2-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
|
|
// CHECK2-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
|
|
// CHECK2-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK2-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 3
|
|
// CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK2: cond.true:
|
|
// CHECK2-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK2: cond.false:
|
|
// CHECK2-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK2-NEXT: br label [[COND_END]]
|
|
// CHECK2: cond.end:
|
|
// CHECK2-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
|
|
// CHECK2-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
|
|
// CHECK2-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK2-NEXT: store i64 [[TMP8]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK2: omp.inner.for.cond:
|
|
// CHECK2-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !38
|
|
// CHECK2-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !38
|
|
// CHECK2-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]]
|
|
// CHECK2-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK2: omp.inner.for.body:
|
|
// CHECK2-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !38
|
|
// CHECK2-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400
|
|
// CHECK2-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]
|
|
// CHECK2-NEXT: store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !38
|
|
// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !38
|
|
// CHECK2-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double
|
|
// CHECK2-NEXT: [[ADD:%.*]] = fadd double [[CONV4]], 1.500000e+00
|
|
// CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
|
|
// CHECK2-NEXT: store double [[ADD]], double* [[A]], align 8, !llvm.access.group !38
|
|
// CHECK2-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
|
|
// CHECK2-NEXT: [[TMP13:%.*]] = load double, double* [[A5]], align 8, !llvm.access.group !38
|
|
// CHECK2-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00
|
|
// CHECK2-NEXT: store double [[INC]], double* [[A5]], align 8, !llvm.access.group !38
|
|
// CHECK2-NEXT: [[CONV6:%.*]] = fptosi double [[INC]] to i16
|
|
// CHECK2-NEXT: [[TMP14:%.*]] = mul nsw i64 1, [[TMP2]]
|
|
// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP14]]
|
|
// CHECK2-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
|
|
// CHECK2-NEXT: store i16 [[CONV6]], i16* [[ARRAYIDX7]], align 2, !llvm.access.group !38
|
|
// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK2: omp.body.continue:
|
|
// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK2: omp.inner.for.inc:
|
|
// CHECK2-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !38
|
|
// CHECK2-NEXT: [[ADD8:%.*]] = add i64 [[TMP15]], 1
|
|
// CHECK2-NEXT: store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !38
|
|
// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP39:![0-9]+]]
|
|
// CHECK2: omp.inner.for.end:
|
|
// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK2: omp.loop.exit:
|
|
// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
|
|
// CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK2-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0
|
|
// CHECK2-NEXT: br i1 [[TMP17]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
|
|
// CHECK2: .omp.final.then:
|
|
// CHECK2-NEXT: store i64 400, i64* [[IT]], align 8
|
|
// CHECK2-NEXT: br label [[DOTOMP_FINAL_DONE]]
|
|
// CHECK2: .omp.final.done:
|
|
// CHECK2-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195
|
|
// CHECK2-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
|
|
// CHECK2-NEXT: entry:
|
|
// CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
|
|
// CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
|
|
// CHECK2-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
|
|
// CHECK2-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
|
|
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
|
|
// CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
|
|
// CHECK2-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
|
|
// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
|
|
// CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
|
|
// CHECK2-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4
|
|
// CHECK2-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
|
|
// CHECK2-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
|
|
// CHECK2-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
|
|
// CHECK2-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2
|
|
// CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
|
|
// CHECK2-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 8
|
|
// CHECK2-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
|
|
// CHECK2-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1
|
|
// CHECK2-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
|
|
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]])
|
|
// CHECK2-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..11
|
|
// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] {
|
|
// CHECK2-NEXT: entry:
|
|
// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
|
|
// CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
|
|
// CHECK2-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
|
|
// CHECK2-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
|
|
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
|
|
// CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
|
|
// CHECK2-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
|
|
// CHECK2-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178
|
|
// CHECK2-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
|
|
// CHECK2-NEXT: entry:
|
|
// CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
|
|
// CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
|
|
// CHECK2-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
|
|
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
|
|
// CHECK2-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
|
|
// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
|
|
// CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
|
|
// CHECK2-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4
|
|
// CHECK2-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
|
|
// CHECK2-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
|
|
// CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
|
|
// CHECK2-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
|
|
// CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
|
|
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]])
|
|
// CHECK2-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..14
|
|
// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] {
|
|
// CHECK2-NEXT: entry:
|
|
// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
|
|
// CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[TMP:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK2-NEXT: [[I:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
|
|
// CHECK2-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
|
|
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
|
|
// CHECK2-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
|
|
// CHECK2-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK2-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK2-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
|
|
// CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK2-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
|
|
// CHECK2-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
|
|
// CHECK2-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6
|
|
// CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK2: cond.true:
|
|
// CHECK2-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK2: cond.false:
|
|
// CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK2-NEXT: br label [[COND_END]]
|
|
// CHECK2: cond.end:
|
|
// CHECK2-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
|
|
// CHECK2-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
|
|
// CHECK2-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK2-NEXT: store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK2: omp.inner.for.cond:
|
|
// CHECK2-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !41
|
|
// CHECK2-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !41
|
|
// CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]]
|
|
// CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK2: omp.inner.for.body:
|
|
// CHECK2-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !41
|
|
// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3
|
|
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
|
|
// CHECK2-NEXT: store i64 [[ADD]], i64* [[I]], align 8, !llvm.access.group !41
|
|
// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !41
|
|
// CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1
|
|
// CHECK2-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 8, !llvm.access.group !41
|
|
// CHECK2-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 8, !llvm.access.group !41
|
|
// CHECK2-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32
|
|
// CHECK2-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
|
|
// CHECK2-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
|
|
// CHECK2-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 8, !llvm.access.group !41
|
|
// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
|
|
// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !41
|
|
// CHECK2-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1
|
|
// CHECK2-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !41
|
|
// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK2: omp.body.continue:
|
|
// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK2: omp.inner.for.inc:
|
|
// CHECK2-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !41
|
|
// CHECK2-NEXT: [[ADD8:%.*]] = add nsw i64 [[TMP12]], 1
|
|
// CHECK2-NEXT: store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !41
|
|
// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP42:![0-9]+]]
|
|
// CHECK2: omp.inner.for.end:
|
|
// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK2: omp.loop.exit:
|
|
// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
|
|
// CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK2-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
|
|
// CHECK2-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
|
|
// CHECK2: .omp.final.then:
|
|
// CHECK2-NEXT: store i64 11, i64* [[I]], align 8
|
|
// CHECK2-NEXT: br label [[DOTOMP_FINAL_DONE]]
|
|
// CHECK2: .omp.final.done:
|
|
// CHECK2-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK2-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
|
|
// CHECK2-SAME: () #[[ATTR7:[0-9]+]] {
|
|
// CHECK2-NEXT: entry:
|
|
// CHECK2-NEXT: call void @__tgt_register_requires(i64 1)
|
|
// CHECK2-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK3-LABEL: define {{[^@]+}}@_Z7get_valv
|
|
// CHECK3-SAME: () #[[ATTR0:[0-9]+]] {
|
|
// CHECK3-NEXT: entry:
|
|
// CHECK3-NEXT: ret i64 0
|
|
//
|
|
//
|
|
// CHECK3-LABEL: define {{[^@]+}}@_Z3fooi
|
|
// CHECK3-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
|
|
// CHECK3-NEXT: entry:
|
|
// CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[AA:%.*]] = alloca i16, align 2
|
|
// CHECK3-NEXT: [[B:%.*]] = alloca [10 x float], align 4
|
|
// CHECK3-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4
|
|
// CHECK3-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8
|
|
// CHECK3-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4
|
|
// CHECK3-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 1
|
|
// CHECK3-NEXT: [[K:%.*]] = alloca i64, align 8
|
|
// CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[LIN:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[A_CASTED2:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4
|
|
// CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4
|
|
// CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4
|
|
// CHECK3-NEXT: [[A_CASTED3:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[AA_CASTED4:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS6:%.*]] = alloca [2 x i8*], align 4
|
|
// CHECK3-NEXT: [[DOTOFFLOAD_PTRS7:%.*]] = alloca [2 x i8*], align 4
|
|
// CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS8:%.*]] = alloca [2 x i8*], align 4
|
|
// CHECK3-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[A_CASTED11:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS14:%.*]] = alloca [10 x i8*], align 4
|
|
// CHECK3-NEXT: [[DOTOFFLOAD_PTRS15:%.*]] = alloca [10 x i8*], align 4
|
|
// CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS16:%.*]] = alloca [10 x i8*], align 4
|
|
// CHECK3-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 4
|
|
// CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]])
|
|
// CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK3-NEXT: store i16 0, i16* [[AA]], align 2
|
|
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave()
|
|
// CHECK3-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4
|
|
// CHECK3-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP1]], align 4
|
|
// CHECK3-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4
|
|
// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP4:%.*]] = mul nuw i32 5, [[TMP3]]
|
|
// CHECK3-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP4]], align 8
|
|
// CHECK3-NEXT: store i32 [[TMP3]], i32* [[__VLA_EXPR1]], align 4
|
|
// CHECK3-NEXT: [[TMP5:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 1, i32 20, i32 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1)
|
|
// CHECK3-NEXT: [[TMP6:%.*]] = bitcast i8* [[TMP5]] to %struct.kmp_task_t_with_privates*
|
|
// CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP6]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i8* [[TMP5]])
|
|
// CHECK3-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv()
|
|
// CHECK3-NEXT: store i64 [[CALL]], i64* [[K]], align 8
|
|
// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK3-NEXT: store i32 [[TMP9]], i32* [[A_CASTED]], align 4
|
|
// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[A_CASTED]], align 4
|
|
// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101(i32 [[TMP10]], i64* [[K]]) #[[ATTR4:[0-9]+]]
|
|
// CHECK3-NEXT: store i32 12, i32* [[LIN]], align 4
|
|
// CHECK3-NEXT: [[TMP11:%.*]] = load i16, i16* [[AA]], align 2
|
|
// CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
|
|
// CHECK3-NEXT: store i16 [[TMP11]], i16* [[CONV]], align 2
|
|
// CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[AA_CASTED]], align 4
|
|
// CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[LIN]], align 4
|
|
// CHECK3-NEXT: store i32 [[TMP13]], i32* [[LIN_CASTED]], align 4
|
|
// CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[LIN_CASTED]], align 4
|
|
// CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK3-NEXT: store i32 [[TMP15]], i32* [[A_CASTED2]], align 4
|
|
// CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[A_CASTED2]], align 4
|
|
// CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32*
|
|
// CHECK3-NEXT: store i32 [[TMP12]], i32* [[TMP18]], align 4
|
|
// CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32*
|
|
// CHECK3-NEXT: store i32 [[TMP12]], i32* [[TMP20]], align 4
|
|
// CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
|
|
// CHECK3-NEXT: store i8* null, i8** [[TMP21]], align 4
|
|
// CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
|
|
// CHECK3-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i32*
|
|
// CHECK3-NEXT: store i32 [[TMP14]], i32* [[TMP23]], align 4
|
|
// CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
|
|
// CHECK3-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i32*
|
|
// CHECK3-NEXT: store i32 [[TMP14]], i32* [[TMP25]], align 4
|
|
// CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
|
|
// CHECK3-NEXT: store i8* null, i8** [[TMP26]], align 4
|
|
// CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
|
|
// CHECK3-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i32*
|
|
// CHECK3-NEXT: store i32 [[TMP16]], i32* [[TMP28]], align 4
|
|
// CHECK3-NEXT: [[TMP29:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
|
|
// CHECK3-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i32*
|
|
// CHECK3-NEXT: store i32 [[TMP16]], i32* [[TMP30]], align 4
|
|
// CHECK3-NEXT: [[TMP31:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
|
|
// CHECK3-NEXT: store i8* null, i8** [[TMP31]], align 4
|
|
// CHECK3-NEXT: [[TMP32:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP33:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP34:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108.region_id, i32 3, i8** [[TMP32]], i8** [[TMP33]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
|
|
// CHECK3-NEXT: [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 0
|
|
// CHECK3-NEXT: br i1 [[TMP35]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
|
// CHECK3: omp_offload.failed:
|
|
// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108(i32 [[TMP12]], i32 [[TMP14]], i32 [[TMP16]]) #[[ATTR4]]
|
|
// CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
|
// CHECK3: omp_offload.cont:
|
|
// CHECK3-NEXT: [[TMP36:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK3-NEXT: store i32 [[TMP36]], i32* [[A_CASTED3]], align 4
|
|
// CHECK3-NEXT: [[TMP37:%.*]] = load i32, i32* [[A_CASTED3]], align 4
|
|
// CHECK3-NEXT: [[TMP38:%.*]] = load i16, i16* [[AA]], align 2
|
|
// CHECK3-NEXT: [[CONV5:%.*]] = bitcast i32* [[AA_CASTED4]] to i16*
|
|
// CHECK3-NEXT: store i16 [[TMP38]], i16* [[CONV5]], align 2
|
|
// CHECK3-NEXT: [[TMP39:%.*]] = load i32, i32* [[AA_CASTED4]], align 4
|
|
// CHECK3-NEXT: [[TMP40:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP40]], 10
|
|
// CHECK3-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
|
|
// CHECK3: omp_if.then:
|
|
// CHECK3-NEXT: [[TMP41:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP42:%.*]] = bitcast i8** [[TMP41]] to i32*
|
|
// CHECK3-NEXT: store i32 [[TMP37]], i32* [[TMP42]], align 4
|
|
// CHECK3-NEXT: [[TMP43:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP44:%.*]] = bitcast i8** [[TMP43]] to i32*
|
|
// CHECK3-NEXT: store i32 [[TMP37]], i32* [[TMP44]], align 4
|
|
// CHECK3-NEXT: [[TMP45:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS8]], i32 0, i32 0
|
|
// CHECK3-NEXT: store i8* null, i8** [[TMP45]], align 4
|
|
// CHECK3-NEXT: [[TMP46:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 1
|
|
// CHECK3-NEXT: [[TMP47:%.*]] = bitcast i8** [[TMP46]] to i32*
|
|
// CHECK3-NEXT: store i32 [[TMP39]], i32* [[TMP47]], align 4
|
|
// CHECK3-NEXT: [[TMP48:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 1
|
|
// CHECK3-NEXT: [[TMP49:%.*]] = bitcast i8** [[TMP48]] to i32*
|
|
// CHECK3-NEXT: store i32 [[TMP39]], i32* [[TMP49]], align 4
|
|
// CHECK3-NEXT: [[TMP50:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS8]], i32 0, i32 1
|
|
// CHECK3-NEXT: store i8* null, i8** [[TMP50]], align 4
|
|
// CHECK3-NEXT: [[TMP51:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP52:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP53:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116.region_id, i32 2, i8** [[TMP51]], i8** [[TMP52]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
|
|
// CHECK3-NEXT: [[TMP54:%.*]] = icmp ne i32 [[TMP53]], 0
|
|
// CHECK3-NEXT: br i1 [[TMP54]], label [[OMP_OFFLOAD_FAILED9:%.*]], label [[OMP_OFFLOAD_CONT10:%.*]]
|
|
// CHECK3: omp_offload.failed9:
|
|
// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116(i32 [[TMP37]], i32 [[TMP39]]) #[[ATTR4]]
|
|
// CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT10]]
|
|
// CHECK3: omp_offload.cont10:
|
|
// CHECK3-NEXT: br label [[OMP_IF_END:%.*]]
|
|
// CHECK3: omp_if.else:
|
|
// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116(i32 [[TMP37]], i32 [[TMP39]]) #[[ATTR4]]
|
|
// CHECK3-NEXT: br label [[OMP_IF_END]]
|
|
// CHECK3: omp_if.end:
|
|
// CHECK3-NEXT: [[TMP55:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK3-NEXT: store i32 [[TMP55]], i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK3-NEXT: [[TMP56:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK3-NEXT: store i32 [[TMP56]], i32* [[A_CASTED11]], align 4
|
|
// CHECK3-NEXT: [[TMP57:%.*]] = load i32, i32* [[A_CASTED11]], align 4
|
|
// CHECK3-NEXT: [[TMP58:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK3-NEXT: store i32 [[TMP58]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
|
|
// CHECK3-NEXT: [[TMP59:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
|
|
// CHECK3-NEXT: [[TMP60:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK3-NEXT: [[CMP12:%.*]] = icmp sgt i32 [[TMP60]], 20
|
|
// CHECK3-NEXT: br i1 [[CMP12]], label [[OMP_IF_THEN13:%.*]], label [[OMP_IF_ELSE19:%.*]]
|
|
// CHECK3: omp_if.then13:
|
|
// CHECK3-NEXT: [[TMP61:%.*]] = mul nuw i32 [[TMP1]], 4
|
|
// CHECK3-NEXT: [[TMP62:%.*]] = sext i32 [[TMP61]] to i64
|
|
// CHECK3-NEXT: [[TMP63:%.*]] = mul nuw i32 5, [[TMP3]]
|
|
// CHECK3-NEXT: [[TMP64:%.*]] = mul nuw i32 [[TMP63]], 8
|
|
// CHECK3-NEXT: [[TMP65:%.*]] = sext i32 [[TMP64]] to i64
|
|
// CHECK3-NEXT: [[TMP66:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP67:%.*]] = bitcast i8** [[TMP66]] to i32*
|
|
// CHECK3-NEXT: store i32 [[TMP57]], i32* [[TMP67]], align 4
|
|
// CHECK3-NEXT: [[TMP68:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP69:%.*]] = bitcast i8** [[TMP68]] to i32*
|
|
// CHECK3-NEXT: store i32 [[TMP57]], i32* [[TMP69]], align 4
|
|
// CHECK3-NEXT: [[TMP70:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
|
|
// CHECK3-NEXT: store i64 4, i64* [[TMP70]], align 4
|
|
// CHECK3-NEXT: [[TMP71:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 0
|
|
// CHECK3-NEXT: store i8* null, i8** [[TMP71]], align 4
|
|
// CHECK3-NEXT: [[TMP72:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 1
|
|
// CHECK3-NEXT: [[TMP73:%.*]] = bitcast i8** [[TMP72]] to [10 x float]**
|
|
// CHECK3-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP73]], align 4
|
|
// CHECK3-NEXT: [[TMP74:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 1
|
|
// CHECK3-NEXT: [[TMP75:%.*]] = bitcast i8** [[TMP74]] to [10 x float]**
|
|
// CHECK3-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP75]], align 4
|
|
// CHECK3-NEXT: [[TMP76:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1
|
|
// CHECK3-NEXT: store i64 40, i64* [[TMP76]], align 4
|
|
// CHECK3-NEXT: [[TMP77:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 1
|
|
// CHECK3-NEXT: store i8* null, i8** [[TMP77]], align 4
|
|
// CHECK3-NEXT: [[TMP78:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 2
|
|
// CHECK3-NEXT: [[TMP79:%.*]] = bitcast i8** [[TMP78]] to i32*
|
|
// CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP79]], align 4
|
|
// CHECK3-NEXT: [[TMP80:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 2
|
|
// CHECK3-NEXT: [[TMP81:%.*]] = bitcast i8** [[TMP80]] to i32*
|
|
// CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP81]], align 4
|
|
// CHECK3-NEXT: [[TMP82:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2
|
|
// CHECK3-NEXT: store i64 4, i64* [[TMP82]], align 4
|
|
// CHECK3-NEXT: [[TMP83:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 2
|
|
// CHECK3-NEXT: store i8* null, i8** [[TMP83]], align 4
|
|
// CHECK3-NEXT: [[TMP84:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 3
|
|
// CHECK3-NEXT: [[TMP85:%.*]] = bitcast i8** [[TMP84]] to float**
|
|
// CHECK3-NEXT: store float* [[VLA]], float** [[TMP85]], align 4
|
|
// CHECK3-NEXT: [[TMP86:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 3
|
|
// CHECK3-NEXT: [[TMP87:%.*]] = bitcast i8** [[TMP86]] to float**
|
|
// CHECK3-NEXT: store float* [[VLA]], float** [[TMP87]], align 4
|
|
// CHECK3-NEXT: [[TMP88:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3
|
|
// CHECK3-NEXT: store i64 [[TMP62]], i64* [[TMP88]], align 4
|
|
// CHECK3-NEXT: [[TMP89:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 3
|
|
// CHECK3-NEXT: store i8* null, i8** [[TMP89]], align 4
|
|
// CHECK3-NEXT: [[TMP90:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 4
|
|
// CHECK3-NEXT: [[TMP91:%.*]] = bitcast i8** [[TMP90]] to [5 x [10 x double]]**
|
|
// CHECK3-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP91]], align 4
|
|
// CHECK3-NEXT: [[TMP92:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 4
|
|
// CHECK3-NEXT: [[TMP93:%.*]] = bitcast i8** [[TMP92]] to [5 x [10 x double]]**
|
|
// CHECK3-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP93]], align 4
|
|
// CHECK3-NEXT: [[TMP94:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4
|
|
// CHECK3-NEXT: store i64 400, i64* [[TMP94]], align 4
|
|
// CHECK3-NEXT: [[TMP95:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 4
|
|
// CHECK3-NEXT: store i8* null, i8** [[TMP95]], align 4
|
|
// CHECK3-NEXT: [[TMP96:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 5
|
|
// CHECK3-NEXT: [[TMP97:%.*]] = bitcast i8** [[TMP96]] to i32*
|
|
// CHECK3-NEXT: store i32 5, i32* [[TMP97]], align 4
|
|
// CHECK3-NEXT: [[TMP98:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 5
|
|
// CHECK3-NEXT: [[TMP99:%.*]] = bitcast i8** [[TMP98]] to i32*
|
|
// CHECK3-NEXT: store i32 5, i32* [[TMP99]], align 4
|
|
// CHECK3-NEXT: [[TMP100:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 5
|
|
// CHECK3-NEXT: store i64 4, i64* [[TMP100]], align 4
|
|
// CHECK3-NEXT: [[TMP101:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 5
|
|
// CHECK3-NEXT: store i8* null, i8** [[TMP101]], align 4
|
|
// CHECK3-NEXT: [[TMP102:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 6
|
|
// CHECK3-NEXT: [[TMP103:%.*]] = bitcast i8** [[TMP102]] to i32*
|
|
// CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP103]], align 4
|
|
// CHECK3-NEXT: [[TMP104:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 6
|
|
// CHECK3-NEXT: [[TMP105:%.*]] = bitcast i8** [[TMP104]] to i32*
|
|
// CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP105]], align 4
|
|
// CHECK3-NEXT: [[TMP106:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 6
|
|
// CHECK3-NEXT: store i64 4, i64* [[TMP106]], align 4
|
|
// CHECK3-NEXT: [[TMP107:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 6
|
|
// CHECK3-NEXT: store i8* null, i8** [[TMP107]], align 4
|
|
// CHECK3-NEXT: [[TMP108:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 7
|
|
// CHECK3-NEXT: [[TMP109:%.*]] = bitcast i8** [[TMP108]] to double**
|
|
// CHECK3-NEXT: store double* [[VLA1]], double** [[TMP109]], align 4
|
|
// CHECK3-NEXT: [[TMP110:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 7
|
|
// CHECK3-NEXT: [[TMP111:%.*]] = bitcast i8** [[TMP110]] to double**
|
|
// CHECK3-NEXT: store double* [[VLA1]], double** [[TMP111]], align 4
|
|
// CHECK3-NEXT: [[TMP112:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7
|
|
// CHECK3-NEXT: store i64 [[TMP65]], i64* [[TMP112]], align 4
|
|
// CHECK3-NEXT: [[TMP113:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 7
|
|
// CHECK3-NEXT: store i8* null, i8** [[TMP113]], align 4
|
|
// CHECK3-NEXT: [[TMP114:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 8
|
|
// CHECK3-NEXT: [[TMP115:%.*]] = bitcast i8** [[TMP114]] to %struct.TT**
|
|
// CHECK3-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP115]], align 4
|
|
// CHECK3-NEXT: [[TMP116:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 8
|
|
// CHECK3-NEXT: [[TMP117:%.*]] = bitcast i8** [[TMP116]] to %struct.TT**
|
|
// CHECK3-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP117]], align 4
|
|
// CHECK3-NEXT: [[TMP118:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 8
|
|
// CHECK3-NEXT: store i64 12, i64* [[TMP118]], align 4
|
|
// CHECK3-NEXT: [[TMP119:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 8
|
|
// CHECK3-NEXT: store i8* null, i8** [[TMP119]], align 4
|
|
// CHECK3-NEXT: [[TMP120:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 9
|
|
// CHECK3-NEXT: [[TMP121:%.*]] = bitcast i8** [[TMP120]] to i32*
|
|
// CHECK3-NEXT: store i32 [[TMP59]], i32* [[TMP121]], align 4
|
|
// CHECK3-NEXT: [[TMP122:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 9
|
|
// CHECK3-NEXT: [[TMP123:%.*]] = bitcast i8** [[TMP122]] to i32*
|
|
// CHECK3-NEXT: store i32 [[TMP59]], i32* [[TMP123]], align 4
|
|
// CHECK3-NEXT: [[TMP124:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 9
|
|
// CHECK3-NEXT: store i64 4, i64* [[TMP124]], align 4
|
|
// CHECK3-NEXT: [[TMP125:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 9
|
|
// CHECK3-NEXT: store i8* null, i8** [[TMP125]], align 4
|
|
// CHECK3-NEXT: [[TMP126:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP127:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP128:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP129:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140.region_id, i32 10, i8** [[TMP126]], i8** [[TMP127]], i64* [[TMP128]], i64* getelementptr inbounds ([10 x i64], [10 x i64]* @.offload_maptypes.8, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
|
|
// CHECK3-NEXT: [[TMP130:%.*]] = icmp ne i32 [[TMP129]], 0
|
|
// CHECK3-NEXT: br i1 [[TMP130]], label [[OMP_OFFLOAD_FAILED17:%.*]], label [[OMP_OFFLOAD_CONT18:%.*]]
|
|
// CHECK3: omp_offload.failed17:
|
|
// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140(i32 [[TMP57]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]], i32 [[TMP59]]) #[[ATTR4]]
|
|
// CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT18]]
|
|
// CHECK3: omp_offload.cont18:
|
|
// CHECK3-NEXT: br label [[OMP_IF_END20:%.*]]
|
|
// CHECK3: omp_if.else19:
|
|
// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140(i32 [[TMP57]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]], i32 [[TMP59]]) #[[ATTR4]]
|
|
// CHECK3-NEXT: br label [[OMP_IF_END20]]
|
|
// CHECK3: omp_if.end20:
|
|
// CHECK3-NEXT: [[TMP131:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK3-NEXT: [[TMP132:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
|
|
// CHECK3-NEXT: call void @llvm.stackrestore(i8* [[TMP132]])
|
|
// CHECK3-NEXT: ret i32 [[TMP131]]
|
|
//
|
|
//
|
|
// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96
|
|
// CHECK3-SAME: () #[[ATTR2:[0-9]+]] {
|
|
// CHECK3-NEXT: entry:
|
|
// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
|
|
// CHECK3-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined.
|
|
// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] {
|
|
// CHECK3-NEXT: entry:
|
|
// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK3-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
|
|
// CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
|
|
// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5
|
|
// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK3: cond.true:
|
|
// CHECK3-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK3: cond.false:
|
|
// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK3-NEXT: br label [[COND_END]]
|
|
// CHECK3: cond.end:
|
|
// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
|
|
// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK3: omp.inner.for.cond:
|
|
// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
|
|
// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !11
|
|
// CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
|
|
// CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK3: omp.inner.for.body:
|
|
// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
|
|
// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5
|
|
// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]]
|
|
// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11
|
|
// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK3: omp.body.continue:
|
|
// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK3: omp.inner.for.inc:
|
|
// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
|
|
// CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
|
|
// CHECK3-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
|
|
// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]
|
|
// CHECK3: omp.inner.for.end:
|
|
// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK3: omp.loop.exit:
|
|
// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
|
|
// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK3-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0
|
|
// CHECK3-NEXT: br i1 [[TMP10]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
|
|
// CHECK3: .omp.final.then:
|
|
// CHECK3-NEXT: store i32 33, i32* [[I]], align 4
|
|
// CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]]
|
|
// CHECK3: .omp.final.done:
|
|
// CHECK3-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK3-LABEL: define {{[^@]+}}@.omp_task_entry.
|
|
// CHECK3-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] {
|
|
// CHECK3-NEXT: entry:
|
|
// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 4
|
|
// CHECK3-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 4
|
|
// CHECK3-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 4
|
|
// CHECK3-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 4
|
|
// CHECK3-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 4
|
|
// CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 4
|
|
// CHECK3-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4
|
|
// CHECK3-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4
|
|
// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4
|
|
// CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
|
|
// CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 4
|
|
// CHECK3-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon*
|
|
// CHECK3-NEXT: [[TMP9:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8*
|
|
// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META17:![0-9]+]])
|
|
// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]])
|
|
// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META22:![0-9]+]])
|
|
// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META24:![0-9]+]])
|
|
// CHECK3-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !26
|
|
// CHECK3-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 4, !noalias !26
|
|
// CHECK3-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !26
|
|
// CHECK3-NEXT: store void (i8*, ...)* null, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !26
|
|
// CHECK3-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 4, !noalias !26
|
|
// CHECK3-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !26
|
|
// CHECK3-NEXT: [[TMP10:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !26
|
|
// CHECK3-NEXT: [[TMP11:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 0, i32 0, i8* null, i32 0, i8* null) #[[ATTR4]]
|
|
// CHECK3-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
|
|
// CHECK3-NEXT: br i1 [[TMP12]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]]
|
|
// CHECK3: omp_offload.failed.i:
|
|
// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96() #[[ATTR4]]
|
|
// CHECK3-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]]
|
|
// CHECK3: .omp_outlined..1.exit:
|
|
// CHECK3-NEXT: ret i32 0
|
|
//
|
|
//
|
|
// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101
|
|
// CHECK3-SAME: (i32 [[A:%.*]], i64* nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR3]] {
|
|
// CHECK3-NEXT: entry:
|
|
// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[K_ADDR:%.*]] = alloca i64*, align 4
|
|
// CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK3-NEXT: store i64* [[K]], i64** [[K_ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP0:%.*]] = load i64*, i64** [[K_ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
|
|
// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
|
|
// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i64*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP2]], i64* [[TMP0]])
|
|
// CHECK3-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..2
|
|
// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i64* nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR3]] {
|
|
// CHECK3-NEXT: entry:
|
|
// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[K_ADDR:%.*]] = alloca i64*, align 4
|
|
// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[DOTLINEAR_START:%.*]] = alloca i64, align 8
|
|
// CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[K1:%.*]] = alloca i64, align 8
|
|
// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK3-NEXT: store i64* [[K]], i64** [[K_ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP0:%.*]] = load i64*, i64** [[K_ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP1:%.*]] = load i64, i64* [[TMP0]], align 8
|
|
// CHECK3-NEXT: store i64 [[TMP1]], i64* [[DOTLINEAR_START]], align 8
|
|
// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK3-NEXT: store i32 8, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK3-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
|
|
// CHECK3-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP3]])
|
|
// CHECK3-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 35, i32 0, i32 8, i32 1, i32 1)
|
|
// CHECK3-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
|
|
// CHECK3: omp.dispatch.cond:
|
|
// CHECK3-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
|
|
// CHECK3-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP4]], 0
|
|
// CHECK3-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
|
|
// CHECK3: omp.dispatch.body:
|
|
// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK3-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK3: omp.inner.for.cond:
|
|
// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27
|
|
// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !27
|
|
// CHECK3-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
|
|
// CHECK3-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK3: omp.inner.for.body:
|
|
// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27
|
|
// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
|
|
// CHECK3-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL]]
|
|
// CHECK3-NEXT: store i32 [[SUB]], i32* [[I]], align 4, !llvm.access.group !27
|
|
// CHECK3-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8, !llvm.access.group !27
|
|
// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27
|
|
// CHECK3-NEXT: [[MUL2:%.*]] = mul nsw i32 [[TMP10]], 3
|
|
// CHECK3-NEXT: [[CONV:%.*]] = sext i32 [[MUL2]] to i64
|
|
// CHECK3-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP9]], [[CONV]]
|
|
// CHECK3-NEXT: store i64 [[ADD]], i64* [[K1]], align 8, !llvm.access.group !27
|
|
// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !27
|
|
// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP11]], 1
|
|
// CHECK3-NEXT: store i32 [[ADD3]], i32* [[A_ADDR]], align 4, !llvm.access.group !27
|
|
// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK3: omp.body.continue:
|
|
// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK3: omp.inner.for.inc:
|
|
// CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27
|
|
// CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1
|
|
// CHECK3-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27
|
|
// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]]
|
|
// CHECK3: omp.inner.for.end:
|
|
// CHECK3-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
|
|
// CHECK3: omp.dispatch.inc:
|
|
// CHECK3-NEXT: br label [[OMP_DISPATCH_COND]]
|
|
// CHECK3: omp.dispatch.end:
|
|
// CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK3-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
|
|
// CHECK3-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
|
|
// CHECK3: .omp.final.then:
|
|
// CHECK3-NEXT: store i32 1, i32* [[I]], align 4
|
|
// CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]]
|
|
// CHECK3: .omp.final.done:
|
|
// CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK3-NEXT: [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0
|
|
// CHECK3-NEXT: br i1 [[TMP16]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
|
|
// CHECK3: .omp.linear.pu:
|
|
// CHECK3-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8
|
|
// CHECK3-NEXT: [[ADD5:%.*]] = add nsw i64 [[TMP17]], 27
|
|
// CHECK3-NEXT: store i64 [[ADD5]], i64* [[TMP0]], align 8
|
|
// CHECK3-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]]
|
|
// CHECK3: .omp.linear.pu.done:
|
|
// CHECK3-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108
|
|
// CHECK3-SAME: (i32 [[AA:%.*]], i32 [[LIN:%.*]], i32 [[A:%.*]]) #[[ATTR2]] {
|
|
// CHECK3-NEXT: entry:
|
|
// CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
|
|
// CHECK3-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
|
|
// CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
|
|
// CHECK3-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
|
|
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
|
|
// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[LIN_ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 [[TMP2]], i32* [[LIN_CASTED]], align 4
|
|
// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[LIN_CASTED]], align 4
|
|
// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 [[TMP4]], i32* [[A_CASTED]], align 4
|
|
// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[A_CASTED]], align 4
|
|
// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]])
|
|
// CHECK3-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..3
|
|
// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]], i32 [[LIN:%.*]], i32 [[A:%.*]]) #[[ATTR3]] {
|
|
// CHECK3-NEXT: entry:
|
|
// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
|
|
// CHECK3-NEXT: [[TMP:%.*]] = alloca i64, align 4
|
|
// CHECK3-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[DOTLINEAR_START1:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8
|
|
// CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
|
|
// CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
|
|
// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
|
|
// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[IT:%.*]] = alloca i64, align 8
|
|
// CHECK3-NEXT: [[LIN2:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[A3:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
|
|
// CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[LIN_ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4
|
|
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START1]], align 4
|
|
// CHECK3-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv()
|
|
// CHECK3-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8
|
|
// CHECK3-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK3-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK3-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
|
|
// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK3-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
|
|
// CHECK3-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3]], i32 [[TMP3]])
|
|
// CHECK3-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
|
|
// CHECK3-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK3-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3
|
|
// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK3: cond.true:
|
|
// CHECK3-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK3: cond.false:
|
|
// CHECK3-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK3-NEXT: br label [[COND_END]]
|
|
// CHECK3: cond.end:
|
|
// CHECK3-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
|
|
// CHECK3-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
|
|
// CHECK3-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK3-NEXT: store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK3: omp.inner.for.cond:
|
|
// CHECK3-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !30
|
|
// CHECK3-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !30
|
|
// CHECK3-NEXT: [[CMP4:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]]
|
|
// CHECK3-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK3: omp.inner.for.body:
|
|
// CHECK3-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !30
|
|
// CHECK3-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400
|
|
// CHECK3-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]
|
|
// CHECK3-NEXT: store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !30
|
|
// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4, !llvm.access.group !30
|
|
// CHECK3-NEXT: [[CONV5:%.*]] = sext i32 [[TMP10]] to i64
|
|
// CHECK3-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !30
|
|
// CHECK3-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !30
|
|
// CHECK3-NEXT: [[MUL6:%.*]] = mul i64 [[TMP11]], [[TMP12]]
|
|
// CHECK3-NEXT: [[ADD:%.*]] = add i64 [[CONV5]], [[MUL6]]
|
|
// CHECK3-NEXT: [[CONV7:%.*]] = trunc i64 [[ADD]] to i32
|
|
// CHECK3-NEXT: store i32 [[CONV7]], i32* [[LIN2]], align 4, !llvm.access.group !30
|
|
// CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START1]], align 4, !llvm.access.group !30
|
|
// CHECK3-NEXT: [[CONV8:%.*]] = sext i32 [[TMP13]] to i64
|
|
// CHECK3-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !30
|
|
// CHECK3-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !30
|
|
// CHECK3-NEXT: [[MUL9:%.*]] = mul i64 [[TMP14]], [[TMP15]]
|
|
// CHECK3-NEXT: [[ADD10:%.*]] = add i64 [[CONV8]], [[MUL9]]
|
|
// CHECK3-NEXT: [[CONV11:%.*]] = trunc i64 [[ADD10]] to i32
|
|
// CHECK3-NEXT: store i32 [[CONV11]], i32* [[A3]], align 4, !llvm.access.group !30
|
|
// CHECK3-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !30
|
|
// CHECK3-NEXT: [[CONV12:%.*]] = sext i16 [[TMP16]] to i32
|
|
// CHECK3-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1
|
|
// CHECK3-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16
|
|
// CHECK3-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 4, !llvm.access.group !30
|
|
// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK3: omp.body.continue:
|
|
// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK3: omp.inner.for.inc:
|
|
// CHECK3-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !30
|
|
// CHECK3-NEXT: [[ADD15:%.*]] = add i64 [[TMP17]], 1
|
|
// CHECK3-NEXT: store i64 [[ADD15]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !30
|
|
// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP31:![0-9]+]]
|
|
// CHECK3: omp.inner.for.end:
|
|
// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK3: omp.loop.exit:
|
|
// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
|
|
// CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK3-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
|
|
// CHECK3-NEXT: br i1 [[TMP19]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
|
|
// CHECK3: .omp.final.then:
|
|
// CHECK3-NEXT: store i64 400, i64* [[IT]], align 8
|
|
// CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]]
|
|
// CHECK3: .omp.final.done:
|
|
// CHECK3-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK3-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0
|
|
// CHECK3-NEXT: br i1 [[TMP21]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
|
|
// CHECK3: .omp.linear.pu:
|
|
// CHECK3-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4
|
|
// CHECK3-NEXT: [[CONV16:%.*]] = sext i32 [[TMP22]] to i64
|
|
// CHECK3-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
|
|
// CHECK3-NEXT: [[MUL17:%.*]] = mul i64 4, [[TMP23]]
|
|
// CHECK3-NEXT: [[ADD18:%.*]] = add i64 [[CONV16]], [[MUL17]]
|
|
// CHECK3-NEXT: [[CONV19:%.*]] = trunc i64 [[ADD18]] to i32
|
|
// CHECK3-NEXT: store i32 [[CONV19]], i32* [[LIN_ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTLINEAR_START1]], align 4
|
|
// CHECK3-NEXT: [[CONV20:%.*]] = sext i32 [[TMP24]] to i64
|
|
// CHECK3-NEXT: [[TMP25:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
|
|
// CHECK3-NEXT: [[MUL21:%.*]] = mul i64 4, [[TMP25]]
|
|
// CHECK3-NEXT: [[ADD22:%.*]] = add i64 [[CONV20]], [[MUL21]]
|
|
// CHECK3-NEXT: [[CONV23:%.*]] = trunc i64 [[ADD22]] to i32
|
|
// CHECK3-NEXT: store i32 [[CONV23]], i32* [[A_ADDR]], align 4
|
|
// CHECK3-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]]
|
|
// CHECK3: .omp.linear.pu.done:
|
|
// CHECK3-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116
|
|
// CHECK3-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] {
|
|
// CHECK3-NEXT: entry:
|
|
// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
|
|
// CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
|
|
// CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
|
|
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
|
|
// CHECK3-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
|
|
// CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
|
|
// CHECK3-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
|
|
// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
|
|
// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]])
|
|
// CHECK3-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..4
|
|
// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR3]] {
|
|
// CHECK3-NEXT: entry:
|
|
// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[TMP:%.*]] = alloca i16, align 2
|
|
// CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[IT:%.*]] = alloca i16, align 2
|
|
// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
|
|
// CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
|
|
// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK3-NEXT: store i32 3, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
|
|
// CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
|
|
// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3
|
|
// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK3: cond.true:
|
|
// CHECK3-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK3: cond.false:
|
|
// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK3-NEXT: br label [[COND_END]]
|
|
// CHECK3: cond.end:
|
|
// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
|
|
// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK3: omp.inner.for.cond:
|
|
// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33
|
|
// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !33
|
|
// CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
|
|
// CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK3: omp.inner.for.body:
|
|
// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33
|
|
// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4
|
|
// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]]
|
|
// CHECK3-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
|
|
// CHECK3-NEXT: store i16 [[CONV2]], i16* [[IT]], align 2, !llvm.access.group !33
|
|
// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !33
|
|
// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1
|
|
// CHECK3-NEXT: store i32 [[ADD3]], i32* [[A_ADDR]], align 4, !llvm.access.group !33
|
|
// CHECK3-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !33
|
|
// CHECK3-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32
|
|
// CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
|
|
// CHECK3-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
|
|
// CHECK3-NEXT: store i16 [[CONV6]], i16* [[CONV]], align 4, !llvm.access.group !33
|
|
// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK3: omp.body.continue:
|
|
// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK3: omp.inner.for.inc:
|
|
// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33
|
|
// CHECK3-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1
|
|
// CHECK3-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33
|
|
// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP34:![0-9]+]]
|
|
// CHECK3: omp.inner.for.end:
|
|
// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK3: omp.loop.exit:
|
|
// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
|
|
// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK3-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
|
|
// CHECK3-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
|
|
// CHECK3: .omp.final.then:
|
|
// CHECK3-NEXT: store i16 22, i16* [[IT]], align 2
|
|
// CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]]
|
|
// CHECK3: .omp.final.done:
|
|
// CHECK3-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140
|
|
// CHECK3-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] {
|
|
// CHECK3-NEXT: entry:
|
|
// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
|
|
// CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4
|
|
// CHECK3-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
|
|
// CHECK3-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4
|
|
// CHECK3-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
|
|
// CHECK3-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK3-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
|
|
// CHECK3-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4
|
|
// CHECK3-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
|
|
// CHECK3-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
|
|
// CHECK3-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4
|
|
// CHECK3-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
|
|
// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
|
|
// CHECK3-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4
|
|
// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4
|
|
// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
|
|
// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
|
|
// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*, i32)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i32 [[TMP11]])
|
|
// CHECK3-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..7
|
|
// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] {
|
|
// CHECK3-NEXT: entry:
|
|
// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
|
|
// CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4
|
|
// CHECK3-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
|
|
// CHECK3-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4
|
|
// CHECK3-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
|
|
// CHECK3-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[TMP:%.*]] = alloca i8, align 1
|
|
// CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[IT:%.*]] = alloca i8, align 1
|
|
// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK3-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
|
|
// CHECK3-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4
|
|
// CHECK3-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
|
|
// CHECK3-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
|
|
// CHECK3-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4
|
|
// CHECK3-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
|
|
// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
|
|
// CHECK3-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK3-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
|
|
// CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
|
|
// CHECK3-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
|
|
// CHECK3: omp.dispatch.cond:
|
|
// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25
|
|
// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK3: cond.true:
|
|
// CHECK3-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK3: cond.false:
|
|
// CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK3-NEXT: br label [[COND_END]]
|
|
// CHECK3: cond.end:
|
|
// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
|
|
// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK3-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK3-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
|
|
// CHECK3-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
|
|
// CHECK3: omp.dispatch.body:
|
|
// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK3: omp.inner.for.cond:
|
|
// CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36
|
|
// CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !36
|
|
// CHECK3-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
|
|
// CHECK3-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK3: omp.inner.for.body:
|
|
// CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36
|
|
// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
|
|
// CHECK3-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]]
|
|
// CHECK3-NEXT: [[CONV:%.*]] = trunc i32 [[SUB]] to i8
|
|
// CHECK3-NEXT: store i8 [[CONV]], i8* [[IT]], align 1, !llvm.access.group !36
|
|
// CHECK3-NEXT: [[TMP19:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !36
|
|
// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1
|
|
// CHECK3-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4, !llvm.access.group !36
|
|
// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2
|
|
// CHECK3-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !36
|
|
// CHECK3-NEXT: [[CONV7:%.*]] = fpext float [[TMP20]] to double
|
|
// CHECK3-NEXT: [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00
|
|
// CHECK3-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float
|
|
// CHECK3-NEXT: store float [[CONV9]], float* [[ARRAYIDX]], align 4, !llvm.access.group !36
|
|
// CHECK3-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3
|
|
// CHECK3-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX10]], align 4, !llvm.access.group !36
|
|
// CHECK3-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double
|
|
// CHECK3-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00
|
|
// CHECK3-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float
|
|
// CHECK3-NEXT: store float [[CONV13]], float* [[ARRAYIDX10]], align 4, !llvm.access.group !36
|
|
// CHECK3-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1
|
|
// CHECK3-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX14]], i32 0, i32 2
|
|
// CHECK3-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX15]], align 8, !llvm.access.group !36
|
|
// CHECK3-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00
|
|
// CHECK3-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8, !llvm.access.group !36
|
|
// CHECK3-NEXT: [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]]
|
|
// CHECK3-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP23]]
|
|
// CHECK3-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX17]], i32 3
|
|
// CHECK3-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX18]], align 8, !llvm.access.group !36
|
|
// CHECK3-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00
|
|
// CHECK3-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8, !llvm.access.group !36
|
|
// CHECK3-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 4, !llvm.access.group !36
|
|
// CHECK3-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1
|
|
// CHECK3-NEXT: store i64 [[ADD20]], i64* [[X]], align 4, !llvm.access.group !36
|
|
// CHECK3-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1
|
|
// CHECK3-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 4, !llvm.access.group !36
|
|
// CHECK3-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i32
|
|
// CHECK3-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1
|
|
// CHECK3-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8
|
|
// CHECK3-NEXT: store i8 [[CONV23]], i8* [[Y]], align 4, !llvm.access.group !36
|
|
// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK3: omp.body.continue:
|
|
// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK3: omp.inner.for.inc:
|
|
// CHECK3-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36
|
|
// CHECK3-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1
|
|
// CHECK3-NEXT: store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36
|
|
// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP37:![0-9]+]]
|
|
// CHECK3: omp.inner.for.end:
|
|
// CHECK3-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
|
|
// CHECK3: omp.dispatch.inc:
|
|
// CHECK3-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK3-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK3-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]
|
|
// CHECK3-NEXT: store i32 [[ADD25]], i32* [[DOTOMP_LB]], align 4
|
|
// CHECK3-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK3-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK3-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]]
|
|
// CHECK3-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK3-NEXT: br label [[OMP_DISPATCH_COND]]
|
|
// CHECK3: omp.dispatch.end:
|
|
// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]])
|
|
// CHECK3-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK3-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0
|
|
// CHECK3-NEXT: br i1 [[TMP33]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
|
|
// CHECK3: .omp.final.then:
|
|
// CHECK3-NEXT: store i8 96, i8* [[IT]], align 1
|
|
// CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]]
|
|
// CHECK3: .omp.final.done:
|
|
// CHECK3-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK3-LABEL: define {{[^@]+}}@_Z3bari
|
|
// CHECK3-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
|
|
// CHECK3-NEXT: entry:
|
|
// CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4
|
|
// CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK3-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]])
|
|
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
|
|
// CHECK3-NEXT: store i32 [[ADD]], i32* [[A]], align 4
|
|
// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK3-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]])
|
|
// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
|
|
// CHECK3-NEXT: store i32 [[ADD2]], i32* [[A]], align 4
|
|
// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK3-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]])
|
|
// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
|
|
// CHECK3-NEXT: store i32 [[ADD4]], i32* [[A]], align 4
|
|
// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK3-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]])
|
|
// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
|
|
// CHECK3-NEXT: store i32 [[ADD6]], i32* [[A]], align 4
|
|
// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK3-NEXT: ret i32 [[TMP8]]
|
|
//
|
|
//
|
|
// CHECK3-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
|
|
// CHECK3-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 {
|
|
// CHECK3-NEXT: entry:
|
|
// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
|
|
// CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[B:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4
|
|
// CHECK3-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4
|
|
// CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4
|
|
// CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4
|
|
// CHECK3-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 4
|
|
// CHECK3-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
|
|
// CHECK3-NEXT: store i32 [[ADD]], i32* [[B]], align 4
|
|
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave()
|
|
// CHECK3-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4
|
|
// CHECK3-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]]
|
|
// CHECK3-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2
|
|
// CHECK3-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4
|
|
// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[B]], align 4
|
|
// CHECK3-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4
|
|
// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4
|
|
// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 60
|
|
// CHECK3-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
|
|
// CHECK3: omp_if.then:
|
|
// CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP7:%.*]] = mul nuw i32 2, [[TMP1]]
|
|
// CHECK3-NEXT: [[TMP8:%.*]] = mul nuw i32 [[TMP7]], 2
|
|
// CHECK3-NEXT: [[TMP9:%.*]] = sext i32 [[TMP8]] to i64
|
|
// CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to %struct.S1**
|
|
// CHECK3-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP11]], align 4
|
|
// CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to double**
|
|
// CHECK3-NEXT: store double* [[A]], double** [[TMP13]], align 4
|
|
// CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
|
|
// CHECK3-NEXT: store i64 8, i64* [[TMP14]], align 4
|
|
// CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
|
|
// CHECK3-NEXT: store i8* null, i8** [[TMP15]], align 4
|
|
// CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
|
|
// CHECK3-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32*
|
|
// CHECK3-NEXT: store i32 [[TMP5]], i32* [[TMP17]], align 4
|
|
// CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
|
|
// CHECK3-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32*
|
|
// CHECK3-NEXT: store i32 [[TMP5]], i32* [[TMP19]], align 4
|
|
// CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1
|
|
// CHECK3-NEXT: store i64 4, i64* [[TMP20]], align 4
|
|
// CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
|
|
// CHECK3-NEXT: store i8* null, i8** [[TMP21]], align 4
|
|
// CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
|
|
// CHECK3-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i32*
|
|
// CHECK3-NEXT: store i32 2, i32* [[TMP23]], align 4
|
|
// CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
|
|
// CHECK3-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i32*
|
|
// CHECK3-NEXT: store i32 2, i32* [[TMP25]], align 4
|
|
// CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2
|
|
// CHECK3-NEXT: store i64 4, i64* [[TMP26]], align 4
|
|
// CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
|
|
// CHECK3-NEXT: store i8* null, i8** [[TMP27]], align 4
|
|
// CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
|
|
// CHECK3-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i32*
|
|
// CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP29]], align 4
|
|
// CHECK3-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
|
|
// CHECK3-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i32*
|
|
// CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP31]], align 4
|
|
// CHECK3-NEXT: [[TMP32:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3
|
|
// CHECK3-NEXT: store i64 4, i64* [[TMP32]], align 4
|
|
// CHECK3-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
|
|
// CHECK3-NEXT: store i8* null, i8** [[TMP33]], align 4
|
|
// CHECK3-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
|
|
// CHECK3-NEXT: [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i16**
|
|
// CHECK3-NEXT: store i16* [[VLA]], i16** [[TMP35]], align 4
|
|
// CHECK3-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
|
|
// CHECK3-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i16**
|
|
// CHECK3-NEXT: store i16* [[VLA]], i16** [[TMP37]], align 4
|
|
// CHECK3-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4
|
|
// CHECK3-NEXT: store i64 [[TMP9]], i64* [[TMP38]], align 4
|
|
// CHECK3-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4
|
|
// CHECK3-NEXT: store i8* null, i8** [[TMP39]], align 4
|
|
// CHECK3-NEXT: [[TMP40:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP41:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP42:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP43:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216.region_id, i32 5, i8** [[TMP40]], i8** [[TMP41]], i64* [[TMP42]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
|
|
// CHECK3-NEXT: [[TMP44:%.*]] = icmp ne i32 [[TMP43]], 0
|
|
// CHECK3-NEXT: br i1 [[TMP44]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
|
// CHECK3: omp_offload.failed:
|
|
// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR4]]
|
|
// CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
|
// CHECK3: omp_offload.cont:
|
|
// CHECK3-NEXT: br label [[OMP_IF_END:%.*]]
|
|
// CHECK3: omp_if.else:
|
|
// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR4]]
|
|
// CHECK3-NEXT: br label [[OMP_IF_END]]
|
|
// CHECK3: omp_if.end:
|
|
// CHECK3-NEXT: [[TMP45:%.*]] = mul nsw i32 1, [[TMP1]]
|
|
// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP45]]
|
|
// CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
|
|
// CHECK3-NEXT: [[TMP46:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2
|
|
// CHECK3-NEXT: [[CONV:%.*]] = sext i16 [[TMP46]] to i32
|
|
// CHECK3-NEXT: [[TMP47:%.*]] = load i32, i32* [[B]], align 4
|
|
// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP47]]
|
|
// CHECK3-NEXT: [[TMP48:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
|
|
// CHECK3-NEXT: call void @llvm.stackrestore(i8* [[TMP48]])
|
|
// CHECK3-NEXT: ret i32 [[ADD3]]
|
|
//
|
|
//
|
|
// CHECK3-LABEL: define {{[^@]+}}@_ZL7fstatici
|
|
// CHECK3-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
|
|
// CHECK3-NEXT: entry:
|
|
// CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[AA:%.*]] = alloca i16, align 2
|
|
// CHECK3-NEXT: [[AAA:%.*]] = alloca i8, align 1
|
|
// CHECK3-NEXT: [[B:%.*]] = alloca [10 x i32], align 4
|
|
// CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4
|
|
// CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4
|
|
// CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4
|
|
// CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK3-NEXT: store i16 0, i16* [[AA]], align 2
|
|
// CHECK3-NEXT: store i8 0, i8* [[AAA]], align 1
|
|
// CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK3-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
|
|
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
|
|
// CHECK3-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
|
|
// CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
|
|
// CHECK3-NEXT: store i16 [[TMP2]], i16* [[CONV]], align 2
|
|
// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
|
|
// CHECK3-NEXT: [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1
|
|
// CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
|
|
// CHECK3-NEXT: store i8 [[TMP4]], i8* [[CONV1]], align 1
|
|
// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
|
|
// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50
|
|
// CHECK3-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
|
|
// CHECK3: omp_if.then:
|
|
// CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32*
|
|
// CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4
|
|
// CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32*
|
|
// CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP10]], align 4
|
|
// CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
|
|
// CHECK3-NEXT: store i8* null, i8** [[TMP11]], align 4
|
|
// CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
|
|
// CHECK3-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32*
|
|
// CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4
|
|
// CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
|
|
// CHECK3-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32*
|
|
// CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP15]], align 4
|
|
// CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
|
|
// CHECK3-NEXT: store i8* null, i8** [[TMP16]], align 4
|
|
// CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
|
|
// CHECK3-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32*
|
|
// CHECK3-NEXT: store i32 [[TMP5]], i32* [[TMP18]], align 4
|
|
// CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
|
|
// CHECK3-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32*
|
|
// CHECK3-NEXT: store i32 [[TMP5]], i32* [[TMP20]], align 4
|
|
// CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
|
|
// CHECK3-NEXT: store i8* null, i8** [[TMP21]], align 4
|
|
// CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
|
|
// CHECK3-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]**
|
|
// CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 4
|
|
// CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
|
|
// CHECK3-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]**
|
|
// CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 4
|
|
// CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
|
|
// CHECK3-NEXT: store i8* null, i8** [[TMP26]], align 4
|
|
// CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
|
|
// CHECK3-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0
|
|
// CHECK3-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
|
// CHECK3: omp_offload.failed:
|
|
// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]]
|
|
// CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
|
// CHECK3: omp_offload.cont:
|
|
// CHECK3-NEXT: br label [[OMP_IF_END:%.*]]
|
|
// CHECK3: omp_if.else:
|
|
// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]]
|
|
// CHECK3-NEXT: br label [[OMP_IF_END]]
|
|
// CHECK3: omp_if.end:
|
|
// CHECK3-NEXT: [[TMP31:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK3-NEXT: ret i32 [[TMP31]]
|
|
//
|
|
//
|
|
// CHECK3-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
|
|
// CHECK3-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat {
|
|
// CHECK3-NEXT: entry:
|
|
// CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[AA:%.*]] = alloca i16, align 2
|
|
// CHECK3-NEXT: [[B:%.*]] = alloca [10 x i32], align 4
|
|
// CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4
|
|
// CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4
|
|
// CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4
|
|
// CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK3-NEXT: store i16 0, i16* [[AA]], align 2
|
|
// CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK3-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
|
|
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
|
|
// CHECK3-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
|
|
// CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
|
|
// CHECK3-NEXT: store i16 [[TMP2]], i16* [[CONV]], align 2
|
|
// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
|
|
// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40
|
|
// CHECK3-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
|
|
// CHECK3: omp_if.then:
|
|
// CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i32*
|
|
// CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP6]], align 4
|
|
// CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32*
|
|
// CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4
|
|
// CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
|
|
// CHECK3-NEXT: store i8* null, i8** [[TMP9]], align 4
|
|
// CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
|
|
// CHECK3-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i32*
|
|
// CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP11]], align 4
|
|
// CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
|
|
// CHECK3-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32*
|
|
// CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4
|
|
// CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
|
|
// CHECK3-NEXT: store i8* null, i8** [[TMP14]], align 4
|
|
// CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
|
|
// CHECK3-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]**
|
|
// CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 4
|
|
// CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
|
|
// CHECK3-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]**
|
|
// CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 4
|
|
// CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
|
|
// CHECK3-NEXT: store i8* null, i8** [[TMP19]], align 4
|
|
// CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.15, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.16, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
|
|
// CHECK3-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0
|
|
// CHECK3-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
|
// CHECK3: omp_offload.failed:
|
|
// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]]
|
|
// CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
|
// CHECK3: omp_offload.cont:
|
|
// CHECK3-NEXT: br label [[OMP_IF_END:%.*]]
|
|
// CHECK3: omp_if.else:
|
|
// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]]
|
|
// CHECK3-NEXT: br label [[OMP_IF_END]]
|
|
// CHECK3: omp_if.end:
|
|
// CHECK3-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK3-NEXT: ret i32 [[TMP24]]
|
|
//
|
|
//
|
|
// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216
|
|
// CHECK3-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {
|
|
// CHECK3-NEXT: entry:
|
|
// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
|
|
// CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4
|
|
// CHECK3-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
|
|
// CHECK3-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
|
|
// CHECK3-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4
|
|
// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4
|
|
// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]])
|
|
// CHECK3-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..9
|
|
// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR3]] {
|
|
// CHECK3-NEXT: entry:
|
|
// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
|
|
// CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4
|
|
// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
|
|
// CHECK3-NEXT: [[TMP:%.*]] = alloca i64, align 4
|
|
// CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
|
|
// CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
|
|
// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
|
|
// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[IT:%.*]] = alloca i64, align 8
|
|
// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK3-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
|
|
// CHECK3-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
|
|
// CHECK3-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
|
|
// CHECK3-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK3-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK3-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
|
|
// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK3-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
|
|
// CHECK3-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
|
|
// CHECK3-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK3-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 3
|
|
// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK3: cond.true:
|
|
// CHECK3-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK3: cond.false:
|
|
// CHECK3-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK3-NEXT: br label [[COND_END]]
|
|
// CHECK3: cond.end:
|
|
// CHECK3-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
|
|
// CHECK3-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
|
|
// CHECK3-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK3-NEXT: store i64 [[TMP8]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK3: omp.inner.for.cond:
|
|
// CHECK3-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !39
|
|
// CHECK3-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !39
|
|
// CHECK3-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]]
|
|
// CHECK3-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK3: omp.inner.for.body:
|
|
// CHECK3-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !39
|
|
// CHECK3-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400
|
|
// CHECK3-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]
|
|
// CHECK3-NEXT: store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !39
|
|
// CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[B_ADDR]], align 4, !llvm.access.group !39
|
|
// CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP12]] to double
|
|
// CHECK3-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00
|
|
// CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
|
|
// CHECK3-NEXT: store double [[ADD]], double* [[A]], align 4, !llvm.access.group !39
|
|
// CHECK3-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP13:%.*]] = load double, double* [[A4]], align 4, !llvm.access.group !39
|
|
// CHECK3-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00
|
|
// CHECK3-NEXT: store double [[INC]], double* [[A4]], align 4, !llvm.access.group !39
|
|
// CHECK3-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16
|
|
// CHECK3-NEXT: [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]]
|
|
// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP14]]
|
|
// CHECK3-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
|
|
// CHECK3-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2, !llvm.access.group !39
|
|
// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK3: omp.body.continue:
|
|
// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK3: omp.inner.for.inc:
|
|
// CHECK3-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !39
|
|
// CHECK3-NEXT: [[ADD7:%.*]] = add i64 [[TMP15]], 1
|
|
// CHECK3-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !39
|
|
// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP40:![0-9]+]]
|
|
// CHECK3: omp.inner.for.end:
|
|
// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK3: omp.loop.exit:
|
|
// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
|
|
// CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK3-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0
|
|
// CHECK3-NEXT: br i1 [[TMP17]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
|
|
// CHECK3: .omp.final.then:
|
|
// CHECK3-NEXT: store i64 400, i64* [[IT]], align 8
|
|
// CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]]
|
|
// CHECK3: .omp.final.done:
|
|
// CHECK3-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195
|
|
// CHECK3-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
|
|
// CHECK3-NEXT: entry:
|
|
// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
|
|
// CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
|
|
// CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
|
|
// CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
|
|
// CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
|
|
// CHECK3-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
|
|
// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
|
|
// CHECK3-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
|
|
// CHECK3-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
|
|
// CHECK3-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2
|
|
// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
|
|
// CHECK3-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 4
|
|
// CHECK3-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
|
|
// CHECK3-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1
|
|
// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
|
|
// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]])
|
|
// CHECK3-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..11
|
|
// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] {
|
|
// CHECK3-NEXT: entry:
|
|
// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
|
|
// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
|
|
// CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
|
|
// CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
|
|
// CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
|
|
// CHECK3-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
|
|
// CHECK3-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178
|
|
// CHECK3-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
|
|
// CHECK3-NEXT: entry:
|
|
// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
|
|
// CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
|
|
// CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
|
|
// CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
|
|
// CHECK3-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
|
|
// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
|
|
// CHECK3-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
|
|
// CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
|
|
// CHECK3-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2
|
|
// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
|
|
// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]])
|
|
// CHECK3-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..14
|
|
// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] {
|
|
// CHECK3-NEXT: entry:
|
|
// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
|
|
// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
|
|
// CHECK3-NEXT: [[TMP:%.*]] = alloca i64, align 4
|
|
// CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
|
|
// CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
|
|
// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
|
|
// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[I:%.*]] = alloca i64, align 8
|
|
// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
|
|
// CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
|
|
// CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
|
|
// CHECK3-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
|
|
// CHECK3-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK3-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK3-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
|
|
// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK3-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
|
|
// CHECK3-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
|
|
// CHECK3-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6
|
|
// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK3: cond.true:
|
|
// CHECK3-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK3: cond.false:
|
|
// CHECK3-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK3-NEXT: br label [[COND_END]]
|
|
// CHECK3: cond.end:
|
|
// CHECK3-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
|
|
// CHECK3-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
|
|
// CHECK3-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK3-NEXT: store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK3: omp.inner.for.cond:
|
|
// CHECK3-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !42
|
|
// CHECK3-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !42
|
|
// CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]]
|
|
// CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK3: omp.inner.for.body:
|
|
// CHECK3-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !42
|
|
// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3
|
|
// CHECK3-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
|
|
// CHECK3-NEXT: store i64 [[ADD]], i64* [[I]], align 8, !llvm.access.group !42
|
|
// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !42
|
|
// CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
|
|
// CHECK3-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4, !llvm.access.group !42
|
|
// CHECK3-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !42
|
|
// CHECK3-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32
|
|
// CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
|
|
// CHECK3-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
|
|
// CHECK3-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 4, !llvm.access.group !42
|
|
// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
|
|
// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !42
|
|
// CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1
|
|
// CHECK3-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !42
|
|
// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK3: omp.body.continue:
|
|
// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK3: omp.inner.for.inc:
|
|
// CHECK3-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !42
|
|
// CHECK3-NEXT: [[ADD7:%.*]] = add nsw i64 [[TMP12]], 1
|
|
// CHECK3-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !42
|
|
// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP43:![0-9]+]]
|
|
// CHECK3: omp.inner.for.end:
|
|
// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK3: omp.loop.exit:
|
|
// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
|
|
// CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK3-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
|
|
// CHECK3-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
|
|
// CHECK3: .omp.final.then:
|
|
// CHECK3-NEXT: store i64 11, i64* [[I]], align 8
|
|
// CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]]
|
|
// CHECK3: .omp.final.done:
|
|
// CHECK3-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK3-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
|
|
// CHECK3-SAME: () #[[ATTR7:[0-9]+]] {
|
|
// CHECK3-NEXT: entry:
|
|
// CHECK3-NEXT: call void @__tgt_register_requires(i64 1)
|
|
// CHECK3-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK4-LABEL: define {{[^@]+}}@_Z7get_valv
|
|
// CHECK4-SAME: () #[[ATTR0:[0-9]+]] {
|
|
// CHECK4-NEXT: entry:
|
|
// CHECK4-NEXT: ret i64 0
|
|
//
|
|
//
|
|
// CHECK4-LABEL: define {{[^@]+}}@_Z3fooi
|
|
// CHECK4-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
|
|
// CHECK4-NEXT: entry:
|
|
// CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[AA:%.*]] = alloca i16, align 2
|
|
// CHECK4-NEXT: [[B:%.*]] = alloca [10 x float], align 4
|
|
// CHECK4-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4
|
|
// CHECK4-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8
|
|
// CHECK4-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4
|
|
// CHECK4-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 1
|
|
// CHECK4-NEXT: [[K:%.*]] = alloca i64, align 8
|
|
// CHECK4-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[LIN:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[A_CASTED2:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4
|
|
// CHECK4-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4
|
|
// CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4
|
|
// CHECK4-NEXT: [[A_CASTED3:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[AA_CASTED4:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS6:%.*]] = alloca [2 x i8*], align 4
|
|
// CHECK4-NEXT: [[DOTOFFLOAD_PTRS7:%.*]] = alloca [2 x i8*], align 4
|
|
// CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS8:%.*]] = alloca [2 x i8*], align 4
|
|
// CHECK4-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[A_CASTED11:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS14:%.*]] = alloca [10 x i8*], align 4
|
|
// CHECK4-NEXT: [[DOTOFFLOAD_PTRS15:%.*]] = alloca [10 x i8*], align 4
|
|
// CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS16:%.*]] = alloca [10 x i8*], align 4
|
|
// CHECK4-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 4
|
|
// CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]])
|
|
// CHECK4-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK4-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK4-NEXT: store i16 0, i16* [[AA]], align 2
|
|
// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK4-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave()
|
|
// CHECK4-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4
|
|
// CHECK4-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP1]], align 4
|
|
// CHECK4-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4
|
|
// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK4-NEXT: [[TMP4:%.*]] = mul nuw i32 5, [[TMP3]]
|
|
// CHECK4-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP4]], align 8
|
|
// CHECK4-NEXT: store i32 [[TMP3]], i32* [[__VLA_EXPR1]], align 4
|
|
// CHECK4-NEXT: [[TMP5:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 1, i32 20, i32 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1)
|
|
// CHECK4-NEXT: [[TMP6:%.*]] = bitcast i8* [[TMP5]] to %struct.kmp_task_t_with_privates*
|
|
// CHECK4-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP6]], i32 0, i32 0
|
|
// CHECK4-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i8* [[TMP5]])
|
|
// CHECK4-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv()
|
|
// CHECK4-NEXT: store i64 [[CALL]], i64* [[K]], align 8
|
|
// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK4-NEXT: store i32 [[TMP9]], i32* [[A_CASTED]], align 4
|
|
// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[A_CASTED]], align 4
|
|
// CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101(i32 [[TMP10]], i64* [[K]]) #[[ATTR4:[0-9]+]]
|
|
// CHECK4-NEXT: store i32 12, i32* [[LIN]], align 4
|
|
// CHECK4-NEXT: [[TMP11:%.*]] = load i16, i16* [[AA]], align 2
|
|
// CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
|
|
// CHECK4-NEXT: store i16 [[TMP11]], i16* [[CONV]], align 2
|
|
// CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[AA_CASTED]], align 4
|
|
// CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[LIN]], align 4
|
|
// CHECK4-NEXT: store i32 [[TMP13]], i32* [[LIN_CASTED]], align 4
|
|
// CHECK4-NEXT: [[TMP14:%.*]] = load i32, i32* [[LIN_CASTED]], align 4
|
|
// CHECK4-NEXT: [[TMP15:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK4-NEXT: store i32 [[TMP15]], i32* [[A_CASTED2]], align 4
|
|
// CHECK4-NEXT: [[TMP16:%.*]] = load i32, i32* [[A_CASTED2]], align 4
|
|
// CHECK4-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK4-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32*
|
|
// CHECK4-NEXT: store i32 [[TMP12]], i32* [[TMP18]], align 4
|
|
// CHECK4-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK4-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32*
|
|
// CHECK4-NEXT: store i32 [[TMP12]], i32* [[TMP20]], align 4
|
|
// CHECK4-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
|
|
// CHECK4-NEXT: store i8* null, i8** [[TMP21]], align 4
|
|
// CHECK4-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
|
|
// CHECK4-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i32*
|
|
// CHECK4-NEXT: store i32 [[TMP14]], i32* [[TMP23]], align 4
|
|
// CHECK4-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
|
|
// CHECK4-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i32*
|
|
// CHECK4-NEXT: store i32 [[TMP14]], i32* [[TMP25]], align 4
|
|
// CHECK4-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
|
|
// CHECK4-NEXT: store i8* null, i8** [[TMP26]], align 4
|
|
// CHECK4-NEXT: [[TMP27:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
|
|
// CHECK4-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i32*
|
|
// CHECK4-NEXT: store i32 [[TMP16]], i32* [[TMP28]], align 4
|
|
// CHECK4-NEXT: [[TMP29:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
|
|
// CHECK4-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i32*
|
|
// CHECK4-NEXT: store i32 [[TMP16]], i32* [[TMP30]], align 4
|
|
// CHECK4-NEXT: [[TMP31:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
|
|
// CHECK4-NEXT: store i8* null, i8** [[TMP31]], align 4
|
|
// CHECK4-NEXT: [[TMP32:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK4-NEXT: [[TMP33:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK4-NEXT: [[TMP34:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108.region_id, i32 3, i8** [[TMP32]], i8** [[TMP33]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
|
|
// CHECK4-NEXT: [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 0
|
|
// CHECK4-NEXT: br i1 [[TMP35]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
|
// CHECK4: omp_offload.failed:
|
|
// CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108(i32 [[TMP12]], i32 [[TMP14]], i32 [[TMP16]]) #[[ATTR4]]
|
|
// CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
|
// CHECK4: omp_offload.cont:
|
|
// CHECK4-NEXT: [[TMP36:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK4-NEXT: store i32 [[TMP36]], i32* [[A_CASTED3]], align 4
|
|
// CHECK4-NEXT: [[TMP37:%.*]] = load i32, i32* [[A_CASTED3]], align 4
|
|
// CHECK4-NEXT: [[TMP38:%.*]] = load i16, i16* [[AA]], align 2
|
|
// CHECK4-NEXT: [[CONV5:%.*]] = bitcast i32* [[AA_CASTED4]] to i16*
|
|
// CHECK4-NEXT: store i16 [[TMP38]], i16* [[CONV5]], align 2
|
|
// CHECK4-NEXT: [[TMP39:%.*]] = load i32, i32* [[AA_CASTED4]], align 4
|
|
// CHECK4-NEXT: [[TMP40:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP40]], 10
|
|
// CHECK4-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
|
|
// CHECK4: omp_if.then:
|
|
// CHECK4-NEXT: [[TMP41:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0
|
|
// CHECK4-NEXT: [[TMP42:%.*]] = bitcast i8** [[TMP41]] to i32*
|
|
// CHECK4-NEXT: store i32 [[TMP37]], i32* [[TMP42]], align 4
|
|
// CHECK4-NEXT: [[TMP43:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0
|
|
// CHECK4-NEXT: [[TMP44:%.*]] = bitcast i8** [[TMP43]] to i32*
|
|
// CHECK4-NEXT: store i32 [[TMP37]], i32* [[TMP44]], align 4
|
|
// CHECK4-NEXT: [[TMP45:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS8]], i32 0, i32 0
|
|
// CHECK4-NEXT: store i8* null, i8** [[TMP45]], align 4
|
|
// CHECK4-NEXT: [[TMP46:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 1
|
|
// CHECK4-NEXT: [[TMP47:%.*]] = bitcast i8** [[TMP46]] to i32*
|
|
// CHECK4-NEXT: store i32 [[TMP39]], i32* [[TMP47]], align 4
|
|
// CHECK4-NEXT: [[TMP48:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 1
|
|
// CHECK4-NEXT: [[TMP49:%.*]] = bitcast i8** [[TMP48]] to i32*
|
|
// CHECK4-NEXT: store i32 [[TMP39]], i32* [[TMP49]], align 4
|
|
// CHECK4-NEXT: [[TMP50:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS8]], i32 0, i32 1
|
|
// CHECK4-NEXT: store i8* null, i8** [[TMP50]], align 4
|
|
// CHECK4-NEXT: [[TMP51:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0
|
|
// CHECK4-NEXT: [[TMP52:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0
|
|
// CHECK4-NEXT: [[TMP53:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116.region_id, i32 2, i8** [[TMP51]], i8** [[TMP52]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
|
|
// CHECK4-NEXT: [[TMP54:%.*]] = icmp ne i32 [[TMP53]], 0
|
|
// CHECK4-NEXT: br i1 [[TMP54]], label [[OMP_OFFLOAD_FAILED9:%.*]], label [[OMP_OFFLOAD_CONT10:%.*]]
|
|
// CHECK4: omp_offload.failed9:
|
|
// CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116(i32 [[TMP37]], i32 [[TMP39]]) #[[ATTR4]]
|
|
// CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT10]]
|
|
// CHECK4: omp_offload.cont10:
|
|
// CHECK4-NEXT: br label [[OMP_IF_END:%.*]]
|
|
// CHECK4: omp_if.else:
|
|
// CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116(i32 [[TMP37]], i32 [[TMP39]]) #[[ATTR4]]
|
|
// CHECK4-NEXT: br label [[OMP_IF_END]]
|
|
// CHECK4: omp_if.end:
|
|
// CHECK4-NEXT: [[TMP55:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK4-NEXT: store i32 [[TMP55]], i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK4-NEXT: [[TMP56:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK4-NEXT: store i32 [[TMP56]], i32* [[A_CASTED11]], align 4
|
|
// CHECK4-NEXT: [[TMP57:%.*]] = load i32, i32* [[A_CASTED11]], align 4
|
|
// CHECK4-NEXT: [[TMP58:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK4-NEXT: store i32 [[TMP58]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
|
|
// CHECK4-NEXT: [[TMP59:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
|
|
// CHECK4-NEXT: [[TMP60:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK4-NEXT: [[CMP12:%.*]] = icmp sgt i32 [[TMP60]], 20
|
|
// CHECK4-NEXT: br i1 [[CMP12]], label [[OMP_IF_THEN13:%.*]], label [[OMP_IF_ELSE19:%.*]]
|
|
// CHECK4: omp_if.then13:
|
|
// CHECK4-NEXT: [[TMP61:%.*]] = mul nuw i32 [[TMP1]], 4
|
|
// CHECK4-NEXT: [[TMP62:%.*]] = sext i32 [[TMP61]] to i64
|
|
// CHECK4-NEXT: [[TMP63:%.*]] = mul nuw i32 5, [[TMP3]]
|
|
// CHECK4-NEXT: [[TMP64:%.*]] = mul nuw i32 [[TMP63]], 8
|
|
// CHECK4-NEXT: [[TMP65:%.*]] = sext i32 [[TMP64]] to i64
|
|
// CHECK4-NEXT: [[TMP66:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 0
|
|
// CHECK4-NEXT: [[TMP67:%.*]] = bitcast i8** [[TMP66]] to i32*
|
|
// CHECK4-NEXT: store i32 [[TMP57]], i32* [[TMP67]], align 4
|
|
// CHECK4-NEXT: [[TMP68:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 0
|
|
// CHECK4-NEXT: [[TMP69:%.*]] = bitcast i8** [[TMP68]] to i32*
|
|
// CHECK4-NEXT: store i32 [[TMP57]], i32* [[TMP69]], align 4
|
|
// CHECK4-NEXT: [[TMP70:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
|
|
// CHECK4-NEXT: store i64 4, i64* [[TMP70]], align 4
|
|
// CHECK4-NEXT: [[TMP71:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 0
|
|
// CHECK4-NEXT: store i8* null, i8** [[TMP71]], align 4
|
|
// CHECK4-NEXT: [[TMP72:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 1
|
|
// CHECK4-NEXT: [[TMP73:%.*]] = bitcast i8** [[TMP72]] to [10 x float]**
|
|
// CHECK4-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP73]], align 4
|
|
// CHECK4-NEXT: [[TMP74:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 1
|
|
// CHECK4-NEXT: [[TMP75:%.*]] = bitcast i8** [[TMP74]] to [10 x float]**
|
|
// CHECK4-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP75]], align 4
|
|
// CHECK4-NEXT: [[TMP76:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1
|
|
// CHECK4-NEXT: store i64 40, i64* [[TMP76]], align 4
|
|
// CHECK4-NEXT: [[TMP77:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 1
|
|
// CHECK4-NEXT: store i8* null, i8** [[TMP77]], align 4
|
|
// CHECK4-NEXT: [[TMP78:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 2
|
|
// CHECK4-NEXT: [[TMP79:%.*]] = bitcast i8** [[TMP78]] to i32*
|
|
// CHECK4-NEXT: store i32 [[TMP1]], i32* [[TMP79]], align 4
|
|
// CHECK4-NEXT: [[TMP80:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 2
|
|
// CHECK4-NEXT: [[TMP81:%.*]] = bitcast i8** [[TMP80]] to i32*
|
|
// CHECK4-NEXT: store i32 [[TMP1]], i32* [[TMP81]], align 4
|
|
// CHECK4-NEXT: [[TMP82:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2
|
|
// CHECK4-NEXT: store i64 4, i64* [[TMP82]], align 4
|
|
// CHECK4-NEXT: [[TMP83:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 2
|
|
// CHECK4-NEXT: store i8* null, i8** [[TMP83]], align 4
|
|
// CHECK4-NEXT: [[TMP84:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 3
|
|
// CHECK4-NEXT: [[TMP85:%.*]] = bitcast i8** [[TMP84]] to float**
|
|
// CHECK4-NEXT: store float* [[VLA]], float** [[TMP85]], align 4
|
|
// CHECK4-NEXT: [[TMP86:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 3
|
|
// CHECK4-NEXT: [[TMP87:%.*]] = bitcast i8** [[TMP86]] to float**
|
|
// CHECK4-NEXT: store float* [[VLA]], float** [[TMP87]], align 4
|
|
// CHECK4-NEXT: [[TMP88:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3
|
|
// CHECK4-NEXT: store i64 [[TMP62]], i64* [[TMP88]], align 4
|
|
// CHECK4-NEXT: [[TMP89:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 3
|
|
// CHECK4-NEXT: store i8* null, i8** [[TMP89]], align 4
|
|
// CHECK4-NEXT: [[TMP90:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 4
|
|
// CHECK4-NEXT: [[TMP91:%.*]] = bitcast i8** [[TMP90]] to [5 x [10 x double]]**
|
|
// CHECK4-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP91]], align 4
|
|
// CHECK4-NEXT: [[TMP92:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 4
|
|
// CHECK4-NEXT: [[TMP93:%.*]] = bitcast i8** [[TMP92]] to [5 x [10 x double]]**
|
|
// CHECK4-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP93]], align 4
|
|
// CHECK4-NEXT: [[TMP94:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4
|
|
// CHECK4-NEXT: store i64 400, i64* [[TMP94]], align 4
|
|
// CHECK4-NEXT: [[TMP95:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 4
|
|
// CHECK4-NEXT: store i8* null, i8** [[TMP95]], align 4
|
|
// CHECK4-NEXT: [[TMP96:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 5
|
|
// CHECK4-NEXT: [[TMP97:%.*]] = bitcast i8** [[TMP96]] to i32*
|
|
// CHECK4-NEXT: store i32 5, i32* [[TMP97]], align 4
|
|
// CHECK4-NEXT: [[TMP98:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 5
|
|
// CHECK4-NEXT: [[TMP99:%.*]] = bitcast i8** [[TMP98]] to i32*
|
|
// CHECK4-NEXT: store i32 5, i32* [[TMP99]], align 4
|
|
// CHECK4-NEXT: [[TMP100:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 5
|
|
// CHECK4-NEXT: store i64 4, i64* [[TMP100]], align 4
|
|
// CHECK4-NEXT: [[TMP101:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 5
|
|
// CHECK4-NEXT: store i8* null, i8** [[TMP101]], align 4
|
|
// CHECK4-NEXT: [[TMP102:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 6
|
|
// CHECK4-NEXT: [[TMP103:%.*]] = bitcast i8** [[TMP102]] to i32*
|
|
// CHECK4-NEXT: store i32 [[TMP3]], i32* [[TMP103]], align 4
|
|
// CHECK4-NEXT: [[TMP104:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 6
|
|
// CHECK4-NEXT: [[TMP105:%.*]] = bitcast i8** [[TMP104]] to i32*
|
|
// CHECK4-NEXT: store i32 [[TMP3]], i32* [[TMP105]], align 4
|
|
// CHECK4-NEXT: [[TMP106:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 6
|
|
// CHECK4-NEXT: store i64 4, i64* [[TMP106]], align 4
|
|
// CHECK4-NEXT: [[TMP107:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 6
|
|
// CHECK4-NEXT: store i8* null, i8** [[TMP107]], align 4
|
|
// CHECK4-NEXT: [[TMP108:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 7
|
|
// CHECK4-NEXT: [[TMP109:%.*]] = bitcast i8** [[TMP108]] to double**
|
|
// CHECK4-NEXT: store double* [[VLA1]], double** [[TMP109]], align 4
|
|
// CHECK4-NEXT: [[TMP110:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 7
|
|
// CHECK4-NEXT: [[TMP111:%.*]] = bitcast i8** [[TMP110]] to double**
|
|
// CHECK4-NEXT: store double* [[VLA1]], double** [[TMP111]], align 4
|
|
// CHECK4-NEXT: [[TMP112:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7
|
|
// CHECK4-NEXT: store i64 [[TMP65]], i64* [[TMP112]], align 4
|
|
// CHECK4-NEXT: [[TMP113:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 7
|
|
// CHECK4-NEXT: store i8* null, i8** [[TMP113]], align 4
|
|
// CHECK4-NEXT: [[TMP114:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 8
|
|
// CHECK4-NEXT: [[TMP115:%.*]] = bitcast i8** [[TMP114]] to %struct.TT**
|
|
// CHECK4-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP115]], align 4
|
|
// CHECK4-NEXT: [[TMP116:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 8
|
|
// CHECK4-NEXT: [[TMP117:%.*]] = bitcast i8** [[TMP116]] to %struct.TT**
|
|
// CHECK4-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP117]], align 4
|
|
// CHECK4-NEXT: [[TMP118:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 8
|
|
// CHECK4-NEXT: store i64 12, i64* [[TMP118]], align 4
|
|
// CHECK4-NEXT: [[TMP119:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 8
|
|
// CHECK4-NEXT: store i8* null, i8** [[TMP119]], align 4
|
|
// CHECK4-NEXT: [[TMP120:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 9
|
|
// CHECK4-NEXT: [[TMP121:%.*]] = bitcast i8** [[TMP120]] to i32*
|
|
// CHECK4-NEXT: store i32 [[TMP59]], i32* [[TMP121]], align 4
|
|
// CHECK4-NEXT: [[TMP122:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 9
|
|
// CHECK4-NEXT: [[TMP123:%.*]] = bitcast i8** [[TMP122]] to i32*
|
|
// CHECK4-NEXT: store i32 [[TMP59]], i32* [[TMP123]], align 4
|
|
// CHECK4-NEXT: [[TMP124:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 9
|
|
// CHECK4-NEXT: store i64 4, i64* [[TMP124]], align 4
|
|
// CHECK4-NEXT: [[TMP125:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 9
|
|
// CHECK4-NEXT: store i8* null, i8** [[TMP125]], align 4
|
|
// CHECK4-NEXT: [[TMP126:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 0
|
|
// CHECK4-NEXT: [[TMP127:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 0
|
|
// CHECK4-NEXT: [[TMP128:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
|
|
// CHECK4-NEXT: [[TMP129:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140.region_id, i32 10, i8** [[TMP126]], i8** [[TMP127]], i64* [[TMP128]], i64* getelementptr inbounds ([10 x i64], [10 x i64]* @.offload_maptypes.8, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
|
|
// CHECK4-NEXT: [[TMP130:%.*]] = icmp ne i32 [[TMP129]], 0
|
|
// CHECK4-NEXT: br i1 [[TMP130]], label [[OMP_OFFLOAD_FAILED17:%.*]], label [[OMP_OFFLOAD_CONT18:%.*]]
|
|
// CHECK4: omp_offload.failed17:
|
|
// CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140(i32 [[TMP57]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]], i32 [[TMP59]]) #[[ATTR4]]
|
|
// CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT18]]
|
|
// CHECK4: omp_offload.cont18:
|
|
// CHECK4-NEXT: br label [[OMP_IF_END20:%.*]]
|
|
// CHECK4: omp_if.else19:
|
|
// CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140(i32 [[TMP57]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]], i32 [[TMP59]]) #[[ATTR4]]
|
|
// CHECK4-NEXT: br label [[OMP_IF_END20]]
|
|
// CHECK4: omp_if.end20:
|
|
// CHECK4-NEXT: [[TMP131:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK4-NEXT: [[TMP132:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
|
|
// CHECK4-NEXT: call void @llvm.stackrestore(i8* [[TMP132]])
|
|
// CHECK4-NEXT: ret i32 [[TMP131]]
|
|
//
|
|
//
|
|
// CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96
|
|
// CHECK4-SAME: () #[[ATTR2:[0-9]+]] {
|
|
// CHECK4-NEXT: entry:
|
|
// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
|
|
// CHECK4-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined.
|
|
// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] {
|
|
// CHECK4-NEXT: entry:
|
|
// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK4-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
|
|
// CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
|
|
// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5
|
|
// CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK4: cond.true:
|
|
// CHECK4-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK4: cond.false:
|
|
// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK4-NEXT: br label [[COND_END]]
|
|
// CHECK4: cond.end:
|
|
// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
|
|
// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK4-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK4: omp.inner.for.cond:
|
|
// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
|
|
// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !11
|
|
// CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
|
|
// CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK4: omp.inner.for.body:
|
|
// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
|
|
// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5
|
|
// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]]
|
|
// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11
|
|
// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK4: omp.body.continue:
|
|
// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK4: omp.inner.for.inc:
|
|
// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
|
|
// CHECK4-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
|
|
// CHECK4-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
|
|
// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]
|
|
// CHECK4: omp.inner.for.end:
|
|
// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK4: omp.loop.exit:
|
|
// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
|
|
// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK4-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0
|
|
// CHECK4-NEXT: br i1 [[TMP10]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
|
|
// CHECK4: .omp.final.then:
|
|
// CHECK4-NEXT: store i32 33, i32* [[I]], align 4
|
|
// CHECK4-NEXT: br label [[DOTOMP_FINAL_DONE]]
|
|
// CHECK4: .omp.final.done:
|
|
// CHECK4-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK4-LABEL: define {{[^@]+}}@.omp_task_entry.
|
|
// CHECK4-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] {
|
|
// CHECK4-NEXT: entry:
|
|
// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 4
|
|
// CHECK4-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 4
|
|
// CHECK4-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 4
|
|
// CHECK4-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 4
|
|
// CHECK4-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 4
|
|
// CHECK4-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 4
|
|
// CHECK4-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4
|
|
// CHECK4-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4
|
|
// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4
|
|
// CHECK4-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4
|
|
// CHECK4-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
|
|
// CHECK4-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
|
|
// CHECK4-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0
|
|
// CHECK4-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 4
|
|
// CHECK4-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon*
|
|
// CHECK4-NEXT: [[TMP9:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8*
|
|
// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META17:![0-9]+]])
|
|
// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]])
|
|
// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META22:![0-9]+]])
|
|
// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META24:![0-9]+]])
|
|
// CHECK4-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !26
|
|
// CHECK4-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 4, !noalias !26
|
|
// CHECK4-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !26
|
|
// CHECK4-NEXT: store void (i8*, ...)* null, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !26
|
|
// CHECK4-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 4, !noalias !26
|
|
// CHECK4-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !26
|
|
// CHECK4-NEXT: [[TMP10:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !26
|
|
// CHECK4-NEXT: [[TMP11:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 0, i32 0, i8* null, i32 0, i8* null) #[[ATTR4]]
|
|
// CHECK4-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
|
|
// CHECK4-NEXT: br i1 [[TMP12]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]]
|
|
// CHECK4: omp_offload.failed.i:
|
|
// CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96() #[[ATTR4]]
|
|
// CHECK4-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]]
|
|
// CHECK4: .omp_outlined..1.exit:
|
|
// CHECK4-NEXT: ret i32 0
|
|
//
|
|
//
|
|
// CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101
|
|
// CHECK4-SAME: (i32 [[A:%.*]], i64* nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR3]] {
|
|
// CHECK4-NEXT: entry:
|
|
// CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[K_ADDR:%.*]] = alloca i64*, align 4
|
|
// CHECK4-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK4-NEXT: store i64* [[K]], i64** [[K_ADDR]], align 4
|
|
// CHECK4-NEXT: [[TMP0:%.*]] = load i64*, i64** [[K_ADDR]], align 4
|
|
// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK4-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
|
|
// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
|
|
// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i64*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP2]], i64* [[TMP0]])
|
|
// CHECK4-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..2
|
|
// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i64* nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR3]] {
|
|
// CHECK4-NEXT: entry:
|
|
// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[K_ADDR:%.*]] = alloca i64*, align 4
|
|
// CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[DOTLINEAR_START:%.*]] = alloca i64, align 8
|
|
// CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[K1:%.*]] = alloca i64, align 8
|
|
// CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK4-NEXT: store i64* [[K]], i64** [[K_ADDR]], align 4
|
|
// CHECK4-NEXT: [[TMP0:%.*]] = load i64*, i64** [[K_ADDR]], align 4
|
|
// CHECK4-NEXT: [[TMP1:%.*]] = load i64, i64* [[TMP0]], align 8
|
|
// CHECK4-NEXT: store i64 [[TMP1]], i64* [[DOTLINEAR_START]], align 8
|
|
// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK4-NEXT: store i32 8, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK4-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
|
|
// CHECK4-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP3]])
|
|
// CHECK4-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 35, i32 0, i32 8, i32 1, i32 1)
|
|
// CHECK4-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
|
|
// CHECK4: omp.dispatch.cond:
|
|
// CHECK4-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
|
|
// CHECK4-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP4]], 0
|
|
// CHECK4-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
|
|
// CHECK4: omp.dispatch.body:
|
|
// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK4-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK4: omp.inner.for.cond:
|
|
// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27
|
|
// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !27
|
|
// CHECK4-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
|
|
// CHECK4-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK4: omp.inner.for.body:
|
|
// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27
|
|
// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
|
|
// CHECK4-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL]]
|
|
// CHECK4-NEXT: store i32 [[SUB]], i32* [[I]], align 4, !llvm.access.group !27
|
|
// CHECK4-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8, !llvm.access.group !27
|
|
// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27
|
|
// CHECK4-NEXT: [[MUL2:%.*]] = mul nsw i32 [[TMP10]], 3
|
|
// CHECK4-NEXT: [[CONV:%.*]] = sext i32 [[MUL2]] to i64
|
|
// CHECK4-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP9]], [[CONV]]
|
|
// CHECK4-NEXT: store i64 [[ADD]], i64* [[K1]], align 8, !llvm.access.group !27
|
|
// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !27
|
|
// CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP11]], 1
|
|
// CHECK4-NEXT: store i32 [[ADD3]], i32* [[A_ADDR]], align 4, !llvm.access.group !27
|
|
// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK4: omp.body.continue:
|
|
// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK4: omp.inner.for.inc:
|
|
// CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27
|
|
// CHECK4-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1
|
|
// CHECK4-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27
|
|
// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]]
|
|
// CHECK4: omp.inner.for.end:
|
|
// CHECK4-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
|
|
// CHECK4: omp.dispatch.inc:
|
|
// CHECK4-NEXT: br label [[OMP_DISPATCH_COND]]
|
|
// CHECK4: omp.dispatch.end:
|
|
// CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK4-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
|
|
// CHECK4-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
|
|
// CHECK4: .omp.final.then:
|
|
// CHECK4-NEXT: store i32 1, i32* [[I]], align 4
|
|
// CHECK4-NEXT: br label [[DOTOMP_FINAL_DONE]]
|
|
// CHECK4: .omp.final.done:
|
|
// CHECK4-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK4-NEXT: [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0
|
|
// CHECK4-NEXT: br i1 [[TMP16]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
|
|
// CHECK4: .omp.linear.pu:
|
|
// CHECK4-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8
|
|
// CHECK4-NEXT: [[ADD5:%.*]] = add nsw i64 [[TMP17]], 27
|
|
// CHECK4-NEXT: store i64 [[ADD5]], i64* [[TMP0]], align 8
|
|
// CHECK4-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]]
|
|
// CHECK4: .omp.linear.pu.done:
|
|
// CHECK4-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108
|
|
// CHECK4-SAME: (i32 [[AA:%.*]], i32 [[LIN:%.*]], i32 [[A:%.*]]) #[[ATTR2]] {
|
|
// CHECK4-NEXT: entry:
|
|
// CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
|
|
// CHECK4-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4
|
|
// CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
|
|
// CHECK4-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
|
|
// CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
|
|
// CHECK4-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
|
|
// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
|
|
// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[LIN_ADDR]], align 4
|
|
// CHECK4-NEXT: store i32 [[TMP2]], i32* [[LIN_CASTED]], align 4
|
|
// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[LIN_CASTED]], align 4
|
|
// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK4-NEXT: store i32 [[TMP4]], i32* [[A_CASTED]], align 4
|
|
// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[A_CASTED]], align 4
|
|
// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]])
|
|
// CHECK4-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..3
|
|
// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]], i32 [[LIN:%.*]], i32 [[A:%.*]]) #[[ATTR3]] {
|
|
// CHECK4-NEXT: entry:
|
|
// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
|
|
// CHECK4-NEXT: [[TMP:%.*]] = alloca i64, align 4
|
|
// CHECK4-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[DOTLINEAR_START1:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8
|
|
// CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
|
|
// CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
|
|
// CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
|
|
// CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[IT:%.*]] = alloca i64, align 8
|
|
// CHECK4-NEXT: [[LIN2:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[A3:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK4-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
|
|
// CHECK4-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4
|
|
// CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
|
|
// CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[LIN_ADDR]], align 4
|
|
// CHECK4-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4
|
|
// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK4-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START1]], align 4
|
|
// CHECK4-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv()
|
|
// CHECK4-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8
|
|
// CHECK4-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK4-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK4-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
|
|
// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK4-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
|
|
// CHECK4-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3]], i32 [[TMP3]])
|
|
// CHECK4-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
|
|
// CHECK4-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK4-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3
|
|
// CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK4: cond.true:
|
|
// CHECK4-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK4: cond.false:
|
|
// CHECK4-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK4-NEXT: br label [[COND_END]]
|
|
// CHECK4: cond.end:
|
|
// CHECK4-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
|
|
// CHECK4-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
|
|
// CHECK4-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK4-NEXT: store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK4: omp.inner.for.cond:
|
|
// CHECK4-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !30
|
|
// CHECK4-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !30
|
|
// CHECK4-NEXT: [[CMP4:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]]
|
|
// CHECK4-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK4: omp.inner.for.body:
|
|
// CHECK4-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !30
|
|
// CHECK4-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400
|
|
// CHECK4-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]
|
|
// CHECK4-NEXT: store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !30
|
|
// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4, !llvm.access.group !30
|
|
// CHECK4-NEXT: [[CONV5:%.*]] = sext i32 [[TMP10]] to i64
|
|
// CHECK4-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !30
|
|
// CHECK4-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !30
|
|
// CHECK4-NEXT: [[MUL6:%.*]] = mul i64 [[TMP11]], [[TMP12]]
|
|
// CHECK4-NEXT: [[ADD:%.*]] = add i64 [[CONV5]], [[MUL6]]
|
|
// CHECK4-NEXT: [[CONV7:%.*]] = trunc i64 [[ADD]] to i32
|
|
// CHECK4-NEXT: store i32 [[CONV7]], i32* [[LIN2]], align 4, !llvm.access.group !30
|
|
// CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START1]], align 4, !llvm.access.group !30
|
|
// CHECK4-NEXT: [[CONV8:%.*]] = sext i32 [[TMP13]] to i64
|
|
// CHECK4-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !30
|
|
// CHECK4-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !30
|
|
// CHECK4-NEXT: [[MUL9:%.*]] = mul i64 [[TMP14]], [[TMP15]]
|
|
// CHECK4-NEXT: [[ADD10:%.*]] = add i64 [[CONV8]], [[MUL9]]
|
|
// CHECK4-NEXT: [[CONV11:%.*]] = trunc i64 [[ADD10]] to i32
|
|
// CHECK4-NEXT: store i32 [[CONV11]], i32* [[A3]], align 4, !llvm.access.group !30
|
|
// CHECK4-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !30
|
|
// CHECK4-NEXT: [[CONV12:%.*]] = sext i16 [[TMP16]] to i32
|
|
// CHECK4-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1
|
|
// CHECK4-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16
|
|
// CHECK4-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 4, !llvm.access.group !30
|
|
// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK4: omp.body.continue:
|
|
// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK4: omp.inner.for.inc:
|
|
// CHECK4-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !30
|
|
// CHECK4-NEXT: [[ADD15:%.*]] = add i64 [[TMP17]], 1
|
|
// CHECK4-NEXT: store i64 [[ADD15]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !30
|
|
// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP31:![0-9]+]]
|
|
// CHECK4: omp.inner.for.end:
|
|
// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK4: omp.loop.exit:
|
|
// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
|
|
// CHECK4-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK4-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
|
|
// CHECK4-NEXT: br i1 [[TMP19]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
|
|
// CHECK4: .omp.final.then:
|
|
// CHECK4-NEXT: store i64 400, i64* [[IT]], align 8
|
|
// CHECK4-NEXT: br label [[DOTOMP_FINAL_DONE]]
|
|
// CHECK4: .omp.final.done:
|
|
// CHECK4-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK4-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0
|
|
// CHECK4-NEXT: br i1 [[TMP21]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
|
|
// CHECK4: .omp.linear.pu:
|
|
// CHECK4-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4
|
|
// CHECK4-NEXT: [[CONV16:%.*]] = sext i32 [[TMP22]] to i64
|
|
// CHECK4-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
|
|
// CHECK4-NEXT: [[MUL17:%.*]] = mul i64 4, [[TMP23]]
|
|
// CHECK4-NEXT: [[ADD18:%.*]] = add i64 [[CONV16]], [[MUL17]]
|
|
// CHECK4-NEXT: [[CONV19:%.*]] = trunc i64 [[ADD18]] to i32
|
|
// CHECK4-NEXT: store i32 [[CONV19]], i32* [[LIN_ADDR]], align 4
|
|
// CHECK4-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTLINEAR_START1]], align 4
|
|
// CHECK4-NEXT: [[CONV20:%.*]] = sext i32 [[TMP24]] to i64
|
|
// CHECK4-NEXT: [[TMP25:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
|
|
// CHECK4-NEXT: [[MUL21:%.*]] = mul i64 4, [[TMP25]]
|
|
// CHECK4-NEXT: [[ADD22:%.*]] = add i64 [[CONV20]], [[MUL21]]
|
|
// CHECK4-NEXT: [[CONV23:%.*]] = trunc i64 [[ADD22]] to i32
|
|
// CHECK4-NEXT: store i32 [[CONV23]], i32* [[A_ADDR]], align 4
|
|
// CHECK4-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]]
|
|
// CHECK4: .omp.linear.pu.done:
|
|
// CHECK4-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116
|
|
// CHECK4-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] {
|
|
// CHECK4-NEXT: entry:
|
|
// CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK4-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
|
|
// CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
|
|
// CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK4-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
|
|
// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
|
|
// CHECK4-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
|
|
// CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
|
|
// CHECK4-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
|
|
// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
|
|
// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]])
|
|
// CHECK4-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..4
|
|
// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR3]] {
|
|
// CHECK4-NEXT: entry:
|
|
// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[TMP:%.*]] = alloca i16, align 2
|
|
// CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[IT:%.*]] = alloca i16, align 2
|
|
// CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK4-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
|
|
// CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
|
|
// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK4-NEXT: store i32 3, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
|
|
// CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
|
|
// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3
|
|
// CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK4: cond.true:
|
|
// CHECK4-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK4: cond.false:
|
|
// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK4-NEXT: br label [[COND_END]]
|
|
// CHECK4: cond.end:
|
|
// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
|
|
// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK4-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK4: omp.inner.for.cond:
|
|
// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33
|
|
// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !33
|
|
// CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
|
|
// CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK4: omp.inner.for.body:
|
|
// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33
|
|
// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4
|
|
// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]]
|
|
// CHECK4-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
|
|
// CHECK4-NEXT: store i16 [[CONV2]], i16* [[IT]], align 2, !llvm.access.group !33
|
|
// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !33
|
|
// CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1
|
|
// CHECK4-NEXT: store i32 [[ADD3]], i32* [[A_ADDR]], align 4, !llvm.access.group !33
|
|
// CHECK4-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !33
|
|
// CHECK4-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32
|
|
// CHECK4-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
|
|
// CHECK4-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
|
|
// CHECK4-NEXT: store i16 [[CONV6]], i16* [[CONV]], align 4, !llvm.access.group !33
|
|
// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK4: omp.body.continue:
|
|
// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK4: omp.inner.for.inc:
|
|
// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33
|
|
// CHECK4-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1
|
|
// CHECK4-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33
|
|
// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP34:![0-9]+]]
|
|
// CHECK4: omp.inner.for.end:
|
|
// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK4: omp.loop.exit:
|
|
// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
|
|
// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK4-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
|
|
// CHECK4-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
|
|
// CHECK4: .omp.final.then:
|
|
// CHECK4-NEXT: store i16 22, i16* [[IT]], align 2
|
|
// CHECK4-NEXT: br label [[DOTOMP_FINAL_DONE]]
|
|
// CHECK4: .omp.final.done:
|
|
// CHECK4-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140
|
|
// CHECK4-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] {
|
|
// CHECK4-NEXT: entry:
|
|
// CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
|
|
// CHECK4-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4
|
|
// CHECK4-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
|
|
// CHECK4-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4
|
|
// CHECK4-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
|
|
// CHECK4-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK4-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
|
|
// CHECK4-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
|
|
// CHECK4-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4
|
|
// CHECK4-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
|
|
// CHECK4-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
|
|
// CHECK4-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
|
|
// CHECK4-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4
|
|
// CHECK4-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
|
|
// CHECK4-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK4-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
|
|
// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
|
|
// CHECK4-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
|
|
// CHECK4-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
|
|
// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
|
|
// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
|
|
// CHECK4-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
|
|
// CHECK4-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
|
|
// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK4-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4
|
|
// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4
|
|
// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK4-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
|
|
// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
|
|
// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*, i32)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i32 [[TMP11]])
|
|
// CHECK4-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..7
|
|
// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] {
|
|
// CHECK4-NEXT: entry:
|
|
// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
|
|
// CHECK4-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4
|
|
// CHECK4-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
|
|
// CHECK4-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4
|
|
// CHECK4-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
|
|
// CHECK4-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[TMP:%.*]] = alloca i8, align 1
|
|
// CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[IT:%.*]] = alloca i8, align 1
|
|
// CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK4-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
|
|
// CHECK4-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
|
|
// CHECK4-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4
|
|
// CHECK4-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
|
|
// CHECK4-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
|
|
// CHECK4-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
|
|
// CHECK4-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4
|
|
// CHECK4-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
|
|
// CHECK4-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK4-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
|
|
// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
|
|
// CHECK4-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
|
|
// CHECK4-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
|
|
// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
|
|
// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
|
|
// CHECK4-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
|
|
// CHECK4-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
|
|
// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK4-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK4-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
|
|
// CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
|
|
// CHECK4-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
|
|
// CHECK4: omp.dispatch.cond:
|
|
// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25
|
|
// CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK4: cond.true:
|
|
// CHECK4-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK4: cond.false:
|
|
// CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK4-NEXT: br label [[COND_END]]
|
|
// CHECK4: cond.end:
|
|
// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
|
|
// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK4-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK4-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK4-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK4-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
|
|
// CHECK4-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
|
|
// CHECK4: omp.dispatch.body:
|
|
// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK4: omp.inner.for.cond:
|
|
// CHECK4-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36
|
|
// CHECK4-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !36
|
|
// CHECK4-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
|
|
// CHECK4-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK4: omp.inner.for.body:
|
|
// CHECK4-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36
|
|
// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
|
|
// CHECK4-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]]
|
|
// CHECK4-NEXT: [[CONV:%.*]] = trunc i32 [[SUB]] to i8
|
|
// CHECK4-NEXT: store i8 [[CONV]], i8* [[IT]], align 1, !llvm.access.group !36
|
|
// CHECK4-NEXT: [[TMP19:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !36
|
|
// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1
|
|
// CHECK4-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4, !llvm.access.group !36
|
|
// CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2
|
|
// CHECK4-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !36
|
|
// CHECK4-NEXT: [[CONV7:%.*]] = fpext float [[TMP20]] to double
|
|
// CHECK4-NEXT: [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00
|
|
// CHECK4-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float
|
|
// CHECK4-NEXT: store float [[CONV9]], float* [[ARRAYIDX]], align 4, !llvm.access.group !36
|
|
// CHECK4-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3
|
|
// CHECK4-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX10]], align 4, !llvm.access.group !36
|
|
// CHECK4-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double
|
|
// CHECK4-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00
|
|
// CHECK4-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float
|
|
// CHECK4-NEXT: store float [[CONV13]], float* [[ARRAYIDX10]], align 4, !llvm.access.group !36
|
|
// CHECK4-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1
|
|
// CHECK4-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX14]], i32 0, i32 2
|
|
// CHECK4-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX15]], align 8, !llvm.access.group !36
|
|
// CHECK4-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00
|
|
// CHECK4-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8, !llvm.access.group !36
|
|
// CHECK4-NEXT: [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]]
|
|
// CHECK4-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP23]]
|
|
// CHECK4-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX17]], i32 3
|
|
// CHECK4-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX18]], align 8, !llvm.access.group !36
|
|
// CHECK4-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00
|
|
// CHECK4-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8, !llvm.access.group !36
|
|
// CHECK4-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0
|
|
// CHECK4-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 4, !llvm.access.group !36
|
|
// CHECK4-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1
|
|
// CHECK4-NEXT: store i64 [[ADD20]], i64* [[X]], align 4, !llvm.access.group !36
|
|
// CHECK4-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1
|
|
// CHECK4-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 4, !llvm.access.group !36
|
|
// CHECK4-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i32
|
|
// CHECK4-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1
|
|
// CHECK4-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8
|
|
// CHECK4-NEXT: store i8 [[CONV23]], i8* [[Y]], align 4, !llvm.access.group !36
|
|
// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK4: omp.body.continue:
|
|
// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK4: omp.inner.for.inc:
|
|
// CHECK4-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36
|
|
// CHECK4-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1
|
|
// CHECK4-NEXT: store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36
|
|
// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP37:![0-9]+]]
|
|
// CHECK4: omp.inner.for.end:
|
|
// CHECK4-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
|
|
// CHECK4: omp.dispatch.inc:
|
|
// CHECK4-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK4-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK4-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]
|
|
// CHECK4-NEXT: store i32 [[ADD25]], i32* [[DOTOMP_LB]], align 4
|
|
// CHECK4-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK4-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK4-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]]
|
|
// CHECK4-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK4-NEXT: br label [[OMP_DISPATCH_COND]]
|
|
// CHECK4: omp.dispatch.end:
|
|
// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]])
|
|
// CHECK4-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK4-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0
|
|
// CHECK4-NEXT: br i1 [[TMP33]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
|
|
// CHECK4: .omp.final.then:
|
|
// CHECK4-NEXT: store i8 96, i8* [[IT]], align 1
|
|
// CHECK4-NEXT: br label [[DOTOMP_FINAL_DONE]]
|
|
// CHECK4: .omp.final.done:
|
|
// CHECK4-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK4-LABEL: define {{[^@]+}}@_Z3bari
|
|
// CHECK4-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
|
|
// CHECK4-NEXT: entry:
|
|
// CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4
|
|
// CHECK4-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK4-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK4-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]])
|
|
// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
|
|
// CHECK4-NEXT: store i32 [[ADD]], i32* [[A]], align 4
|
|
// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK4-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]])
|
|
// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK4-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
|
|
// CHECK4-NEXT: store i32 [[ADD2]], i32* [[A]], align 4
|
|
// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK4-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]])
|
|
// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK4-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
|
|
// CHECK4-NEXT: store i32 [[ADD4]], i32* [[A]], align 4
|
|
// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK4-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]])
|
|
// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK4-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
|
|
// CHECK4-NEXT: store i32 [[ADD6]], i32* [[A]], align 4
|
|
// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK4-NEXT: ret i32 [[TMP8]]
|
|
//
|
|
//
|
|
// CHECK4-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
|
|
// CHECK4-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 {
|
|
// CHECK4-NEXT: entry:
|
|
// CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
|
|
// CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[B:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4
|
|
// CHECK4-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4
|
|
// CHECK4-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4
|
|
// CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4
|
|
// CHECK4-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 4
|
|
// CHECK4-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK4-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
|
|
// CHECK4-NEXT: store i32 [[ADD]], i32* [[B]], align 4
|
|
// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK4-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave()
|
|
// CHECK4-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4
|
|
// CHECK4-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]]
|
|
// CHECK4-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2
|
|
// CHECK4-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4
|
|
// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[B]], align 4
|
|
// CHECK4-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4
|
|
// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4
|
|
// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 60
|
|
// CHECK4-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
|
|
// CHECK4: omp_if.then:
|
|
// CHECK4-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
|
|
// CHECK4-NEXT: [[TMP7:%.*]] = mul nuw i32 2, [[TMP1]]
|
|
// CHECK4-NEXT: [[TMP8:%.*]] = mul nuw i32 [[TMP7]], 2
|
|
// CHECK4-NEXT: [[TMP9:%.*]] = sext i32 [[TMP8]] to i64
|
|
// CHECK4-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK4-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to %struct.S1**
|
|
// CHECK4-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP11]], align 4
|
|
// CHECK4-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK4-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to double**
|
|
// CHECK4-NEXT: store double* [[A]], double** [[TMP13]], align 4
|
|
// CHECK4-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
|
|
// CHECK4-NEXT: store i64 8, i64* [[TMP14]], align 4
|
|
// CHECK4-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
|
|
// CHECK4-NEXT: store i8* null, i8** [[TMP15]], align 4
|
|
// CHECK4-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
|
|
// CHECK4-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32*
|
|
// CHECK4-NEXT: store i32 [[TMP5]], i32* [[TMP17]], align 4
|
|
// CHECK4-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
|
|
// CHECK4-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32*
|
|
// CHECK4-NEXT: store i32 [[TMP5]], i32* [[TMP19]], align 4
|
|
// CHECK4-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1
|
|
// CHECK4-NEXT: store i64 4, i64* [[TMP20]], align 4
|
|
// CHECK4-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
|
|
// CHECK4-NEXT: store i8* null, i8** [[TMP21]], align 4
|
|
// CHECK4-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
|
|
// CHECK4-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i32*
|
|
// CHECK4-NEXT: store i32 2, i32* [[TMP23]], align 4
|
|
// CHECK4-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
|
|
// CHECK4-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i32*
|
|
// CHECK4-NEXT: store i32 2, i32* [[TMP25]], align 4
|
|
// CHECK4-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2
|
|
// CHECK4-NEXT: store i64 4, i64* [[TMP26]], align 4
|
|
// CHECK4-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
|
|
// CHECK4-NEXT: store i8* null, i8** [[TMP27]], align 4
|
|
// CHECK4-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
|
|
// CHECK4-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i32*
|
|
// CHECK4-NEXT: store i32 [[TMP1]], i32* [[TMP29]], align 4
|
|
// CHECK4-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
|
|
// CHECK4-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i32*
|
|
// CHECK4-NEXT: store i32 [[TMP1]], i32* [[TMP31]], align 4
|
|
// CHECK4-NEXT: [[TMP32:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3
|
|
// CHECK4-NEXT: store i64 4, i64* [[TMP32]], align 4
|
|
// CHECK4-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
|
|
// CHECK4-NEXT: store i8* null, i8** [[TMP33]], align 4
|
|
// CHECK4-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
|
|
// CHECK4-NEXT: [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i16**
|
|
// CHECK4-NEXT: store i16* [[VLA]], i16** [[TMP35]], align 4
|
|
// CHECK4-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
|
|
// CHECK4-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i16**
|
|
// CHECK4-NEXT: store i16* [[VLA]], i16** [[TMP37]], align 4
|
|
// CHECK4-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4
|
|
// CHECK4-NEXT: store i64 [[TMP9]], i64* [[TMP38]], align 4
|
|
// CHECK4-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4
|
|
// CHECK4-NEXT: store i8* null, i8** [[TMP39]], align 4
|
|
// CHECK4-NEXT: [[TMP40:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK4-NEXT: [[TMP41:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK4-NEXT: [[TMP42:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
|
|
// CHECK4-NEXT: [[TMP43:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216.region_id, i32 5, i8** [[TMP40]], i8** [[TMP41]], i64* [[TMP42]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
|
|
// CHECK4-NEXT: [[TMP44:%.*]] = icmp ne i32 [[TMP43]], 0
|
|
// CHECK4-NEXT: br i1 [[TMP44]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
|
// CHECK4: omp_offload.failed:
|
|
// CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR4]]
|
|
// CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
|
// CHECK4: omp_offload.cont:
|
|
// CHECK4-NEXT: br label [[OMP_IF_END:%.*]]
|
|
// CHECK4: omp_if.else:
|
|
// CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR4]]
|
|
// CHECK4-NEXT: br label [[OMP_IF_END]]
|
|
// CHECK4: omp_if.end:
|
|
// CHECK4-NEXT: [[TMP45:%.*]] = mul nsw i32 1, [[TMP1]]
|
|
// CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP45]]
|
|
// CHECK4-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
|
|
// CHECK4-NEXT: [[TMP46:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2
|
|
// CHECK4-NEXT: [[CONV:%.*]] = sext i16 [[TMP46]] to i32
|
|
// CHECK4-NEXT: [[TMP47:%.*]] = load i32, i32* [[B]], align 4
|
|
// CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP47]]
|
|
// CHECK4-NEXT: [[TMP48:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
|
|
// CHECK4-NEXT: call void @llvm.stackrestore(i8* [[TMP48]])
|
|
// CHECK4-NEXT: ret i32 [[ADD3]]
|
|
//
|
|
//
|
|
// CHECK4-LABEL: define {{[^@]+}}@_ZL7fstatici
|
|
// CHECK4-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
|
|
// CHECK4-NEXT: entry:
|
|
// CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[AA:%.*]] = alloca i16, align 2
|
|
// CHECK4-NEXT: [[AAA:%.*]] = alloca i8, align 1
|
|
// CHECK4-NEXT: [[B:%.*]] = alloca [10 x i32], align 4
|
|
// CHECK4-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4
|
|
// CHECK4-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4
|
|
// CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4
|
|
// CHECK4-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK4-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK4-NEXT: store i16 0, i16* [[AA]], align 2
|
|
// CHECK4-NEXT: store i8 0, i8* [[AAA]], align 1
|
|
// CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK4-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
|
|
// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
|
|
// CHECK4-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
|
|
// CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
|
|
// CHECK4-NEXT: store i16 [[TMP2]], i16* [[CONV]], align 2
|
|
// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
|
|
// CHECK4-NEXT: [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1
|
|
// CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
|
|
// CHECK4-NEXT: store i8 [[TMP4]], i8* [[CONV1]], align 1
|
|
// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
|
|
// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50
|
|
// CHECK4-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
|
|
// CHECK4: omp_if.then:
|
|
// CHECK4-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK4-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32*
|
|
// CHECK4-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4
|
|
// CHECK4-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK4-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32*
|
|
// CHECK4-NEXT: store i32 [[TMP1]], i32* [[TMP10]], align 4
|
|
// CHECK4-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
|
|
// CHECK4-NEXT: store i8* null, i8** [[TMP11]], align 4
|
|
// CHECK4-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
|
|
// CHECK4-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32*
|
|
// CHECK4-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4
|
|
// CHECK4-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
|
|
// CHECK4-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32*
|
|
// CHECK4-NEXT: store i32 [[TMP3]], i32* [[TMP15]], align 4
|
|
// CHECK4-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
|
|
// CHECK4-NEXT: store i8* null, i8** [[TMP16]], align 4
|
|
// CHECK4-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
|
|
// CHECK4-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32*
|
|
// CHECK4-NEXT: store i32 [[TMP5]], i32* [[TMP18]], align 4
|
|
// CHECK4-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
|
|
// CHECK4-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32*
|
|
// CHECK4-NEXT: store i32 [[TMP5]], i32* [[TMP20]], align 4
|
|
// CHECK4-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
|
|
// CHECK4-NEXT: store i8* null, i8** [[TMP21]], align 4
|
|
// CHECK4-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
|
|
// CHECK4-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]**
|
|
// CHECK4-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 4
|
|
// CHECK4-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
|
|
// CHECK4-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]**
|
|
// CHECK4-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 4
|
|
// CHECK4-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
|
|
// CHECK4-NEXT: store i8* null, i8** [[TMP26]], align 4
|
|
// CHECK4-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK4-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK4-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
|
|
// CHECK4-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0
|
|
// CHECK4-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
|
// CHECK4: omp_offload.failed:
|
|
// CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]]
|
|
// CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
|
// CHECK4: omp_offload.cont:
|
|
// CHECK4-NEXT: br label [[OMP_IF_END:%.*]]
|
|
// CHECK4: omp_if.else:
|
|
// CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]]
|
|
// CHECK4-NEXT: br label [[OMP_IF_END]]
|
|
// CHECK4: omp_if.end:
|
|
// CHECK4-NEXT: [[TMP31:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK4-NEXT: ret i32 [[TMP31]]
|
|
//
|
|
//
|
|
// CHECK4-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
|
|
// CHECK4-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat {
|
|
// CHECK4-NEXT: entry:
|
|
// CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[AA:%.*]] = alloca i16, align 2
|
|
// CHECK4-NEXT: [[B:%.*]] = alloca [10 x i32], align 4
|
|
// CHECK4-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4
|
|
// CHECK4-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4
|
|
// CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4
|
|
// CHECK4-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK4-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK4-NEXT: store i16 0, i16* [[AA]], align 2
|
|
// CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK4-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
|
|
// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
|
|
// CHECK4-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
|
|
// CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
|
|
// CHECK4-NEXT: store i16 [[TMP2]], i16* [[CONV]], align 2
|
|
// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
|
|
// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40
|
|
// CHECK4-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
|
|
// CHECK4: omp_if.then:
|
|
// CHECK4-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK4-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i32*
|
|
// CHECK4-NEXT: store i32 [[TMP1]], i32* [[TMP6]], align 4
|
|
// CHECK4-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK4-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32*
|
|
// CHECK4-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4
|
|
// CHECK4-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
|
|
// CHECK4-NEXT: store i8* null, i8** [[TMP9]], align 4
|
|
// CHECK4-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
|
|
// CHECK4-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i32*
|
|
// CHECK4-NEXT: store i32 [[TMP3]], i32* [[TMP11]], align 4
|
|
// CHECK4-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
|
|
// CHECK4-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32*
|
|
// CHECK4-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4
|
|
// CHECK4-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
|
|
// CHECK4-NEXT: store i8* null, i8** [[TMP14]], align 4
|
|
// CHECK4-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
|
|
// CHECK4-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]**
|
|
// CHECK4-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 4
|
|
// CHECK4-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
|
|
// CHECK4-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]**
|
|
// CHECK4-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 4
|
|
// CHECK4-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
|
|
// CHECK4-NEXT: store i8* null, i8** [[TMP19]], align 4
|
|
// CHECK4-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK4-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK4-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.15, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.16, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
|
|
// CHECK4-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0
|
|
// CHECK4-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
|
// CHECK4: omp_offload.failed:
|
|
// CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]]
|
|
// CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
|
// CHECK4: omp_offload.cont:
|
|
// CHECK4-NEXT: br label [[OMP_IF_END:%.*]]
|
|
// CHECK4: omp_if.else:
|
|
// CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]]
|
|
// CHECK4-NEXT: br label [[OMP_IF_END]]
|
|
// CHECK4: omp_if.end:
|
|
// CHECK4-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK4-NEXT: ret i32 [[TMP24]]
|
|
//
|
|
//
|
|
// CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216
|
|
// CHECK4-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {
|
|
// CHECK4-NEXT: entry:
|
|
// CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
|
|
// CHECK4-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4
|
|
// CHECK4-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK4-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
|
|
// CHECK4-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
|
|
// CHECK4-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
|
|
// CHECK4-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4
|
|
// CHECK4-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
|
|
// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
|
|
// CHECK4-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
|
|
// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4
|
|
// CHECK4-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4
|
|
// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4
|
|
// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]])
|
|
// CHECK4-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..9
|
|
// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR3]] {
|
|
// CHECK4-NEXT: entry:
|
|
// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
|
|
// CHECK4-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4
|
|
// CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
|
|
// CHECK4-NEXT: [[TMP:%.*]] = alloca i64, align 4
|
|
// CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
|
|
// CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
|
|
// CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
|
|
// CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[IT:%.*]] = alloca i64, align 8
|
|
// CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK4-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK4-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
|
|
// CHECK4-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
|
|
// CHECK4-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
|
|
// CHECK4-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4
|
|
// CHECK4-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
|
|
// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
|
|
// CHECK4-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
|
|
// CHECK4-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK4-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK4-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
|
|
// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK4-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
|
|
// CHECK4-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
|
|
// CHECK4-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK4-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 3
|
|
// CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK4: cond.true:
|
|
// CHECK4-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK4: cond.false:
|
|
// CHECK4-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK4-NEXT: br label [[COND_END]]
|
|
// CHECK4: cond.end:
|
|
// CHECK4-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
|
|
// CHECK4-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
|
|
// CHECK4-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK4-NEXT: store i64 [[TMP8]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK4: omp.inner.for.cond:
|
|
// CHECK4-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !39
|
|
// CHECK4-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !39
|
|
// CHECK4-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]]
|
|
// CHECK4-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK4: omp.inner.for.body:
|
|
// CHECK4-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !39
|
|
// CHECK4-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400
|
|
// CHECK4-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]
|
|
// CHECK4-NEXT: store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !39
|
|
// CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[B_ADDR]], align 4, !llvm.access.group !39
|
|
// CHECK4-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP12]] to double
|
|
// CHECK4-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00
|
|
// CHECK4-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
|
|
// CHECK4-NEXT: store double [[ADD]], double* [[A]], align 4, !llvm.access.group !39
|
|
// CHECK4-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
|
|
// CHECK4-NEXT: [[TMP13:%.*]] = load double, double* [[A4]], align 4, !llvm.access.group !39
|
|
// CHECK4-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00
|
|
// CHECK4-NEXT: store double [[INC]], double* [[A4]], align 4, !llvm.access.group !39
|
|
// CHECK4-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16
|
|
// CHECK4-NEXT: [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]]
|
|
// CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP14]]
|
|
// CHECK4-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
|
|
// CHECK4-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2, !llvm.access.group !39
|
|
// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK4: omp.body.continue:
|
|
// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK4: omp.inner.for.inc:
|
|
// CHECK4-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !39
|
|
// CHECK4-NEXT: [[ADD7:%.*]] = add i64 [[TMP15]], 1
|
|
// CHECK4-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !39
|
|
// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP40:![0-9]+]]
|
|
// CHECK4: omp.inner.for.end:
|
|
// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK4: omp.loop.exit:
|
|
// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
|
|
// CHECK4-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK4-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0
|
|
// CHECK4-NEXT: br i1 [[TMP17]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
|
|
// CHECK4: .omp.final.then:
|
|
// CHECK4-NEXT: store i64 400, i64* [[IT]], align 8
|
|
// CHECK4-NEXT: br label [[DOTOMP_FINAL_DONE]]
|
|
// CHECK4: .omp.final.done:
|
|
// CHECK4-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195
|
|
// CHECK4-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
|
|
// CHECK4-NEXT: entry:
|
|
// CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
|
|
// CHECK4-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK4-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
|
|
// CHECK4-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
|
|
// CHECK4-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
|
|
// CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
|
|
// CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
|
|
// CHECK4-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
|
|
// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK4-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
|
|
// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
|
|
// CHECK4-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
|
|
// CHECK4-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
|
|
// CHECK4-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2
|
|
// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
|
|
// CHECK4-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 4
|
|
// CHECK4-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
|
|
// CHECK4-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1
|
|
// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
|
|
// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]])
|
|
// CHECK4-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..11
|
|
// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] {
|
|
// CHECK4-NEXT: entry:
|
|
// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
|
|
// CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK4-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
|
|
// CHECK4-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
|
|
// CHECK4-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
|
|
// CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
|
|
// CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
|
|
// CHECK4-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
|
|
// CHECK4-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178
|
|
// CHECK4-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
|
|
// CHECK4-NEXT: entry:
|
|
// CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
|
|
// CHECK4-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK4-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
|
|
// CHECK4-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
|
|
// CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
|
|
// CHECK4-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
|
|
// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK4-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
|
|
// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
|
|
// CHECK4-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
|
|
// CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
|
|
// CHECK4-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2
|
|
// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
|
|
// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]])
|
|
// CHECK4-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..14
|
|
// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] {
|
|
// CHECK4-NEXT: entry:
|
|
// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
|
|
// CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
|
|
// CHECK4-NEXT: [[TMP:%.*]] = alloca i64, align 4
|
|
// CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
|
|
// CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
|
|
// CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
|
|
// CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[I:%.*]] = alloca i64, align 8
|
|
// CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK4-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
|
|
// CHECK4-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
|
|
// CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
|
|
// CHECK4-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
|
|
// CHECK4-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK4-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK4-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
|
|
// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK4-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
|
|
// CHECK4-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
|
|
// CHECK4-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6
|
|
// CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK4: cond.true:
|
|
// CHECK4-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK4: cond.false:
|
|
// CHECK4-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK4-NEXT: br label [[COND_END]]
|
|
// CHECK4: cond.end:
|
|
// CHECK4-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
|
|
// CHECK4-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
|
|
// CHECK4-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK4-NEXT: store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK4: omp.inner.for.cond:
|
|
// CHECK4-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !42
|
|
// CHECK4-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !42
|
|
// CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]]
|
|
// CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK4: omp.inner.for.body:
|
|
// CHECK4-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !42
|
|
// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3
|
|
// CHECK4-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
|
|
// CHECK4-NEXT: store i64 [[ADD]], i64* [[I]], align 8, !llvm.access.group !42
|
|
// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !42
|
|
// CHECK4-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
|
|
// CHECK4-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4, !llvm.access.group !42
|
|
// CHECK4-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !42
|
|
// CHECK4-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32
|
|
// CHECK4-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
|
|
// CHECK4-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
|
|
// CHECK4-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 4, !llvm.access.group !42
|
|
// CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
|
|
// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !42
|
|
// CHECK4-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1
|
|
// CHECK4-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !42
|
|
// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK4: omp.body.continue:
|
|
// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK4: omp.inner.for.inc:
|
|
// CHECK4-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !42
|
|
// CHECK4-NEXT: [[ADD7:%.*]] = add nsw i64 [[TMP12]], 1
|
|
// CHECK4-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !42
|
|
// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP43:![0-9]+]]
|
|
// CHECK4: omp.inner.for.end:
|
|
// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK4: omp.loop.exit:
|
|
// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
|
|
// CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK4-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
|
|
// CHECK4-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
|
|
// CHECK4: .omp.final.then:
|
|
// CHECK4-NEXT: store i64 11, i64* [[I]], align 8
|
|
// CHECK4-NEXT: br label [[DOTOMP_FINAL_DONE]]
|
|
// CHECK4: .omp.final.done:
|
|
// CHECK4-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK4-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
|
|
// CHECK4-SAME: () #[[ATTR7:[0-9]+]] {
|
|
// CHECK4-NEXT: entry:
|
|
// CHECK4-NEXT: call void @__tgt_register_requires(i64 1)
|
|
// CHECK4-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK5-LABEL: define {{[^@]+}}@_Z7get_valv
|
|
// CHECK5-SAME: () #[[ATTR0:[0-9]+]] {
|
|
// CHECK5-NEXT: entry:
|
|
// CHECK5-NEXT: ret i64 0
|
|
//
|
|
//
|
|
// CHECK5-LABEL: define {{[^@]+}}@_Z3fooi
|
|
// CHECK5-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
|
|
// CHECK5-NEXT: entry:
|
|
// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK5-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK5-NEXT: [[AA:%.*]] = alloca i16, align 2
|
|
// CHECK5-NEXT: [[B:%.*]] = alloca [10 x float], align 4
|
|
// CHECK5-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8
|
|
// CHECK5-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8
|
|
// CHECK5-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8
|
|
// CHECK5-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8
|
|
// CHECK5-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8
|
|
// CHECK5-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 1
|
|
// CHECK5-NEXT: [[K:%.*]] = alloca i64, align 8
|
|
// CHECK5-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK5-NEXT: [[K_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK5-NEXT: [[LIN:%.*]] = alloca i32, align 4
|
|
// CHECK5-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK5-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK5-NEXT: [[A_CASTED4:%.*]] = alloca i64, align 8
|
|
// CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8
|
|
// CHECK5-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8
|
|
// CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8
|
|
// CHECK5-NEXT: [[A_CASTED6:%.*]] = alloca i64, align 8
|
|
// CHECK5-NEXT: [[AA_CASTED8:%.*]] = alloca i64, align 8
|
|
// CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS10:%.*]] = alloca [2 x i8*], align 8
|
|
// CHECK5-NEXT: [[DOTOFFLOAD_PTRS11:%.*]] = alloca [2 x i8*], align 8
|
|
// CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS12:%.*]] = alloca [2 x i8*], align 8
|
|
// CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
|
// CHECK5-NEXT: [[A_CASTED15:%.*]] = alloca i64, align 8
|
|
// CHECK5-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS20:%.*]] = alloca [10 x i8*], align 8
|
|
// CHECK5-NEXT: [[DOTOFFLOAD_PTRS21:%.*]] = alloca [10 x i8*], align 8
|
|
// CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS22:%.*]] = alloca [10 x i8*], align 8
|
|
// CHECK5-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 8
|
|
// CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]])
|
|
// CHECK5-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK5-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK5-NEXT: store i16 0, i16* [[AA]], align 2
|
|
// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK5-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
|
|
// CHECK5-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave()
|
|
// CHECK5-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8
|
|
// CHECK5-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP2]], align 4
|
|
// CHECK5-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8
|
|
// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK5-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64
|
|
// CHECK5-NEXT: [[TMP6:%.*]] = mul nuw i64 5, [[TMP5]]
|
|
// CHECK5-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP6]], align 8
|
|
// CHECK5-NEXT: store i64 [[TMP5]], i64* [[__VLA_EXPR1]], align 8
|
|
// CHECK5-NEXT: [[TMP7:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 1, i64 40, i64 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1)
|
|
// CHECK5-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.kmp_task_t_with_privates*
|
|
// CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP8]], i32 0, i32 0
|
|
// CHECK5-NEXT: [[TMP10:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i8* [[TMP7]])
|
|
// CHECK5-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv()
|
|
// CHECK5-NEXT: store i64 [[CALL]], i64* [[K]], align 8
|
|
// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32*
|
|
// CHECK5-NEXT: store i32 [[TMP11]], i32* [[CONV]], align 4
|
|
// CHECK5-NEXT: [[TMP12:%.*]] = load i64, i64* [[A_CASTED]], align 8
|
|
// CHECK5-NEXT: [[TMP13:%.*]] = load i64, i64* [[K]], align 8
|
|
// CHECK5-NEXT: store i64 [[TMP13]], i64* [[K_CASTED]], align 8
|
|
// CHECK5-NEXT: [[TMP14:%.*]] = load i64, i64* [[K_CASTED]], align 8
|
|
// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101(i64 [[TMP12]], i64 [[TMP14]]) #[[ATTR4:[0-9]+]]
|
|
// CHECK5-NEXT: store i32 12, i32* [[LIN]], align 4
|
|
// CHECK5-NEXT: [[TMP15:%.*]] = load i16, i16* [[AA]], align 2
|
|
// CHECK5-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
|
|
// CHECK5-NEXT: store i16 [[TMP15]], i16* [[CONV2]], align 2
|
|
// CHECK5-NEXT: [[TMP16:%.*]] = load i64, i64* [[AA_CASTED]], align 8
|
|
// CHECK5-NEXT: [[TMP17:%.*]] = load i32, i32* [[LIN]], align 4
|
|
// CHECK5-NEXT: [[CONV3:%.*]] = bitcast i64* [[LIN_CASTED]] to i32*
|
|
// CHECK5-NEXT: store i32 [[TMP17]], i32* [[CONV3]], align 4
|
|
// CHECK5-NEXT: [[TMP18:%.*]] = load i64, i64* [[LIN_CASTED]], align 8
|
|
// CHECK5-NEXT: [[TMP19:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK5-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED4]] to i32*
|
|
// CHECK5-NEXT: store i32 [[TMP19]], i32* [[CONV5]], align 4
|
|
// CHECK5-NEXT: [[TMP20:%.*]] = load i64, i64* [[A_CASTED4]], align 8
|
|
// CHECK5-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK5-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i64*
|
|
// CHECK5-NEXT: store i64 [[TMP16]], i64* [[TMP22]], align 8
|
|
// CHECK5-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK5-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i64*
|
|
// CHECK5-NEXT: store i64 [[TMP16]], i64* [[TMP24]], align 8
|
|
// CHECK5-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
|
|
// CHECK5-NEXT: store i8* null, i8** [[TMP25]], align 8
|
|
// CHECK5-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
|
|
// CHECK5-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64*
|
|
// CHECK5-NEXT: store i64 [[TMP18]], i64* [[TMP27]], align 8
|
|
// CHECK5-NEXT: [[TMP28:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
|
|
// CHECK5-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i64*
|
|
// CHECK5-NEXT: store i64 [[TMP18]], i64* [[TMP29]], align 8
|
|
// CHECK5-NEXT: [[TMP30:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
|
|
// CHECK5-NEXT: store i8* null, i8** [[TMP30]], align 8
|
|
// CHECK5-NEXT: [[TMP31:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
|
|
// CHECK5-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i64*
|
|
// CHECK5-NEXT: store i64 [[TMP20]], i64* [[TMP32]], align 8
|
|
// CHECK5-NEXT: [[TMP33:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
|
|
// CHECK5-NEXT: [[TMP34:%.*]] = bitcast i8** [[TMP33]] to i64*
|
|
// CHECK5-NEXT: store i64 [[TMP20]], i64* [[TMP34]], align 8
|
|
// CHECK5-NEXT: [[TMP35:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
|
|
// CHECK5-NEXT: store i8* null, i8** [[TMP35]], align 8
|
|
// CHECK5-NEXT: [[TMP36:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK5-NEXT: [[TMP37:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK5-NEXT: [[TMP38:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108.region_id, i32 3, i8** [[TMP36]], i8** [[TMP37]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
|
|
// CHECK5-NEXT: [[TMP39:%.*]] = icmp ne i32 [[TMP38]], 0
|
|
// CHECK5-NEXT: br i1 [[TMP39]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
|
// CHECK5: omp_offload.failed:
|
|
// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108(i64 [[TMP16]], i64 [[TMP18]], i64 [[TMP20]]) #[[ATTR4]]
|
|
// CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
|
// CHECK5: omp_offload.cont:
|
|
// CHECK5-NEXT: [[TMP40:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK5-NEXT: [[CONV7:%.*]] = bitcast i64* [[A_CASTED6]] to i32*
|
|
// CHECK5-NEXT: store i32 [[TMP40]], i32* [[CONV7]], align 4
|
|
// CHECK5-NEXT: [[TMP41:%.*]] = load i64, i64* [[A_CASTED6]], align 8
|
|
// CHECK5-NEXT: [[TMP42:%.*]] = load i16, i16* [[AA]], align 2
|
|
// CHECK5-NEXT: [[CONV9:%.*]] = bitcast i64* [[AA_CASTED8]] to i16*
|
|
// CHECK5-NEXT: store i16 [[TMP42]], i16* [[CONV9]], align 2
|
|
// CHECK5-NEXT: [[TMP43:%.*]] = load i64, i64* [[AA_CASTED8]], align 8
|
|
// CHECK5-NEXT: [[TMP44:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP44]], 10
|
|
// CHECK5-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
|
|
// CHECK5: omp_if.then:
|
|
// CHECK5-NEXT: [[TMP45:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 0
|
|
// CHECK5-NEXT: [[TMP46:%.*]] = bitcast i8** [[TMP45]] to i64*
|
|
// CHECK5-NEXT: store i64 [[TMP41]], i64* [[TMP46]], align 8
|
|
// CHECK5-NEXT: [[TMP47:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS11]], i32 0, i32 0
|
|
// CHECK5-NEXT: [[TMP48:%.*]] = bitcast i8** [[TMP47]] to i64*
|
|
// CHECK5-NEXT: store i64 [[TMP41]], i64* [[TMP48]], align 8
|
|
// CHECK5-NEXT: [[TMP49:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS12]], i64 0, i64 0
|
|
// CHECK5-NEXT: store i8* null, i8** [[TMP49]], align 8
|
|
// CHECK5-NEXT: [[TMP50:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 1
|
|
// CHECK5-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP50]] to i64*
|
|
// CHECK5-NEXT: store i64 [[TMP43]], i64* [[TMP51]], align 8
|
|
// CHECK5-NEXT: [[TMP52:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS11]], i32 0, i32 1
|
|
// CHECK5-NEXT: [[TMP53:%.*]] = bitcast i8** [[TMP52]] to i64*
|
|
// CHECK5-NEXT: store i64 [[TMP43]], i64* [[TMP53]], align 8
|
|
// CHECK5-NEXT: [[TMP54:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS12]], i64 0, i64 1
|
|
// CHECK5-NEXT: store i8* null, i8** [[TMP54]], align 8
|
|
// CHECK5-NEXT: [[TMP55:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 0
|
|
// CHECK5-NEXT: [[TMP56:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS11]], i32 0, i32 0
|
|
// CHECK5-NEXT: [[TMP57:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116.region_id, i32 2, i8** [[TMP55]], i8** [[TMP56]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
|
|
// CHECK5-NEXT: [[TMP58:%.*]] = icmp ne i32 [[TMP57]], 0
|
|
// CHECK5-NEXT: br i1 [[TMP58]], label [[OMP_OFFLOAD_FAILED13:%.*]], label [[OMP_OFFLOAD_CONT14:%.*]]
|
|
// CHECK5: omp_offload.failed13:
|
|
// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116(i64 [[TMP41]], i64 [[TMP43]]) #[[ATTR4]]
|
|
// CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT14]]
|
|
// CHECK5: omp_offload.cont14:
|
|
// CHECK5-NEXT: br label [[OMP_IF_END:%.*]]
|
|
// CHECK5: omp_if.else:
|
|
// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116(i64 [[TMP41]], i64 [[TMP43]]) #[[ATTR4]]
|
|
// CHECK5-NEXT: br label [[OMP_IF_END]]
|
|
// CHECK5: omp_if.end:
|
|
// CHECK5-NEXT: [[TMP59:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK5-NEXT: store i32 [[TMP59]], i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK5-NEXT: [[TMP60:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK5-NEXT: [[CONV16:%.*]] = bitcast i64* [[A_CASTED15]] to i32*
|
|
// CHECK5-NEXT: store i32 [[TMP60]], i32* [[CONV16]], align 4
|
|
// CHECK5-NEXT: [[TMP61:%.*]] = load i64, i64* [[A_CASTED15]], align 8
|
|
// CHECK5-NEXT: [[TMP62:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK5-NEXT: [[CONV17:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
|
|
// CHECK5-NEXT: store i32 [[TMP62]], i32* [[CONV17]], align 4
|
|
// CHECK5-NEXT: [[TMP63:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
|
|
// CHECK5-NEXT: [[TMP64:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK5-NEXT: [[CMP18:%.*]] = icmp sgt i32 [[TMP64]], 20
|
|
// CHECK5-NEXT: br i1 [[CMP18]], label [[OMP_IF_THEN19:%.*]], label [[OMP_IF_ELSE25:%.*]]
|
|
// CHECK5: omp_if.then19:
|
|
// CHECK5-NEXT: [[TMP65:%.*]] = mul nuw i64 [[TMP2]], 4
|
|
// CHECK5-NEXT: [[TMP66:%.*]] = mul nuw i64 5, [[TMP5]]
|
|
// CHECK5-NEXT: [[TMP67:%.*]] = mul nuw i64 [[TMP66]], 8
|
|
// CHECK5-NEXT: [[TMP68:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0
|
|
// CHECK5-NEXT: [[TMP69:%.*]] = bitcast i8** [[TMP68]] to i64*
|
|
// CHECK5-NEXT: store i64 [[TMP61]], i64* [[TMP69]], align 8
|
|
// CHECK5-NEXT: [[TMP70:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 0
|
|
// CHECK5-NEXT: [[TMP71:%.*]] = bitcast i8** [[TMP70]] to i64*
|
|
// CHECK5-NEXT: store i64 [[TMP61]], i64* [[TMP71]], align 8
|
|
// CHECK5-NEXT: [[TMP72:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
|
|
// CHECK5-NEXT: store i64 4, i64* [[TMP72]], align 8
|
|
// CHECK5-NEXT: [[TMP73:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 0
|
|
// CHECK5-NEXT: store i8* null, i8** [[TMP73]], align 8
|
|
// CHECK5-NEXT: [[TMP74:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 1
|
|
// CHECK5-NEXT: [[TMP75:%.*]] = bitcast i8** [[TMP74]] to [10 x float]**
|
|
// CHECK5-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP75]], align 8
|
|
// CHECK5-NEXT: [[TMP76:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 1
|
|
// CHECK5-NEXT: [[TMP77:%.*]] = bitcast i8** [[TMP76]] to [10 x float]**
|
|
// CHECK5-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP77]], align 8
|
|
// CHECK5-NEXT: [[TMP78:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1
|
|
// CHECK5-NEXT: store i64 40, i64* [[TMP78]], align 8
|
|
// CHECK5-NEXT: [[TMP79:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 1
|
|
// CHECK5-NEXT: store i8* null, i8** [[TMP79]], align 8
|
|
// CHECK5-NEXT: [[TMP80:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 2
|
|
// CHECK5-NEXT: [[TMP81:%.*]] = bitcast i8** [[TMP80]] to i64*
|
|
// CHECK5-NEXT: store i64 [[TMP2]], i64* [[TMP81]], align 8
|
|
// CHECK5-NEXT: [[TMP82:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 2
|
|
// CHECK5-NEXT: [[TMP83:%.*]] = bitcast i8** [[TMP82]] to i64*
|
|
// CHECK5-NEXT: store i64 [[TMP2]], i64* [[TMP83]], align 8
|
|
// CHECK5-NEXT: [[TMP84:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2
|
|
// CHECK5-NEXT: store i64 8, i64* [[TMP84]], align 8
|
|
// CHECK5-NEXT: [[TMP85:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 2
|
|
// CHECK5-NEXT: store i8* null, i8** [[TMP85]], align 8
|
|
// CHECK5-NEXT: [[TMP86:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 3
|
|
// CHECK5-NEXT: [[TMP87:%.*]] = bitcast i8** [[TMP86]] to float**
|
|
// CHECK5-NEXT: store float* [[VLA]], float** [[TMP87]], align 8
|
|
// CHECK5-NEXT: [[TMP88:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 3
|
|
// CHECK5-NEXT: [[TMP89:%.*]] = bitcast i8** [[TMP88]] to float**
|
|
// CHECK5-NEXT: store float* [[VLA]], float** [[TMP89]], align 8
|
|
// CHECK5-NEXT: [[TMP90:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3
|
|
// CHECK5-NEXT: store i64 [[TMP65]], i64* [[TMP90]], align 8
|
|
// CHECK5-NEXT: [[TMP91:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 3
|
|
// CHECK5-NEXT: store i8* null, i8** [[TMP91]], align 8
|
|
// CHECK5-NEXT: [[TMP92:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 4
|
|
// CHECK5-NEXT: [[TMP93:%.*]] = bitcast i8** [[TMP92]] to [5 x [10 x double]]**
|
|
// CHECK5-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP93]], align 8
|
|
// CHECK5-NEXT: [[TMP94:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 4
|
|
// CHECK5-NEXT: [[TMP95:%.*]] = bitcast i8** [[TMP94]] to [5 x [10 x double]]**
|
|
// CHECK5-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP95]], align 8
|
|
// CHECK5-NEXT: [[TMP96:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4
|
|
// CHECK5-NEXT: store i64 400, i64* [[TMP96]], align 8
|
|
// CHECK5-NEXT: [[TMP97:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 4
|
|
// CHECK5-NEXT: store i8* null, i8** [[TMP97]], align 8
|
|
// CHECK5-NEXT: [[TMP98:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 5
|
|
// CHECK5-NEXT: [[TMP99:%.*]] = bitcast i8** [[TMP98]] to i64*
|
|
// CHECK5-NEXT: store i64 5, i64* [[TMP99]], align 8
|
|
// CHECK5-NEXT: [[TMP100:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 5
|
|
// CHECK5-NEXT: [[TMP101:%.*]] = bitcast i8** [[TMP100]] to i64*
|
|
// CHECK5-NEXT: store i64 5, i64* [[TMP101]], align 8
|
|
// CHECK5-NEXT: [[TMP102:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 5
|
|
// CHECK5-NEXT: store i64 8, i64* [[TMP102]], align 8
|
|
// CHECK5-NEXT: [[TMP103:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 5
|
|
// CHECK5-NEXT: store i8* null, i8** [[TMP103]], align 8
|
|
// CHECK5-NEXT: [[TMP104:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 6
|
|
// CHECK5-NEXT: [[TMP105:%.*]] = bitcast i8** [[TMP104]] to i64*
|
|
// CHECK5-NEXT: store i64 [[TMP5]], i64* [[TMP105]], align 8
|
|
// CHECK5-NEXT: [[TMP106:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 6
|
|
// CHECK5-NEXT: [[TMP107:%.*]] = bitcast i8** [[TMP106]] to i64*
|
|
// CHECK5-NEXT: store i64 [[TMP5]], i64* [[TMP107]], align 8
|
|
// CHECK5-NEXT: [[TMP108:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 6
|
|
// CHECK5-NEXT: store i64 8, i64* [[TMP108]], align 8
|
|
// CHECK5-NEXT: [[TMP109:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 6
|
|
// CHECK5-NEXT: store i8* null, i8** [[TMP109]], align 8
|
|
// CHECK5-NEXT: [[TMP110:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 7
|
|
// CHECK5-NEXT: [[TMP111:%.*]] = bitcast i8** [[TMP110]] to double**
|
|
// CHECK5-NEXT: store double* [[VLA1]], double** [[TMP111]], align 8
|
|
// CHECK5-NEXT: [[TMP112:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 7
|
|
// CHECK5-NEXT: [[TMP113:%.*]] = bitcast i8** [[TMP112]] to double**
|
|
// CHECK5-NEXT: store double* [[VLA1]], double** [[TMP113]], align 8
|
|
// CHECK5-NEXT: [[TMP114:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7
|
|
// CHECK5-NEXT: store i64 [[TMP67]], i64* [[TMP114]], align 8
|
|
// CHECK5-NEXT: [[TMP115:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 7
|
|
// CHECK5-NEXT: store i8* null, i8** [[TMP115]], align 8
|
|
// CHECK5-NEXT: [[TMP116:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 8
|
|
// CHECK5-NEXT: [[TMP117:%.*]] = bitcast i8** [[TMP116]] to %struct.TT**
|
|
// CHECK5-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP117]], align 8
|
|
// CHECK5-NEXT: [[TMP118:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 8
|
|
// CHECK5-NEXT: [[TMP119:%.*]] = bitcast i8** [[TMP118]] to %struct.TT**
|
|
// CHECK5-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP119]], align 8
|
|
// CHECK5-NEXT: [[TMP120:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 8
|
|
// CHECK5-NEXT: store i64 16, i64* [[TMP120]], align 8
|
|
// CHECK5-NEXT: [[TMP121:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 8
|
|
// CHECK5-NEXT: store i8* null, i8** [[TMP121]], align 8
|
|
// CHECK5-NEXT: [[TMP122:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 9
|
|
// CHECK5-NEXT: [[TMP123:%.*]] = bitcast i8** [[TMP122]] to i64*
|
|
// CHECK5-NEXT: store i64 [[TMP63]], i64* [[TMP123]], align 8
|
|
// CHECK5-NEXT: [[TMP124:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 9
|
|
// CHECK5-NEXT: [[TMP125:%.*]] = bitcast i8** [[TMP124]] to i64*
|
|
// CHECK5-NEXT: store i64 [[TMP63]], i64* [[TMP125]], align 8
|
|
// CHECK5-NEXT: [[TMP126:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 9
|
|
// CHECK5-NEXT: store i64 4, i64* [[TMP126]], align 8
|
|
// CHECK5-NEXT: [[TMP127:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 9
|
|
// CHECK5-NEXT: store i8* null, i8** [[TMP127]], align 8
|
|
// CHECK5-NEXT: [[TMP128:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0
|
|
// CHECK5-NEXT: [[TMP129:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 0
|
|
// CHECK5-NEXT: [[TMP130:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
|
|
// CHECK5-NEXT: [[TMP131:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140.region_id, i32 10, i8** [[TMP128]], i8** [[TMP129]], i64* [[TMP130]], i64* getelementptr inbounds ([10 x i64], [10 x i64]* @.offload_maptypes.8, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
|
|
// CHECK5-NEXT: [[TMP132:%.*]] = icmp ne i32 [[TMP131]], 0
|
|
// CHECK5-NEXT: br i1 [[TMP132]], label [[OMP_OFFLOAD_FAILED23:%.*]], label [[OMP_OFFLOAD_CONT24:%.*]]
|
|
// CHECK5: omp_offload.failed23:
|
|
// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140(i64 [[TMP61]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]], i64 [[TMP63]]) #[[ATTR4]]
|
|
// CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT24]]
|
|
// CHECK5: omp_offload.cont24:
|
|
// CHECK5-NEXT: br label [[OMP_IF_END26:%.*]]
|
|
// CHECK5: omp_if.else25:
|
|
// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140(i64 [[TMP61]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]], i64 [[TMP63]]) #[[ATTR4]]
|
|
// CHECK5-NEXT: br label [[OMP_IF_END26]]
|
|
// CHECK5: omp_if.end26:
|
|
// CHECK5-NEXT: [[TMP133:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK5-NEXT: [[TMP134:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
|
|
// CHECK5-NEXT: call void @llvm.stackrestore(i8* [[TMP134]])
|
|
// CHECK5-NEXT: ret i32 [[TMP133]]
|
|
//
|
|
//
|
|
// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96
|
|
// CHECK5-SAME: () #[[ATTR2:[0-9]+]] {
|
|
// CHECK5-NEXT: entry:
|
|
// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
|
|
// CHECK5-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined.
|
|
// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] {
|
|
// CHECK5-NEXT: entry:
|
|
// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4
|
|
// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK5-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
|
|
// CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
|
|
// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5
|
|
// CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK5: cond.true:
|
|
// CHECK5-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK5: cond.false:
|
|
// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK5-NEXT: br label [[COND_END]]
|
|
// CHECK5: cond.end:
|
|
// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
|
|
// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK5-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK5: omp.inner.for.cond:
|
|
// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
|
|
// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !10
|
|
// CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
|
|
// CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK5: omp.inner.for.body:
|
|
// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
|
|
// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5
|
|
// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]]
|
|
// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10
|
|
// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK5: omp.body.continue:
|
|
// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK5: omp.inner.for.inc:
|
|
// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
|
|
// CHECK5-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
|
|
// CHECK5-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
|
|
// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]
|
|
// CHECK5: omp.inner.for.end:
|
|
// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK5: omp.loop.exit:
|
|
// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
|
|
// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK5-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0
|
|
// CHECK5-NEXT: br i1 [[TMP10]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
|
|
// CHECK5: .omp.final.then:
|
|
// CHECK5-NEXT: store i32 33, i32* [[I]], align 4
|
|
// CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]]
|
|
// CHECK5: .omp.final.done:
|
|
// CHECK5-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK5-LABEL: define {{[^@]+}}@.omp_task_entry.
|
|
// CHECK5-SAME: (i32 signext [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] {
|
|
// CHECK5-NEXT: entry:
|
|
// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
|
|
// CHECK5-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8
|
|
// CHECK5-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8
|
|
// CHECK5-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8
|
|
// CHECK5-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8
|
|
// CHECK5-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 8
|
|
// CHECK5-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4
|
|
// CHECK5-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8
|
|
// CHECK5-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4
|
|
// CHECK5-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8
|
|
// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4
|
|
// CHECK5-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8
|
|
// CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
|
|
// CHECK5-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
|
|
// CHECK5-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0
|
|
// CHECK5-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8
|
|
// CHECK5-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon*
|
|
// CHECK5-NEXT: [[TMP9:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8*
|
|
// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META16:![0-9]+]])
|
|
// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]])
|
|
// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META21:![0-9]+]])
|
|
// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META23:![0-9]+]])
|
|
// CHECK5-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !25
|
|
// CHECK5-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !25
|
|
// CHECK5-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !25
|
|
// CHECK5-NEXT: store void (i8*, ...)* null, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !25
|
|
// CHECK5-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !25
|
|
// CHECK5-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !25
|
|
// CHECK5-NEXT: [[TMP10:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !25
|
|
// CHECK5-NEXT: [[TMP11:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 0, i32 0, i8* null, i32 0, i8* null) #[[ATTR4]]
|
|
// CHECK5-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
|
|
// CHECK5-NEXT: br i1 [[TMP12]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]]
|
|
// CHECK5: omp_offload.failed.i:
|
|
// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96() #[[ATTR4]]
|
|
// CHECK5-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]]
|
|
// CHECK5: .omp_outlined..1.exit:
|
|
// CHECK5-NEXT: ret i32 0
|
|
//
|
|
//
|
|
// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101
|
|
// CHECK5-SAME: (i64 [[A:%.*]], i64 [[K:%.*]]) #[[ATTR3]] {
|
|
// CHECK5-NEXT: entry:
|
|
// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK5-NEXT: [[K_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK5-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK5-NEXT: [[K_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK5-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK5-NEXT: store i64 [[K]], i64* [[K_ADDR]], align 8
|
|
// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
|
|
// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32*
|
|
// CHECK5-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
|
|
// CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
|
|
// CHECK5-NEXT: [[TMP2:%.*]] = load i64, i64* [[K_ADDR]], align 8
|
|
// CHECK5-NEXT: store i64 [[TMP2]], i64* [[K_CASTED]], align 8
|
|
// CHECK5-NEXT: [[TMP3:%.*]] = load i64, i64* [[K_CASTED]], align 8
|
|
// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
|
|
// CHECK5-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..2
|
|
// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[K:%.*]]) #[[ATTR3]] {
|
|
// CHECK5-NEXT: entry:
|
|
// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK5-NEXT: [[K_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK5-NEXT: [[DOTLINEAR_START:%.*]] = alloca i64, align 8
|
|
// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4
|
|
// CHECK5-NEXT: [[K1:%.*]] = alloca i64, align 8
|
|
// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK5-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK5-NEXT: store i64 [[K]], i64* [[K_ADDR]], align 8
|
|
// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK5-NEXT: [[TMP0:%.*]] = load i64, i64* [[K_ADDR]], align 8
|
|
// CHECK5-NEXT: store i64 [[TMP0]], i64* [[DOTLINEAR_START]], align 8
|
|
// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK5-NEXT: store i32 8, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK5-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
|
|
// CHECK5-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP2]])
|
|
// CHECK5-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32 1073741859, i32 0, i32 8, i32 1, i32 1)
|
|
// CHECK5-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
|
|
// CHECK5: omp.dispatch.cond:
|
|
// CHECK5-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
|
|
// CHECK5-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP3]], 0
|
|
// CHECK5-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
|
|
// CHECK5: omp.dispatch.body:
|
|
// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK5-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK5: omp.inner.for.cond:
|
|
// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !26
|
|
// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !26
|
|
// CHECK5-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
|
|
// CHECK5-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK5: omp.inner.for.body:
|
|
// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !26
|
|
// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
|
|
// CHECK5-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL]]
|
|
// CHECK5-NEXT: store i32 [[SUB]], i32* [[I]], align 4, !llvm.access.group !26
|
|
// CHECK5-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8, !llvm.access.group !26
|
|
// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !26
|
|
// CHECK5-NEXT: [[MUL2:%.*]] = mul nsw i32 [[TMP9]], 3
|
|
// CHECK5-NEXT: [[CONV3:%.*]] = sext i32 [[MUL2]] to i64
|
|
// CHECK5-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP8]], [[CONV3]]
|
|
// CHECK5-NEXT: store i64 [[ADD]], i64* [[K1]], align 8, !llvm.access.group !26
|
|
// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !26
|
|
// CHECK5-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], 1
|
|
// CHECK5-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 8, !llvm.access.group !26
|
|
// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK5: omp.body.continue:
|
|
// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK5: omp.inner.for.inc:
|
|
// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !26
|
|
// CHECK5-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1
|
|
// CHECK5-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !26
|
|
// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP27:![0-9]+]]
|
|
// CHECK5: omp.inner.for.end:
|
|
// CHECK5-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
|
|
// CHECK5: omp.dispatch.inc:
|
|
// CHECK5-NEXT: br label [[OMP_DISPATCH_COND]]
|
|
// CHECK5: omp.dispatch.end:
|
|
// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK5-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0
|
|
// CHECK5-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
|
|
// CHECK5: .omp.final.then:
|
|
// CHECK5-NEXT: store i32 1, i32* [[I]], align 4
|
|
// CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]]
|
|
// CHECK5: .omp.final.done:
|
|
// CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK5-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0
|
|
// CHECK5-NEXT: br i1 [[TMP15]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
|
|
// CHECK5: .omp.linear.pu:
|
|
// CHECK5-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8
|
|
// CHECK5-NEXT: [[ADD6:%.*]] = add nsw i64 [[TMP16]], 27
|
|
// CHECK5-NEXT: store i64 [[ADD6]], i64* [[K_ADDR]], align 8
|
|
// CHECK5-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]]
|
|
// CHECK5: .omp.linear.pu.done:
|
|
// CHECK5-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108
|
|
// CHECK5-SAME: (i64 [[AA:%.*]], i64 [[LIN:%.*]], i64 [[A:%.*]]) #[[ATTR2]] {
|
|
// CHECK5-NEXT: entry:
|
|
// CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK5-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK5-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK5-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK5-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK5-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
|
|
// CHECK5-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8
|
|
// CHECK5-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
|
|
// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32*
|
|
// CHECK5-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK5-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8
|
|
// CHECK5-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
|
|
// CHECK5-NEXT: store i16 [[TMP0]], i16* [[CONV3]], align 2
|
|
// CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
|
|
// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8
|
|
// CHECK5-NEXT: [[CONV4:%.*]] = bitcast i64* [[LIN_CASTED]] to i32*
|
|
// CHECK5-NEXT: store i32 [[TMP2]], i32* [[CONV4]], align 4
|
|
// CHECK5-NEXT: [[TMP3:%.*]] = load i64, i64* [[LIN_CASTED]], align 8
|
|
// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV2]], align 8
|
|
// CHECK5-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
|
|
// CHECK5-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4
|
|
// CHECK5-NEXT: [[TMP5:%.*]] = load i64, i64* [[A_CASTED]], align 8
|
|
// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]])
|
|
// CHECK5-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..3
|
|
// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]], i64 [[LIN:%.*]], i64 [[A:%.*]]) #[[ATTR3]] {
|
|
// CHECK5-NEXT: entry:
|
|
// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK5-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
|
|
// CHECK5-NEXT: [[TMP:%.*]] = alloca i64, align 8
|
|
// CHECK5-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4
|
|
// CHECK5-NEXT: [[DOTLINEAR_START3:%.*]] = alloca i32, align 4
|
|
// CHECK5-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8
|
|
// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
|
|
// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
|
|
// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
|
|
// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK5-NEXT: [[IT:%.*]] = alloca i64, align 8
|
|
// CHECK5-NEXT: [[LIN4:%.*]] = alloca i32, align 4
|
|
// CHECK5-NEXT: [[A5:%.*]] = alloca i32, align 4
|
|
// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK5-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
|
|
// CHECK5-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8
|
|
// CHECK5-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
|
|
// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32*
|
|
// CHECK5-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV1]], align 8
|
|
// CHECK5-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4
|
|
// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 8
|
|
// CHECK5-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START3]], align 4
|
|
// CHECK5-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv()
|
|
// CHECK5-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8
|
|
// CHECK5-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK5-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK5-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
|
|
// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK5-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
|
|
// CHECK5-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3]], i32 [[TMP3]])
|
|
// CHECK5-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
|
|
// CHECK5-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK5-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3
|
|
// CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK5: cond.true:
|
|
// CHECK5-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK5: cond.false:
|
|
// CHECK5-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK5-NEXT: br label [[COND_END]]
|
|
// CHECK5: cond.end:
|
|
// CHECK5-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
|
|
// CHECK5-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
|
|
// CHECK5-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK5-NEXT: store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK5: omp.inner.for.cond:
|
|
// CHECK5-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !29
|
|
// CHECK5-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !29
|
|
// CHECK5-NEXT: [[CMP6:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]]
|
|
// CHECK5-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK5: omp.inner.for.body:
|
|
// CHECK5-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !29
|
|
// CHECK5-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400
|
|
// CHECK5-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]
|
|
// CHECK5-NEXT: store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !29
|
|
// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4, !llvm.access.group !29
|
|
// CHECK5-NEXT: [[CONV7:%.*]] = sext i32 [[TMP10]] to i64
|
|
// CHECK5-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !29
|
|
// CHECK5-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !29
|
|
// CHECK5-NEXT: [[MUL8:%.*]] = mul i64 [[TMP11]], [[TMP12]]
|
|
// CHECK5-NEXT: [[ADD:%.*]] = add i64 [[CONV7]], [[MUL8]]
|
|
// CHECK5-NEXT: [[CONV9:%.*]] = trunc i64 [[ADD]] to i32
|
|
// CHECK5-NEXT: store i32 [[CONV9]], i32* [[LIN4]], align 4, !llvm.access.group !29
|
|
// CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START3]], align 4, !llvm.access.group !29
|
|
// CHECK5-NEXT: [[CONV10:%.*]] = sext i32 [[TMP13]] to i64
|
|
// CHECK5-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !29
|
|
// CHECK5-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !29
|
|
// CHECK5-NEXT: [[MUL11:%.*]] = mul i64 [[TMP14]], [[TMP15]]
|
|
// CHECK5-NEXT: [[ADD12:%.*]] = add i64 [[CONV10]], [[MUL11]]
|
|
// CHECK5-NEXT: [[CONV13:%.*]] = trunc i64 [[ADD12]] to i32
|
|
// CHECK5-NEXT: store i32 [[CONV13]], i32* [[A5]], align 4, !llvm.access.group !29
|
|
// CHECK5-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 8, !llvm.access.group !29
|
|
// CHECK5-NEXT: [[CONV14:%.*]] = sext i16 [[TMP16]] to i32
|
|
// CHECK5-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1
|
|
// CHECK5-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16
|
|
// CHECK5-NEXT: store i16 [[CONV16]], i16* [[CONV]], align 8, !llvm.access.group !29
|
|
// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK5: omp.body.continue:
|
|
// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK5: omp.inner.for.inc:
|
|
// CHECK5-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !29
|
|
// CHECK5-NEXT: [[ADD17:%.*]] = add i64 [[TMP17]], 1
|
|
// CHECK5-NEXT: store i64 [[ADD17]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !29
|
|
// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP30:![0-9]+]]
|
|
// CHECK5: omp.inner.for.end:
|
|
// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK5: omp.loop.exit:
|
|
// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
|
|
// CHECK5-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK5-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
|
|
// CHECK5-NEXT: br i1 [[TMP19]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
|
|
// CHECK5: .omp.final.then:
|
|
// CHECK5-NEXT: store i64 400, i64* [[IT]], align 8
|
|
// CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]]
|
|
// CHECK5: .omp.final.done:
|
|
// CHECK5-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK5-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0
|
|
// CHECK5-NEXT: br i1 [[TMP21]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
|
|
// CHECK5: .omp.linear.pu:
|
|
// CHECK5-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4
|
|
// CHECK5-NEXT: [[CONV18:%.*]] = sext i32 [[TMP22]] to i64
|
|
// CHECK5-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
|
|
// CHECK5-NEXT: [[MUL19:%.*]] = mul i64 4, [[TMP23]]
|
|
// CHECK5-NEXT: [[ADD20:%.*]] = add i64 [[CONV18]], [[MUL19]]
|
|
// CHECK5-NEXT: [[CONV21:%.*]] = trunc i64 [[ADD20]] to i32
|
|
// CHECK5-NEXT: store i32 [[CONV21]], i32* [[CONV1]], align 8
|
|
// CHECK5-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTLINEAR_START3]], align 4
|
|
// CHECK5-NEXT: [[CONV22:%.*]] = sext i32 [[TMP24]] to i64
|
|
// CHECK5-NEXT: [[TMP25:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
|
|
// CHECK5-NEXT: [[MUL23:%.*]] = mul i64 4, [[TMP25]]
|
|
// CHECK5-NEXT: [[ADD24:%.*]] = add i64 [[CONV22]], [[MUL23]]
|
|
// CHECK5-NEXT: [[CONV25:%.*]] = trunc i64 [[ADD24]] to i32
|
|
// CHECK5-NEXT: store i32 [[CONV25]], i32* [[CONV2]], align 8
|
|
// CHECK5-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]]
|
|
// CHECK5: .omp.linear.pu.done:
|
|
// CHECK5-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116
|
|
// CHECK5-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] {
|
|
// CHECK5-NEXT: entry:
|
|
// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK5-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK5-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK5-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK5-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
|
|
// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
|
|
// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
|
|
// CHECK5-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
|
|
// CHECK5-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4
|
|
// CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
|
|
// CHECK5-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
|
|
// CHECK5-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
|
|
// CHECK5-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2
|
|
// CHECK5-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
|
|
// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
|
|
// CHECK5-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..4
|
|
// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR3]] {
|
|
// CHECK5-NEXT: entry:
|
|
// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK5-NEXT: [[TMP:%.*]] = alloca i16, align 2
|
|
// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK5-NEXT: [[IT:%.*]] = alloca i16, align 2
|
|
// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK5-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK5-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
|
|
// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
|
|
// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK5-NEXT: store i32 3, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
|
|
// CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
|
|
// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3
|
|
// CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK5: cond.true:
|
|
// CHECK5-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK5: cond.false:
|
|
// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK5-NEXT: br label [[COND_END]]
|
|
// CHECK5: cond.end:
|
|
// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
|
|
// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK5-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK5: omp.inner.for.cond:
|
|
// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !32
|
|
// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !32
|
|
// CHECK5-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
|
|
// CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK5: omp.inner.for.body:
|
|
// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !32
|
|
// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4
|
|
// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]]
|
|
// CHECK5-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD]] to i16
|
|
// CHECK5-NEXT: store i16 [[CONV3]], i16* [[IT]], align 2, !llvm.access.group !32
|
|
// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !32
|
|
// CHECK5-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1
|
|
// CHECK5-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 8, !llvm.access.group !32
|
|
// CHECK5-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 8, !llvm.access.group !32
|
|
// CHECK5-NEXT: [[CONV5:%.*]] = sext i16 [[TMP9]] to i32
|
|
// CHECK5-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1
|
|
// CHECK5-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16
|
|
// CHECK5-NEXT: store i16 [[CONV7]], i16* [[CONV1]], align 8, !llvm.access.group !32
|
|
// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK5: omp.body.continue:
|
|
// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK5: omp.inner.for.inc:
|
|
// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !32
|
|
// CHECK5-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP10]], 1
|
|
// CHECK5-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !32
|
|
// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP33:![0-9]+]]
|
|
// CHECK5: omp.inner.for.end:
|
|
// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK5: omp.loop.exit:
|
|
// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
|
|
// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK5-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
|
|
// CHECK5-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
|
|
// CHECK5: .omp.final.then:
|
|
// CHECK5-NEXT: store i16 22, i16* [[IT]], align 2
|
|
// CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]]
|
|
// CHECK5: .omp.final.done:
|
|
// CHECK5-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140
|
|
// CHECK5-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] {
|
|
// CHECK5-NEXT: entry:
|
|
// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
|
|
// CHECK5-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK5-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8
|
|
// CHECK5-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
|
|
// CHECK5-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
|
|
// CHECK5-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8
|
|
// CHECK5-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8
|
|
// CHECK5-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
|
|
// CHECK5-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK5-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK5-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK5-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK5-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
|
|
// CHECK5-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
|
|
// CHECK5-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8
|
|
// CHECK5-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
|
|
// CHECK5-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
|
|
// CHECK5-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
|
|
// CHECK5-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8
|
|
// CHECK5-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
|
|
// CHECK5-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
|
|
// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK5-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
|
|
// CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
|
|
// CHECK5-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
|
|
// CHECK5-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
|
|
// CHECK5-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
|
|
// CHECK5-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
|
|
// CHECK5-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
|
|
// CHECK5-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
|
|
// CHECK5-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
|
|
// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
|
|
// CHECK5-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32*
|
|
// CHECK5-NEXT: store i32 [[TMP8]], i32* [[CONV6]], align 4
|
|
// CHECK5-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
|
|
// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 8
|
|
// CHECK5-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
|
|
// CHECK5-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4
|
|
// CHECK5-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
|
|
// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]])
|
|
// CHECK5-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..7
|
|
// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] {
|
|
// CHECK5-NEXT: entry:
|
|
// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
|
|
// CHECK5-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK5-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8
|
|
// CHECK5-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
|
|
// CHECK5-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
|
|
// CHECK5-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8
|
|
// CHECK5-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8
|
|
// CHECK5-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
|
|
// CHECK5-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK5-NEXT: [[TMP:%.*]] = alloca i8, align 1
|
|
// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK5-NEXT: [[IT:%.*]] = alloca i8, align 1
|
|
// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK5-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK5-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
|
|
// CHECK5-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
|
|
// CHECK5-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8
|
|
// CHECK5-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
|
|
// CHECK5-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
|
|
// CHECK5-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
|
|
// CHECK5-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8
|
|
// CHECK5-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
|
|
// CHECK5-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
|
|
// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK5-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
|
|
// CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
|
|
// CHECK5-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
|
|
// CHECK5-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
|
|
// CHECK5-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
|
|
// CHECK5-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
|
|
// CHECK5-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
|
|
// CHECK5-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
|
|
// CHECK5-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
|
|
// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK5-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 8
|
|
// CHECK5-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
|
|
// CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
|
|
// CHECK5-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
|
|
// CHECK5: omp.dispatch.cond:
|
|
// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25
|
|
// CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK5: cond.true:
|
|
// CHECK5-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK5: cond.false:
|
|
// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK5-NEXT: br label [[COND_END]]
|
|
// CHECK5: cond.end:
|
|
// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
|
|
// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK5-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK5-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
|
|
// CHECK5-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
|
|
// CHECK5: omp.dispatch.body:
|
|
// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK5: omp.inner.for.cond:
|
|
// CHECK5-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !35
|
|
// CHECK5-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !35
|
|
// CHECK5-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
|
|
// CHECK5-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK5: omp.inner.for.body:
|
|
// CHECK5-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !35
|
|
// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
|
|
// CHECK5-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]]
|
|
// CHECK5-NEXT: [[CONV8:%.*]] = trunc i32 [[SUB]] to i8
|
|
// CHECK5-NEXT: store i8 [[CONV8]], i8* [[IT]], align 1, !llvm.access.group !35
|
|
// CHECK5-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !35
|
|
// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1
|
|
// CHECK5-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8, !llvm.access.group !35
|
|
// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
|
|
// CHECK5-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !35
|
|
// CHECK5-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double
|
|
// CHECK5-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00
|
|
// CHECK5-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float
|
|
// CHECK5-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4, !llvm.access.group !35
|
|
// CHECK5-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3
|
|
// CHECK5-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4, !llvm.access.group !35
|
|
// CHECK5-NEXT: [[CONV13:%.*]] = fpext float [[TMP21]] to double
|
|
// CHECK5-NEXT: [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00
|
|
// CHECK5-NEXT: [[CONV15:%.*]] = fptrunc double [[ADD14]] to float
|
|
// CHECK5-NEXT: store float [[CONV15]], float* [[ARRAYIDX12]], align 4, !llvm.access.group !35
|
|
// CHECK5-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1
|
|
// CHECK5-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX16]], i64 0, i64 2
|
|
// CHECK5-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX17]], align 8, !llvm.access.group !35
|
|
// CHECK5-NEXT: [[ADD18:%.*]] = fadd double [[TMP22]], 1.000000e+00
|
|
// CHECK5-NEXT: store double [[ADD18]], double* [[ARRAYIDX17]], align 8, !llvm.access.group !35
|
|
// CHECK5-NEXT: [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]]
|
|
// CHECK5-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP23]]
|
|
// CHECK5-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX19]], i64 3
|
|
// CHECK5-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX20]], align 8, !llvm.access.group !35
|
|
// CHECK5-NEXT: [[ADD21:%.*]] = fadd double [[TMP24]], 1.000000e+00
|
|
// CHECK5-NEXT: store double [[ADD21]], double* [[ARRAYIDX20]], align 8, !llvm.access.group !35
|
|
// CHECK5-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0
|
|
// CHECK5-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 8, !llvm.access.group !35
|
|
// CHECK5-NEXT: [[ADD22:%.*]] = add nsw i64 [[TMP25]], 1
|
|
// CHECK5-NEXT: store i64 [[ADD22]], i64* [[X]], align 8, !llvm.access.group !35
|
|
// CHECK5-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1
|
|
// CHECK5-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 8, !llvm.access.group !35
|
|
// CHECK5-NEXT: [[CONV23:%.*]] = sext i8 [[TMP26]] to i32
|
|
// CHECK5-NEXT: [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1
|
|
// CHECK5-NEXT: [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8
|
|
// CHECK5-NEXT: store i8 [[CONV25]], i8* [[Y]], align 8, !llvm.access.group !35
|
|
// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK5: omp.body.continue:
|
|
// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK5: omp.inner.for.inc:
|
|
// CHECK5-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !35
|
|
// CHECK5-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP27]], 1
|
|
// CHECK5-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !35
|
|
// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP36:![0-9]+]]
|
|
// CHECK5: omp.inner.for.end:
|
|
// CHECK5-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
|
|
// CHECK5: omp.dispatch.inc:
|
|
// CHECK5-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK5-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK5-NEXT: [[ADD27:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]
|
|
// CHECK5-NEXT: store i32 [[ADD27]], i32* [[DOTOMP_LB]], align 4
|
|
// CHECK5-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK5-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK5-NEXT: [[ADD28:%.*]] = add nsw i32 [[TMP30]], [[TMP31]]
|
|
// CHECK5-NEXT: store i32 [[ADD28]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK5-NEXT: br label [[OMP_DISPATCH_COND]]
|
|
// CHECK5: omp.dispatch.end:
|
|
// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]])
|
|
// CHECK5-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK5-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0
|
|
// CHECK5-NEXT: br i1 [[TMP33]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
|
|
// CHECK5: .omp.final.then:
|
|
// CHECK5-NEXT: store i8 96, i8* [[IT]], align 1
|
|
// CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]]
|
|
// CHECK5: .omp.final.done:
|
|
// CHECK5-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK5-LABEL: define {{[^@]+}}@_Z3bari
|
|
// CHECK5-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
|
|
// CHECK5-NEXT: entry:
|
|
// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK5-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK5-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8
|
|
// CHECK5-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK5-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK5-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]])
|
|
// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
|
|
// CHECK5-NEXT: store i32 [[ADD]], i32* [[A]], align 4
|
|
// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK5-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]])
|
|
// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK5-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
|
|
// CHECK5-NEXT: store i32 [[ADD2]], i32* [[A]], align 4
|
|
// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK5-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]])
|
|
// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK5-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
|
|
// CHECK5-NEXT: store i32 [[ADD4]], i32* [[A]], align 4
|
|
// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK5-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]])
|
|
// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK5-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
|
|
// CHECK5-NEXT: store i32 [[ADD6]], i32* [[A]], align 4
|
|
// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK5-NEXT: ret i32 [[TMP8]]
|
|
//
|
|
//
|
|
// CHECK5-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
|
|
// CHECK5-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 {
|
|
// CHECK5-NEXT: entry:
|
|
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
|
|
// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK5-NEXT: [[B:%.*]] = alloca i32, align 4
|
|
// CHECK5-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8
|
|
// CHECK5-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8
|
|
// CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
|
|
// CHECK5-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK5-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [6 x i8*], align 8
|
|
// CHECK5-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [6 x i8*], align 8
|
|
// CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [6 x i8*], align 8
|
|
// CHECK5-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [6 x i64], align 8
|
|
// CHECK5-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK5-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
|
|
// CHECK5-NEXT: store i32 [[ADD]], i32* [[B]], align 4
|
|
// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK5-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
|
|
// CHECK5-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave()
|
|
// CHECK5-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8
|
|
// CHECK5-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]]
|
|
// CHECK5-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2
|
|
// CHECK5-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8
|
|
// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 60
|
|
// CHECK5-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8
|
|
// CHECK5-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
|
|
// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[B]], align 4
|
|
// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i32*
|
|
// CHECK5-NEXT: store i32 [[TMP6]], i32* [[CONV]], align 4
|
|
// CHECK5-NEXT: [[TMP7:%.*]] = load i64, i64* [[B_CASTED]], align 8
|
|
// CHECK5-NEXT: [[TMP8:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
|
|
// CHECK5-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP8]] to i1
|
|
// CHECK5-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
|
|
// CHECK5-NEXT: [[FROMBOOL3:%.*]] = zext i1 [[TOBOOL]] to i8
|
|
// CHECK5-NEXT: store i8 [[FROMBOOL3]], i8* [[CONV2]], align 1
|
|
// CHECK5-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
|
|
// CHECK5-NEXT: [[TMP10:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
|
|
// CHECK5-NEXT: [[TOBOOL4:%.*]] = trunc i8 [[TMP10]] to i1
|
|
// CHECK5-NEXT: br i1 [[TOBOOL4]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
|
|
// CHECK5: omp_if.then:
|
|
// CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
|
|
// CHECK5-NEXT: [[TMP11:%.*]] = mul nuw i64 2, [[TMP2]]
|
|
// CHECK5-NEXT: [[TMP12:%.*]] = mul nuw i64 [[TMP11]], 2
|
|
// CHECK5-NEXT: [[TMP13:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK5-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to %struct.S1**
|
|
// CHECK5-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP14]], align 8
|
|
// CHECK5-NEXT: [[TMP15:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK5-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to double**
|
|
// CHECK5-NEXT: store double* [[A]], double** [[TMP16]], align 8
|
|
// CHECK5-NEXT: [[TMP17:%.*]] = getelementptr inbounds [6 x i64], [6 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
|
|
// CHECK5-NEXT: store i64 8, i64* [[TMP17]], align 8
|
|
// CHECK5-NEXT: [[TMP18:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
|
|
// CHECK5-NEXT: store i8* null, i8** [[TMP18]], align 8
|
|
// CHECK5-NEXT: [[TMP19:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
|
|
// CHECK5-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64*
|
|
// CHECK5-NEXT: store i64 [[TMP7]], i64* [[TMP20]], align 8
|
|
// CHECK5-NEXT: [[TMP21:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
|
|
// CHECK5-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i64*
|
|
// CHECK5-NEXT: store i64 [[TMP7]], i64* [[TMP22]], align 8
|
|
// CHECK5-NEXT: [[TMP23:%.*]] = getelementptr inbounds [6 x i64], [6 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1
|
|
// CHECK5-NEXT: store i64 4, i64* [[TMP23]], align 8
|
|
// CHECK5-NEXT: [[TMP24:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
|
|
// CHECK5-NEXT: store i8* null, i8** [[TMP24]], align 8
|
|
// CHECK5-NEXT: [[TMP25:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
|
|
// CHECK5-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i64*
|
|
// CHECK5-NEXT: store i64 2, i64* [[TMP26]], align 8
|
|
// CHECK5-NEXT: [[TMP27:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
|
|
// CHECK5-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i64*
|
|
// CHECK5-NEXT: store i64 2, i64* [[TMP28]], align 8
|
|
// CHECK5-NEXT: [[TMP29:%.*]] = getelementptr inbounds [6 x i64], [6 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2
|
|
// CHECK5-NEXT: store i64 8, i64* [[TMP29]], align 8
|
|
// CHECK5-NEXT: [[TMP30:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
|
|
// CHECK5-NEXT: store i8* null, i8** [[TMP30]], align 8
|
|
// CHECK5-NEXT: [[TMP31:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
|
|
// CHECK5-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i64*
|
|
// CHECK5-NEXT: store i64 [[TMP2]], i64* [[TMP32]], align 8
|
|
// CHECK5-NEXT: [[TMP33:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
|
|
// CHECK5-NEXT: [[TMP34:%.*]] = bitcast i8** [[TMP33]] to i64*
|
|
// CHECK5-NEXT: store i64 [[TMP2]], i64* [[TMP34]], align 8
|
|
// CHECK5-NEXT: [[TMP35:%.*]] = getelementptr inbounds [6 x i64], [6 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3
|
|
// CHECK5-NEXT: store i64 8, i64* [[TMP35]], align 8
|
|
// CHECK5-NEXT: [[TMP36:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
|
|
// CHECK5-NEXT: store i8* null, i8** [[TMP36]], align 8
|
|
// CHECK5-NEXT: [[TMP37:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
|
|
// CHECK5-NEXT: [[TMP38:%.*]] = bitcast i8** [[TMP37]] to i16**
|
|
// CHECK5-NEXT: store i16* [[VLA]], i16** [[TMP38]], align 8
|
|
// CHECK5-NEXT: [[TMP39:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
|
|
// CHECK5-NEXT: [[TMP40:%.*]] = bitcast i8** [[TMP39]] to i16**
|
|
// CHECK5-NEXT: store i16* [[VLA]], i16** [[TMP40]], align 8
|
|
// CHECK5-NEXT: [[TMP41:%.*]] = getelementptr inbounds [6 x i64], [6 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4
|
|
// CHECK5-NEXT: store i64 [[TMP12]], i64* [[TMP41]], align 8
|
|
// CHECK5-NEXT: [[TMP42:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4
|
|
// CHECK5-NEXT: store i8* null, i8** [[TMP42]], align 8
|
|
// CHECK5-NEXT: [[TMP43:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 5
|
|
// CHECK5-NEXT: [[TMP44:%.*]] = bitcast i8** [[TMP43]] to i64*
|
|
// CHECK5-NEXT: store i64 [[TMP9]], i64* [[TMP44]], align 8
|
|
// CHECK5-NEXT: [[TMP45:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 5
|
|
// CHECK5-NEXT: [[TMP46:%.*]] = bitcast i8** [[TMP45]] to i64*
|
|
// CHECK5-NEXT: store i64 [[TMP9]], i64* [[TMP46]], align 8
|
|
// CHECK5-NEXT: [[TMP47:%.*]] = getelementptr inbounds [6 x i64], [6 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 5
|
|
// CHECK5-NEXT: store i64 1, i64* [[TMP47]], align 8
|
|
// CHECK5-NEXT: [[TMP48:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 5
|
|
// CHECK5-NEXT: store i8* null, i8** [[TMP48]], align 8
|
|
// CHECK5-NEXT: [[TMP49:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK5-NEXT: [[TMP50:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK5-NEXT: [[TMP51:%.*]] = getelementptr inbounds [6 x i64], [6 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
|
|
// CHECK5-NEXT: [[TMP52:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
|
|
// CHECK5-NEXT: [[TOBOOL5:%.*]] = trunc i8 [[TMP52]] to i1
|
|
// CHECK5-NEXT: [[TMP53:%.*]] = select i1 [[TOBOOL5]], i32 0, i32 1
|
|
// CHECK5-NEXT: [[TMP54:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214.region_id, i32 6, i8** [[TMP49]], i8** [[TMP50]], i64* [[TMP51]], i64* getelementptr inbounds ([6 x i64], [6 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP53]])
|
|
// CHECK5-NEXT: [[TMP55:%.*]] = icmp ne i32 [[TMP54]], 0
|
|
// CHECK5-NEXT: br i1 [[TMP55]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
|
// CHECK5: omp_offload.failed:
|
|
// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214(%struct.S1* [[THIS1]], i64 [[TMP7]], i64 2, i64 [[TMP2]], i16* [[VLA]], i64 [[TMP9]]) #[[ATTR4]]
|
|
// CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
|
// CHECK5: omp_offload.cont:
|
|
// CHECK5-NEXT: br label [[OMP_IF_END:%.*]]
|
|
// CHECK5: omp_if.else:
|
|
// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214(%struct.S1* [[THIS1]], i64 [[TMP7]], i64 2, i64 [[TMP2]], i16* [[VLA]], i64 [[TMP9]]) #[[ATTR4]]
|
|
// CHECK5-NEXT: br label [[OMP_IF_END]]
|
|
// CHECK5: omp_if.end:
|
|
// CHECK5-NEXT: [[TMP56:%.*]] = mul nsw i64 1, [[TMP2]]
|
|
// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP56]]
|
|
// CHECK5-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
|
|
// CHECK5-NEXT: [[TMP57:%.*]] = load i16, i16* [[ARRAYIDX6]], align 2
|
|
// CHECK5-NEXT: [[CONV7:%.*]] = sext i16 [[TMP57]] to i32
|
|
// CHECK5-NEXT: [[TMP58:%.*]] = load i32, i32* [[B]], align 4
|
|
// CHECK5-NEXT: [[ADD8:%.*]] = add nsw i32 [[CONV7]], [[TMP58]]
|
|
// CHECK5-NEXT: [[TMP59:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
|
|
// CHECK5-NEXT: call void @llvm.stackrestore(i8* [[TMP59]])
|
|
// CHECK5-NEXT: ret i32 [[ADD8]]
|
|
//
|
|
//
|
|
// CHECK5-LABEL: define {{[^@]+}}@_ZL7fstatici
|
|
// CHECK5-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
|
|
// CHECK5-NEXT: entry:
|
|
// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK5-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK5-NEXT: [[AA:%.*]] = alloca i16, align 2
|
|
// CHECK5-NEXT: [[AAA:%.*]] = alloca i8, align 1
|
|
// CHECK5-NEXT: [[B:%.*]] = alloca [10 x i32], align 4
|
|
// CHECK5-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK5-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK5-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8
|
|
// CHECK5-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8
|
|
// CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8
|
|
// CHECK5-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK5-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK5-NEXT: store i16 0, i16* [[AA]], align 2
|
|
// CHECK5-NEXT: store i8 0, i8* [[AAA]], align 1
|
|
// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32*
|
|
// CHECK5-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4
|
|
// CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
|
|
// CHECK5-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
|
|
// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
|
|
// CHECK5-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
|
|
// CHECK5-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
|
|
// CHECK5-NEXT: [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1
|
|
// CHECK5-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
|
|
// CHECK5-NEXT: store i8 [[TMP4]], i8* [[CONV2]], align 1
|
|
// CHECK5-NEXT: [[TMP5:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
|
|
// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50
|
|
// CHECK5-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
|
|
// CHECK5: omp_if.then:
|
|
// CHECK5-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK5-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64*
|
|
// CHECK5-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8
|
|
// CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK5-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64*
|
|
// CHECK5-NEXT: store i64 [[TMP1]], i64* [[TMP10]], align 8
|
|
// CHECK5-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
|
|
// CHECK5-NEXT: store i8* null, i8** [[TMP11]], align 8
|
|
// CHECK5-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
|
|
// CHECK5-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64*
|
|
// CHECK5-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8
|
|
// CHECK5-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
|
|
// CHECK5-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64*
|
|
// CHECK5-NEXT: store i64 [[TMP3]], i64* [[TMP15]], align 8
|
|
// CHECK5-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
|
|
// CHECK5-NEXT: store i8* null, i8** [[TMP16]], align 8
|
|
// CHECK5-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
|
|
// CHECK5-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64*
|
|
// CHECK5-NEXT: store i64 [[TMP5]], i64* [[TMP18]], align 8
|
|
// CHECK5-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
|
|
// CHECK5-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64*
|
|
// CHECK5-NEXT: store i64 [[TMP5]], i64* [[TMP20]], align 8
|
|
// CHECK5-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
|
|
// CHECK5-NEXT: store i8* null, i8** [[TMP21]], align 8
|
|
// CHECK5-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
|
|
// CHECK5-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]**
|
|
// CHECK5-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 8
|
|
// CHECK5-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
|
|
// CHECK5-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]**
|
|
// CHECK5-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 8
|
|
// CHECK5-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
|
|
// CHECK5-NEXT: store i8* null, i8** [[TMP26]], align 8
|
|
// CHECK5-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK5-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK5-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
|
|
// CHECK5-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0
|
|
// CHECK5-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
|
// CHECK5: omp_offload.failed:
|
|
// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]]
|
|
// CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
|
// CHECK5: omp_offload.cont:
|
|
// CHECK5-NEXT: br label [[OMP_IF_END:%.*]]
|
|
// CHECK5: omp_if.else:
|
|
// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]]
|
|
// CHECK5-NEXT: br label [[OMP_IF_END]]
|
|
// CHECK5: omp_if.end:
|
|
// CHECK5-NEXT: [[TMP31:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK5-NEXT: ret i32 [[TMP31]]
|
|
//
|
|
//
|
|
// CHECK5-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
|
|
// CHECK5-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat {
|
|
// CHECK5-NEXT: entry:
|
|
// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK5-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK5-NEXT: [[AA:%.*]] = alloca i16, align 2
|
|
// CHECK5-NEXT: [[B:%.*]] = alloca [10 x i32], align 4
|
|
// CHECK5-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK5-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8
|
|
// CHECK5-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8
|
|
// CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8
|
|
// CHECK5-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK5-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK5-NEXT: store i16 0, i16* [[AA]], align 2
|
|
// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32*
|
|
// CHECK5-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4
|
|
// CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
|
|
// CHECK5-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
|
|
// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
|
|
// CHECK5-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
|
|
// CHECK5-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
|
|
// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40
|
|
// CHECK5-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
|
|
// CHECK5: omp_if.then:
|
|
// CHECK5-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK5-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64*
|
|
// CHECK5-NEXT: store i64 [[TMP1]], i64* [[TMP6]], align 8
|
|
// CHECK5-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK5-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64*
|
|
// CHECK5-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8
|
|
// CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
|
|
// CHECK5-NEXT: store i8* null, i8** [[TMP9]], align 8
|
|
// CHECK5-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
|
|
// CHECK5-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i64*
|
|
// CHECK5-NEXT: store i64 [[TMP3]], i64* [[TMP11]], align 8
|
|
// CHECK5-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
|
|
// CHECK5-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64*
|
|
// CHECK5-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8
|
|
// CHECK5-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
|
|
// CHECK5-NEXT: store i8* null, i8** [[TMP14]], align 8
|
|
// CHECK5-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
|
|
// CHECK5-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]**
|
|
// CHECK5-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 8
|
|
// CHECK5-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
|
|
// CHECK5-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]**
|
|
// CHECK5-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 8
|
|
// CHECK5-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
|
|
// CHECK5-NEXT: store i8* null, i8** [[TMP19]], align 8
|
|
// CHECK5-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK5-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK5-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.15, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.16, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
|
|
// CHECK5-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0
|
|
// CHECK5-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
|
// CHECK5: omp_offload.failed:
|
|
// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]]
|
|
// CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
|
// CHECK5: omp_offload.cont:
|
|
// CHECK5-NEXT: br label [[OMP_IF_END:%.*]]
|
|
// CHECK5: omp_if.else:
|
|
// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]]
|
|
// CHECK5-NEXT: br label [[OMP_IF_END]]
|
|
// CHECK5: omp_if.end:
|
|
// CHECK5-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK5-NEXT: ret i32 [[TMP24]]
|
|
//
|
|
//
|
|
// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214
|
|
// CHECK5-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] {
|
|
// CHECK5-NEXT: entry:
|
|
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
|
|
// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK5-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK5-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
|
|
// CHECK5-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8
|
|
// CHECK5-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK5-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK5-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK5-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
|
|
// CHECK5-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK5-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4
|
|
// CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]])
|
|
// CHECK5-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK5-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
|
|
// CHECK5-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
|
|
// CHECK5-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
|
|
// CHECK5-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8
|
|
// CHECK5-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
|
|
// CHECK5-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
|
|
// CHECK5-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
|
|
// CHECK5-NEXT: [[TMP3:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
|
|
// CHECK5-NEXT: [[TMP4:%.*]] = load i16*, i16** [[C_ADDR]], align 8
|
|
// CHECK5-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
|
|
// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV]], align 8
|
|
// CHECK5-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i32*
|
|
// CHECK5-NEXT: store i32 [[TMP5]], i32* [[CONV4]], align 4
|
|
// CHECK5-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8
|
|
// CHECK5-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV3]], align 8
|
|
// CHECK5-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP7]] to i1
|
|
// CHECK5-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
|
|
// CHECK5-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
|
|
// CHECK5-NEXT: store i8 [[FROMBOOL]], i8* [[CONV5]], align 1
|
|
// CHECK5-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
|
|
// CHECK5-NEXT: [[TMP9:%.*]] = load i8, i8* [[CONV3]], align 8
|
|
// CHECK5-NEXT: [[TOBOOL6:%.*]] = trunc i8 [[TMP9]] to i1
|
|
// CHECK5-NEXT: br i1 [[TOBOOL6]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
|
|
// CHECK5: omp_if.then:
|
|
// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP6]], i64 [[TMP2]], i64 [[TMP3]], i16* [[TMP4]], i64 [[TMP8]])
|
|
// CHECK5-NEXT: br label [[OMP_IF_END:%.*]]
|
|
// CHECK5: omp_if.else:
|
|
// CHECK5-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]])
|
|
// CHECK5-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
|
|
// CHECK5-NEXT: call void @.omp_outlined..9(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]], i64 [[TMP6]], i64 [[TMP2]], i64 [[TMP3]], i16* [[TMP4]], i64 [[TMP8]]) #[[ATTR4]]
|
|
// CHECK5-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]])
|
|
// CHECK5-NEXT: br label [[OMP_IF_END]]
|
|
// CHECK5: omp_if.end:
|
|
// CHECK5-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..9
|
|
// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] {
|
|
// CHECK5-NEXT: entry:
|
|
// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
|
|
// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK5-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK5-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
|
|
// CHECK5-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8
|
|
// CHECK5-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
|
|
// CHECK5-NEXT: [[TMP:%.*]] = alloca i64, align 8
|
|
// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
|
|
// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
|
|
// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
|
|
// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK5-NEXT: [[IT:%.*]] = alloca i64, align 8
|
|
// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK5-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK5-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
|
|
// CHECK5-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
|
|
// CHECK5-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
|
|
// CHECK5-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8
|
|
// CHECK5-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
|
|
// CHECK5-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
|
|
// CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
|
|
// CHECK5-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
|
|
// CHECK5-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
|
|
// CHECK5-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
|
|
// CHECK5-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK5-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK5-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
|
|
// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK5-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV3]], align 8
|
|
// CHECK5-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1
|
|
// CHECK5-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
|
|
// CHECK5: omp_if.then:
|
|
// CHECK5-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4
|
|
// CHECK5-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
|
|
// CHECK5-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK5-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP7]], 3
|
|
// CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK5: cond.true:
|
|
// CHECK5-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK5: cond.false:
|
|
// CHECK5-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK5-NEXT: br label [[COND_END]]
|
|
// CHECK5: cond.end:
|
|
// CHECK5-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ]
|
|
// CHECK5-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
|
|
// CHECK5-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK5-NEXT: store i64 [[TMP9]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK5: omp.inner.for.cond:
|
|
// CHECK5-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !38
|
|
// CHECK5-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !38
|
|
// CHECK5-NEXT: [[CMP4:%.*]] = icmp ule i64 [[TMP10]], [[TMP11]]
|
|
// CHECK5-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK5: omp.inner.for.body:
|
|
// CHECK5-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !38
|
|
// CHECK5-NEXT: [[MUL:%.*]] = mul i64 [[TMP12]], 400
|
|
// CHECK5-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]
|
|
// CHECK5-NEXT: store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !38
|
|
// CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !38
|
|
// CHECK5-NEXT: [[CONV5:%.*]] = sitofp i32 [[TMP13]] to double
|
|
// CHECK5-NEXT: [[ADD:%.*]] = fadd double [[CONV5]], 1.500000e+00
|
|
// CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
|
|
// CHECK5-NEXT: store double [[ADD]], double* [[A]], align 8, !nontemporal !39, !llvm.access.group !38
|
|
// CHECK5-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
|
|
// CHECK5-NEXT: [[TMP14:%.*]] = load double, double* [[A6]], align 8, !nontemporal !39, !llvm.access.group !38
|
|
// CHECK5-NEXT: [[INC:%.*]] = fadd double [[TMP14]], 1.000000e+00
|
|
// CHECK5-NEXT: store double [[INC]], double* [[A6]], align 8, !nontemporal !39, !llvm.access.group !38
|
|
// CHECK5-NEXT: [[CONV7:%.*]] = fptosi double [[INC]] to i16
|
|
// CHECK5-NEXT: [[TMP15:%.*]] = mul nsw i64 1, [[TMP2]]
|
|
// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP15]]
|
|
// CHECK5-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
|
|
// CHECK5-NEXT: store i16 [[CONV7]], i16* [[ARRAYIDX8]], align 2, !llvm.access.group !38
|
|
// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK5: omp.body.continue:
|
|
// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK5: omp.inner.for.inc:
|
|
// CHECK5-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !38
|
|
// CHECK5-NEXT: [[ADD9:%.*]] = add i64 [[TMP16]], 1
|
|
// CHECK5-NEXT: store i64 [[ADD9]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !38
|
|
// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP40:![0-9]+]]
|
|
// CHECK5: omp.inner.for.end:
|
|
// CHECK5-NEXT: br label [[OMP_IF_END:%.*]]
|
|
// CHECK5: omp_if.else:
|
|
// CHECK5-NEXT: [[TMP17:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK5-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP17]], align 4
|
|
// CHECK5-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP18]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
|
|
// CHECK5-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK5-NEXT: [[CMP10:%.*]] = icmp ugt i64 [[TMP19]], 3
|
|
// CHECK5-NEXT: br i1 [[CMP10]], label [[COND_TRUE11:%.*]], label [[COND_FALSE12:%.*]]
|
|
// CHECK5: cond.true11:
|
|
// CHECK5-NEXT: br label [[COND_END13:%.*]]
|
|
// CHECK5: cond.false12:
|
|
// CHECK5-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK5-NEXT: br label [[COND_END13]]
|
|
// CHECK5: cond.end13:
|
|
// CHECK5-NEXT: [[COND14:%.*]] = phi i64 [ 3, [[COND_TRUE11]] ], [ [[TMP20]], [[COND_FALSE12]] ]
|
|
// CHECK5-NEXT: store i64 [[COND14]], i64* [[DOTOMP_UB]], align 8
|
|
// CHECK5-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK5-NEXT: store i64 [[TMP21]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND15:%.*]]
|
|
// CHECK5: omp.inner.for.cond15:
|
|
// CHECK5-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK5-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK5-NEXT: [[CMP16:%.*]] = icmp ule i64 [[TMP22]], [[TMP23]]
|
|
// CHECK5-NEXT: br i1 [[CMP16]], label [[OMP_INNER_FOR_BODY17:%.*]], label [[OMP_INNER_FOR_END31:%.*]]
|
|
// CHECK5: omp.inner.for.body17:
|
|
// CHECK5-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK5-NEXT: [[MUL18:%.*]] = mul i64 [[TMP24]], 400
|
|
// CHECK5-NEXT: [[SUB19:%.*]] = sub i64 2000, [[MUL18]]
|
|
// CHECK5-NEXT: store i64 [[SUB19]], i64* [[IT]], align 8
|
|
// CHECK5-NEXT: [[TMP25:%.*]] = load i32, i32* [[CONV]], align 8
|
|
// CHECK5-NEXT: [[CONV20:%.*]] = sitofp i32 [[TMP25]] to double
|
|
// CHECK5-NEXT: [[ADD21:%.*]] = fadd double [[CONV20]], 1.500000e+00
|
|
// CHECK5-NEXT: [[A22:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
|
|
// CHECK5-NEXT: store double [[ADD21]], double* [[A22]], align 8
|
|
// CHECK5-NEXT: [[A23:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
|
|
// CHECK5-NEXT: [[TMP26:%.*]] = load double, double* [[A23]], align 8
|
|
// CHECK5-NEXT: [[INC24:%.*]] = fadd double [[TMP26]], 1.000000e+00
|
|
// CHECK5-NEXT: store double [[INC24]], double* [[A23]], align 8
|
|
// CHECK5-NEXT: [[CONV25:%.*]] = fptosi double [[INC24]] to i16
|
|
// CHECK5-NEXT: [[TMP27:%.*]] = mul nsw i64 1, [[TMP2]]
|
|
// CHECK5-NEXT: [[ARRAYIDX26:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP27]]
|
|
// CHECK5-NEXT: [[ARRAYIDX27:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX26]], i64 1
|
|
// CHECK5-NEXT: store i16 [[CONV25]], i16* [[ARRAYIDX27]], align 2
|
|
// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE28:%.*]]
|
|
// CHECK5: omp.body.continue28:
|
|
// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC29:%.*]]
|
|
// CHECK5: omp.inner.for.inc29:
|
|
// CHECK5-NEXT: [[TMP28:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK5-NEXT: [[ADD30:%.*]] = add i64 [[TMP28]], 1
|
|
// CHECK5-NEXT: store i64 [[ADD30]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND15]], !llvm.loop [[LOOP42:![0-9]+]]
|
|
// CHECK5: omp.inner.for.end31:
|
|
// CHECK5-NEXT: br label [[OMP_IF_END]]
|
|
// CHECK5: omp_if.end:
|
|
// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK5: omp.loop.exit:
|
|
// CHECK5-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK5-NEXT: [[TMP30:%.*]] = load i32, i32* [[TMP29]], align 4
|
|
// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP30]])
|
|
// CHECK5-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK5-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0
|
|
// CHECK5-NEXT: br i1 [[TMP32]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
|
|
// CHECK5: .omp.final.then:
|
|
// CHECK5-NEXT: store i64 400, i64* [[IT]], align 8
|
|
// CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]]
|
|
// CHECK5: .omp.final.done:
|
|
// CHECK5-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195
|
|
// CHECK5-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
|
|
// CHECK5-NEXT: entry:
|
|
// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK5-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
|
|
// CHECK5-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK5-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK5-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK5-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK5-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
|
|
// CHECK5-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
|
|
// CHECK5-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
|
|
// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
|
|
// CHECK5-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
|
|
// CHECK5-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
|
|
// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
|
|
// CHECK5-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
|
|
// CHECK5-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4
|
|
// CHECK5-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
|
|
// CHECK5-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
|
|
// CHECK5-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
|
|
// CHECK5-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2
|
|
// CHECK5-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
|
|
// CHECK5-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 8
|
|
// CHECK5-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
|
|
// CHECK5-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1
|
|
// CHECK5-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
|
|
// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]])
|
|
// CHECK5-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..11
|
|
// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] {
|
|
// CHECK5-NEXT: entry:
|
|
// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK5-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
|
|
// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK5-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK5-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
|
|
// CHECK5-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
|
|
// CHECK5-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
|
|
// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
|
|
// CHECK5-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
|
|
// CHECK5-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
|
|
// CHECK5-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178
|
|
// CHECK5-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
|
|
// CHECK5-NEXT: entry:
|
|
// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
|
|
// CHECK5-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK5-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK5-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK5-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
|
|
// CHECK5-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
|
|
// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
|
|
// CHECK5-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
|
|
// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
|
|
// CHECK5-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
|
|
// CHECK5-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4
|
|
// CHECK5-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
|
|
// CHECK5-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
|
|
// CHECK5-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
|
|
// CHECK5-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
|
|
// CHECK5-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
|
|
// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]])
|
|
// CHECK5-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..14
|
|
// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] {
|
|
// CHECK5-NEXT: entry:
|
|
// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
|
|
// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
|
|
// CHECK5-NEXT: [[TMP:%.*]] = alloca i64, align 8
|
|
// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
|
|
// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
|
|
// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
|
|
// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK5-NEXT: [[I:%.*]] = alloca i64, align 8
|
|
// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK5-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK5-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
|
|
// CHECK5-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
|
|
// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
|
|
// CHECK5-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
|
|
// CHECK5-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK5-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK5-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
|
|
// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK5-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
|
|
// CHECK5-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
|
|
// CHECK5-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6
|
|
// CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK5: cond.true:
|
|
// CHECK5-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK5: cond.false:
|
|
// CHECK5-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK5-NEXT: br label [[COND_END]]
|
|
// CHECK5: cond.end:
|
|
// CHECK5-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
|
|
// CHECK5-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
|
|
// CHECK5-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK5-NEXT: store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK5: omp.inner.for.cond:
|
|
// CHECK5-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !44
|
|
// CHECK5-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !44
|
|
// CHECK5-NEXT: [[CMP2:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]]
|
|
// CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK5: omp.inner.for.body:
|
|
// CHECK5-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !44
|
|
// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3
|
|
// CHECK5-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
|
|
// CHECK5-NEXT: store i64 [[ADD]], i64* [[I]], align 8, !llvm.access.group !44
|
|
// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !44
|
|
// CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1
|
|
// CHECK5-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 8, !llvm.access.group !44
|
|
// CHECK5-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 8, !llvm.access.group !44
|
|
// CHECK5-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32
|
|
// CHECK5-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
|
|
// CHECK5-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
|
|
// CHECK5-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 8, !llvm.access.group !44
|
|
// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
|
|
// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !44
|
|
// CHECK5-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1
|
|
// CHECK5-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !44
|
|
// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK5: omp.body.continue:
|
|
// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK5: omp.inner.for.inc:
|
|
// CHECK5-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !44
|
|
// CHECK5-NEXT: [[ADD8:%.*]] = add nsw i64 [[TMP12]], 1
|
|
// CHECK5-NEXT: store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !44
|
|
// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP45:![0-9]+]]
|
|
// CHECK5: omp.inner.for.end:
|
|
// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK5: omp.loop.exit:
|
|
// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
|
|
// CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK5-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
|
|
// CHECK5-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
|
|
// CHECK5: .omp.final.then:
|
|
// CHECK5-NEXT: store i64 11, i64* [[I]], align 8
|
|
// CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]]
|
|
// CHECK5: .omp.final.done:
|
|
// CHECK5-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK5-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
|
|
// CHECK5-SAME: () #[[ATTR7:[0-9]+]] {
|
|
// CHECK5-NEXT: entry:
|
|
// CHECK5-NEXT: call void @__tgt_register_requires(i64 1)
|
|
// CHECK5-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK6-LABEL: define {{[^@]+}}@_Z7get_valv
|
|
// CHECK6-SAME: () #[[ATTR0:[0-9]+]] {
|
|
// CHECK6-NEXT: entry:
|
|
// CHECK6-NEXT: ret i64 0
|
|
//
|
|
//
|
|
// CHECK6-LABEL: define {{[^@]+}}@_Z3fooi
|
|
// CHECK6-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
|
|
// CHECK6-NEXT: entry:
|
|
// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK6-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK6-NEXT: [[AA:%.*]] = alloca i16, align 2
|
|
// CHECK6-NEXT: [[B:%.*]] = alloca [10 x float], align 4
|
|
// CHECK6-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8
|
|
// CHECK6-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8
|
|
// CHECK6-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8
|
|
// CHECK6-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8
|
|
// CHECK6-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8
|
|
// CHECK6-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 1
|
|
// CHECK6-NEXT: [[K:%.*]] = alloca i64, align 8
|
|
// CHECK6-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK6-NEXT: [[K_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK6-NEXT: [[LIN:%.*]] = alloca i32, align 4
|
|
// CHECK6-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK6-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK6-NEXT: [[A_CASTED4:%.*]] = alloca i64, align 8
|
|
// CHECK6-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8
|
|
// CHECK6-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8
|
|
// CHECK6-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8
|
|
// CHECK6-NEXT: [[A_CASTED6:%.*]] = alloca i64, align 8
|
|
// CHECK6-NEXT: [[AA_CASTED8:%.*]] = alloca i64, align 8
|
|
// CHECK6-NEXT: [[DOTOFFLOAD_BASEPTRS10:%.*]] = alloca [2 x i8*], align 8
|
|
// CHECK6-NEXT: [[DOTOFFLOAD_PTRS11:%.*]] = alloca [2 x i8*], align 8
|
|
// CHECK6-NEXT: [[DOTOFFLOAD_MAPPERS12:%.*]] = alloca [2 x i8*], align 8
|
|
// CHECK6-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
|
// CHECK6-NEXT: [[A_CASTED15:%.*]] = alloca i64, align 8
|
|
// CHECK6-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK6-NEXT: [[DOTOFFLOAD_BASEPTRS20:%.*]] = alloca [10 x i8*], align 8
|
|
// CHECK6-NEXT: [[DOTOFFLOAD_PTRS21:%.*]] = alloca [10 x i8*], align 8
|
|
// CHECK6-NEXT: [[DOTOFFLOAD_MAPPERS22:%.*]] = alloca [10 x i8*], align 8
|
|
// CHECK6-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 8
|
|
// CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]])
|
|
// CHECK6-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK6-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK6-NEXT: store i16 0, i16* [[AA]], align 2
|
|
// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK6-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
|
|
// CHECK6-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave()
|
|
// CHECK6-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8
|
|
// CHECK6-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP2]], align 4
|
|
// CHECK6-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8
|
|
// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK6-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64
|
|
// CHECK6-NEXT: [[TMP6:%.*]] = mul nuw i64 5, [[TMP5]]
|
|
// CHECK6-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP6]], align 8
|
|
// CHECK6-NEXT: store i64 [[TMP5]], i64* [[__VLA_EXPR1]], align 8
|
|
// CHECK6-NEXT: [[TMP7:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 1, i64 40, i64 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1)
|
|
// CHECK6-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.kmp_task_t_with_privates*
|
|
// CHECK6-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP8]], i32 0, i32 0
|
|
// CHECK6-NEXT: [[TMP10:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i8* [[TMP7]])
|
|
// CHECK6-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv()
|
|
// CHECK6-NEXT: store i64 [[CALL]], i64* [[K]], align 8
|
|
// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32*
|
|
// CHECK6-NEXT: store i32 [[TMP11]], i32* [[CONV]], align 4
|
|
// CHECK6-NEXT: [[TMP12:%.*]] = load i64, i64* [[A_CASTED]], align 8
|
|
// CHECK6-NEXT: [[TMP13:%.*]] = load i64, i64* [[K]], align 8
|
|
// CHECK6-NEXT: store i64 [[TMP13]], i64* [[K_CASTED]], align 8
|
|
// CHECK6-NEXT: [[TMP14:%.*]] = load i64, i64* [[K_CASTED]], align 8
|
|
// CHECK6-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101(i64 [[TMP12]], i64 [[TMP14]]) #[[ATTR4:[0-9]+]]
|
|
// CHECK6-NEXT: store i32 12, i32* [[LIN]], align 4
|
|
// CHECK6-NEXT: [[TMP15:%.*]] = load i16, i16* [[AA]], align 2
|
|
// CHECK6-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
|
|
// CHECK6-NEXT: store i16 [[TMP15]], i16* [[CONV2]], align 2
|
|
// CHECK6-NEXT: [[TMP16:%.*]] = load i64, i64* [[AA_CASTED]], align 8
|
|
// CHECK6-NEXT: [[TMP17:%.*]] = load i32, i32* [[LIN]], align 4
|
|
// CHECK6-NEXT: [[CONV3:%.*]] = bitcast i64* [[LIN_CASTED]] to i32*
|
|
// CHECK6-NEXT: store i32 [[TMP17]], i32* [[CONV3]], align 4
|
|
// CHECK6-NEXT: [[TMP18:%.*]] = load i64, i64* [[LIN_CASTED]], align 8
|
|
// CHECK6-NEXT: [[TMP19:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK6-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED4]] to i32*
|
|
// CHECK6-NEXT: store i32 [[TMP19]], i32* [[CONV5]], align 4
|
|
// CHECK6-NEXT: [[TMP20:%.*]] = load i64, i64* [[A_CASTED4]], align 8
|
|
// CHECK6-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK6-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i64*
|
|
// CHECK6-NEXT: store i64 [[TMP16]], i64* [[TMP22]], align 8
|
|
// CHECK6-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK6-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i64*
|
|
// CHECK6-NEXT: store i64 [[TMP16]], i64* [[TMP24]], align 8
|
|
// CHECK6-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
|
|
// CHECK6-NEXT: store i8* null, i8** [[TMP25]], align 8
|
|
// CHECK6-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
|
|
// CHECK6-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64*
|
|
// CHECK6-NEXT: store i64 [[TMP18]], i64* [[TMP27]], align 8
|
|
// CHECK6-NEXT: [[TMP28:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
|
|
// CHECK6-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i64*
|
|
// CHECK6-NEXT: store i64 [[TMP18]], i64* [[TMP29]], align 8
|
|
// CHECK6-NEXT: [[TMP30:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
|
|
// CHECK6-NEXT: store i8* null, i8** [[TMP30]], align 8
|
|
// CHECK6-NEXT: [[TMP31:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
|
|
// CHECK6-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i64*
|
|
// CHECK6-NEXT: store i64 [[TMP20]], i64* [[TMP32]], align 8
|
|
// CHECK6-NEXT: [[TMP33:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
|
|
// CHECK6-NEXT: [[TMP34:%.*]] = bitcast i8** [[TMP33]] to i64*
|
|
// CHECK6-NEXT: store i64 [[TMP20]], i64* [[TMP34]], align 8
|
|
// CHECK6-NEXT: [[TMP35:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
|
|
// CHECK6-NEXT: store i8* null, i8** [[TMP35]], align 8
|
|
// CHECK6-NEXT: [[TMP36:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK6-NEXT: [[TMP37:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK6-NEXT: [[TMP38:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108.region_id, i32 3, i8** [[TMP36]], i8** [[TMP37]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
|
|
// CHECK6-NEXT: [[TMP39:%.*]] = icmp ne i32 [[TMP38]], 0
|
|
// CHECK6-NEXT: br i1 [[TMP39]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
|
// CHECK6: omp_offload.failed:
|
|
// CHECK6-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108(i64 [[TMP16]], i64 [[TMP18]], i64 [[TMP20]]) #[[ATTR4]]
|
|
// CHECK6-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
|
// CHECK6: omp_offload.cont:
|
|
// CHECK6-NEXT: [[TMP40:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK6-NEXT: [[CONV7:%.*]] = bitcast i64* [[A_CASTED6]] to i32*
|
|
// CHECK6-NEXT: store i32 [[TMP40]], i32* [[CONV7]], align 4
|
|
// CHECK6-NEXT: [[TMP41:%.*]] = load i64, i64* [[A_CASTED6]], align 8
|
|
// CHECK6-NEXT: [[TMP42:%.*]] = load i16, i16* [[AA]], align 2
|
|
// CHECK6-NEXT: [[CONV9:%.*]] = bitcast i64* [[AA_CASTED8]] to i16*
|
|
// CHECK6-NEXT: store i16 [[TMP42]], i16* [[CONV9]], align 2
|
|
// CHECK6-NEXT: [[TMP43:%.*]] = load i64, i64* [[AA_CASTED8]], align 8
|
|
// CHECK6-NEXT: [[TMP44:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK6-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP44]], 10
|
|
// CHECK6-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
|
|
// CHECK6: omp_if.then:
|
|
// CHECK6-NEXT: [[TMP45:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 0
|
|
// CHECK6-NEXT: [[TMP46:%.*]] = bitcast i8** [[TMP45]] to i64*
|
|
// CHECK6-NEXT: store i64 [[TMP41]], i64* [[TMP46]], align 8
|
|
// CHECK6-NEXT: [[TMP47:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS11]], i32 0, i32 0
|
|
// CHECK6-NEXT: [[TMP48:%.*]] = bitcast i8** [[TMP47]] to i64*
|
|
// CHECK6-NEXT: store i64 [[TMP41]], i64* [[TMP48]], align 8
|
|
// CHECK6-NEXT: [[TMP49:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS12]], i64 0, i64 0
|
|
// CHECK6-NEXT: store i8* null, i8** [[TMP49]], align 8
|
|
// CHECK6-NEXT: [[TMP50:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 1
|
|
// CHECK6-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP50]] to i64*
|
|
// CHECK6-NEXT: store i64 [[TMP43]], i64* [[TMP51]], align 8
|
|
// CHECK6-NEXT: [[TMP52:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS11]], i32 0, i32 1
|
|
// CHECK6-NEXT: [[TMP53:%.*]] = bitcast i8** [[TMP52]] to i64*
|
|
// CHECK6-NEXT: store i64 [[TMP43]], i64* [[TMP53]], align 8
|
|
// CHECK6-NEXT: [[TMP54:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS12]], i64 0, i64 1
|
|
// CHECK6-NEXT: store i8* null, i8** [[TMP54]], align 8
|
|
// CHECK6-NEXT: [[TMP55:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 0
|
|
// CHECK6-NEXT: [[TMP56:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS11]], i32 0, i32 0
|
|
// CHECK6-NEXT: [[TMP57:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116.region_id, i32 2, i8** [[TMP55]], i8** [[TMP56]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
|
|
// CHECK6-NEXT: [[TMP58:%.*]] = icmp ne i32 [[TMP57]], 0
|
|
// CHECK6-NEXT: br i1 [[TMP58]], label [[OMP_OFFLOAD_FAILED13:%.*]], label [[OMP_OFFLOAD_CONT14:%.*]]
|
|
// CHECK6: omp_offload.failed13:
|
|
// CHECK6-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116(i64 [[TMP41]], i64 [[TMP43]]) #[[ATTR4]]
|
|
// CHECK6-NEXT: br label [[OMP_OFFLOAD_CONT14]]
|
|
// CHECK6: omp_offload.cont14:
|
|
// CHECK6-NEXT: br label [[OMP_IF_END:%.*]]
|
|
// CHECK6: omp_if.else:
|
|
// CHECK6-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116(i64 [[TMP41]], i64 [[TMP43]]) #[[ATTR4]]
|
|
// CHECK6-NEXT: br label [[OMP_IF_END]]
|
|
// CHECK6: omp_if.end:
|
|
// CHECK6-NEXT: [[TMP59:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK6-NEXT: store i32 [[TMP59]], i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK6-NEXT: [[TMP60:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK6-NEXT: [[CONV16:%.*]] = bitcast i64* [[A_CASTED15]] to i32*
|
|
// CHECK6-NEXT: store i32 [[TMP60]], i32* [[CONV16]], align 4
|
|
// CHECK6-NEXT: [[TMP61:%.*]] = load i64, i64* [[A_CASTED15]], align 8
|
|
// CHECK6-NEXT: [[TMP62:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK6-NEXT: [[CONV17:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
|
|
// CHECK6-NEXT: store i32 [[TMP62]], i32* [[CONV17]], align 4
|
|
// CHECK6-NEXT: [[TMP63:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
|
|
// CHECK6-NEXT: [[TMP64:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK6-NEXT: [[CMP18:%.*]] = icmp sgt i32 [[TMP64]], 20
|
|
// CHECK6-NEXT: br i1 [[CMP18]], label [[OMP_IF_THEN19:%.*]], label [[OMP_IF_ELSE25:%.*]]
|
|
// CHECK6: omp_if.then19:
|
|
// CHECK6-NEXT: [[TMP65:%.*]] = mul nuw i64 [[TMP2]], 4
|
|
// CHECK6-NEXT: [[TMP66:%.*]] = mul nuw i64 5, [[TMP5]]
|
|
// CHECK6-NEXT: [[TMP67:%.*]] = mul nuw i64 [[TMP66]], 8
|
|
// CHECK6-NEXT: [[TMP68:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0
|
|
// CHECK6-NEXT: [[TMP69:%.*]] = bitcast i8** [[TMP68]] to i64*
|
|
// CHECK6-NEXT: store i64 [[TMP61]], i64* [[TMP69]], align 8
|
|
// CHECK6-NEXT: [[TMP70:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 0
|
|
// CHECK6-NEXT: [[TMP71:%.*]] = bitcast i8** [[TMP70]] to i64*
|
|
// CHECK6-NEXT: store i64 [[TMP61]], i64* [[TMP71]], align 8
|
|
// CHECK6-NEXT: [[TMP72:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
|
|
// CHECK6-NEXT: store i64 4, i64* [[TMP72]], align 8
|
|
// CHECK6-NEXT: [[TMP73:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 0
|
|
// CHECK6-NEXT: store i8* null, i8** [[TMP73]], align 8
|
|
// CHECK6-NEXT: [[TMP74:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 1
|
|
// CHECK6-NEXT: [[TMP75:%.*]] = bitcast i8** [[TMP74]] to [10 x float]**
|
|
// CHECK6-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP75]], align 8
|
|
// CHECK6-NEXT: [[TMP76:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 1
|
|
// CHECK6-NEXT: [[TMP77:%.*]] = bitcast i8** [[TMP76]] to [10 x float]**
|
|
// CHECK6-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP77]], align 8
|
|
// CHECK6-NEXT: [[TMP78:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1
|
|
// CHECK6-NEXT: store i64 40, i64* [[TMP78]], align 8
|
|
// CHECK6-NEXT: [[TMP79:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 1
|
|
// CHECK6-NEXT: store i8* null, i8** [[TMP79]], align 8
|
|
// CHECK6-NEXT: [[TMP80:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 2
|
|
// CHECK6-NEXT: [[TMP81:%.*]] = bitcast i8** [[TMP80]] to i64*
|
|
// CHECK6-NEXT: store i64 [[TMP2]], i64* [[TMP81]], align 8
|
|
// CHECK6-NEXT: [[TMP82:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 2
|
|
// CHECK6-NEXT: [[TMP83:%.*]] = bitcast i8** [[TMP82]] to i64*
|
|
// CHECK6-NEXT: store i64 [[TMP2]], i64* [[TMP83]], align 8
|
|
// CHECK6-NEXT: [[TMP84:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2
|
|
// CHECK6-NEXT: store i64 8, i64* [[TMP84]], align 8
|
|
// CHECK6-NEXT: [[TMP85:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 2
|
|
// CHECK6-NEXT: store i8* null, i8** [[TMP85]], align 8
|
|
// CHECK6-NEXT: [[TMP86:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 3
|
|
// CHECK6-NEXT: [[TMP87:%.*]] = bitcast i8** [[TMP86]] to float**
|
|
// CHECK6-NEXT: store float* [[VLA]], float** [[TMP87]], align 8
|
|
// CHECK6-NEXT: [[TMP88:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 3
|
|
// CHECK6-NEXT: [[TMP89:%.*]] = bitcast i8** [[TMP88]] to float**
|
|
// CHECK6-NEXT: store float* [[VLA]], float** [[TMP89]], align 8
|
|
// CHECK6-NEXT: [[TMP90:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3
|
|
// CHECK6-NEXT: store i64 [[TMP65]], i64* [[TMP90]], align 8
|
|
// CHECK6-NEXT: [[TMP91:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 3
|
|
// CHECK6-NEXT: store i8* null, i8** [[TMP91]], align 8
|
|
// CHECK6-NEXT: [[TMP92:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 4
|
|
// CHECK6-NEXT: [[TMP93:%.*]] = bitcast i8** [[TMP92]] to [5 x [10 x double]]**
|
|
// CHECK6-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP93]], align 8
|
|
// CHECK6-NEXT: [[TMP94:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 4
|
|
// CHECK6-NEXT: [[TMP95:%.*]] = bitcast i8** [[TMP94]] to [5 x [10 x double]]**
|
|
// CHECK6-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP95]], align 8
|
|
// CHECK6-NEXT: [[TMP96:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4
|
|
// CHECK6-NEXT: store i64 400, i64* [[TMP96]], align 8
|
|
// CHECK6-NEXT: [[TMP97:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 4
|
|
// CHECK6-NEXT: store i8* null, i8** [[TMP97]], align 8
|
|
// CHECK6-NEXT: [[TMP98:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 5
|
|
// CHECK6-NEXT: [[TMP99:%.*]] = bitcast i8** [[TMP98]] to i64*
|
|
// CHECK6-NEXT: store i64 5, i64* [[TMP99]], align 8
|
|
// CHECK6-NEXT: [[TMP100:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 5
|
|
// CHECK6-NEXT: [[TMP101:%.*]] = bitcast i8** [[TMP100]] to i64*
|
|
// CHECK6-NEXT: store i64 5, i64* [[TMP101]], align 8
|
|
// CHECK6-NEXT: [[TMP102:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 5
|
|
// CHECK6-NEXT: store i64 8, i64* [[TMP102]], align 8
|
|
// CHECK6-NEXT: [[TMP103:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 5
|
|
// CHECK6-NEXT: store i8* null, i8** [[TMP103]], align 8
|
|
// CHECK6-NEXT: [[TMP104:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 6
|
|
// CHECK6-NEXT: [[TMP105:%.*]] = bitcast i8** [[TMP104]] to i64*
|
|
// CHECK6-NEXT: store i64 [[TMP5]], i64* [[TMP105]], align 8
|
|
// CHECK6-NEXT: [[TMP106:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 6
|
|
// CHECK6-NEXT: [[TMP107:%.*]] = bitcast i8** [[TMP106]] to i64*
|
|
// CHECK6-NEXT: store i64 [[TMP5]], i64* [[TMP107]], align 8
|
|
// CHECK6-NEXT: [[TMP108:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 6
|
|
// CHECK6-NEXT: store i64 8, i64* [[TMP108]], align 8
|
|
// CHECK6-NEXT: [[TMP109:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 6
|
|
// CHECK6-NEXT: store i8* null, i8** [[TMP109]], align 8
|
|
// CHECK6-NEXT: [[TMP110:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 7
|
|
// CHECK6-NEXT: [[TMP111:%.*]] = bitcast i8** [[TMP110]] to double**
|
|
// CHECK6-NEXT: store double* [[VLA1]], double** [[TMP111]], align 8
|
|
// CHECK6-NEXT: [[TMP112:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 7
|
|
// CHECK6-NEXT: [[TMP113:%.*]] = bitcast i8** [[TMP112]] to double**
|
|
// CHECK6-NEXT: store double* [[VLA1]], double** [[TMP113]], align 8
|
|
// CHECK6-NEXT: [[TMP114:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7
|
|
// CHECK6-NEXT: store i64 [[TMP67]], i64* [[TMP114]], align 8
|
|
// CHECK6-NEXT: [[TMP115:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 7
|
|
// CHECK6-NEXT: store i8* null, i8** [[TMP115]], align 8
|
|
// CHECK6-NEXT: [[TMP116:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 8
|
|
// CHECK6-NEXT: [[TMP117:%.*]] = bitcast i8** [[TMP116]] to %struct.TT**
|
|
// CHECK6-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP117]], align 8
|
|
// CHECK6-NEXT: [[TMP118:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 8
|
|
// CHECK6-NEXT: [[TMP119:%.*]] = bitcast i8** [[TMP118]] to %struct.TT**
|
|
// CHECK6-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP119]], align 8
|
|
// CHECK6-NEXT: [[TMP120:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 8
|
|
// CHECK6-NEXT: store i64 16, i64* [[TMP120]], align 8
|
|
// CHECK6-NEXT: [[TMP121:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 8
|
|
// CHECK6-NEXT: store i8* null, i8** [[TMP121]], align 8
|
|
// CHECK6-NEXT: [[TMP122:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 9
|
|
// CHECK6-NEXT: [[TMP123:%.*]] = bitcast i8** [[TMP122]] to i64*
|
|
// CHECK6-NEXT: store i64 [[TMP63]], i64* [[TMP123]], align 8
|
|
// CHECK6-NEXT: [[TMP124:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 9
|
|
// CHECK6-NEXT: [[TMP125:%.*]] = bitcast i8** [[TMP124]] to i64*
|
|
// CHECK6-NEXT: store i64 [[TMP63]], i64* [[TMP125]], align 8
|
|
// CHECK6-NEXT: [[TMP126:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 9
|
|
// CHECK6-NEXT: store i64 4, i64* [[TMP126]], align 8
|
|
// CHECK6-NEXT: [[TMP127:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 9
|
|
// CHECK6-NEXT: store i8* null, i8** [[TMP127]], align 8
|
|
// CHECK6-NEXT: [[TMP128:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0
|
|
// CHECK6-NEXT: [[TMP129:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 0
|
|
// CHECK6-NEXT: [[TMP130:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
|
|
// CHECK6-NEXT: [[TMP131:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140.region_id, i32 10, i8** [[TMP128]], i8** [[TMP129]], i64* [[TMP130]], i64* getelementptr inbounds ([10 x i64], [10 x i64]* @.offload_maptypes.8, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
|
|
// CHECK6-NEXT: [[TMP132:%.*]] = icmp ne i32 [[TMP131]], 0
|
|
// CHECK6-NEXT: br i1 [[TMP132]], label [[OMP_OFFLOAD_FAILED23:%.*]], label [[OMP_OFFLOAD_CONT24:%.*]]
|
|
// CHECK6: omp_offload.failed23:
|
|
// CHECK6-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140(i64 [[TMP61]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]], i64 [[TMP63]]) #[[ATTR4]]
|
|
// CHECK6-NEXT: br label [[OMP_OFFLOAD_CONT24]]
|
|
// CHECK6: omp_offload.cont24:
|
|
// CHECK6-NEXT: br label [[OMP_IF_END26:%.*]]
|
|
// CHECK6: omp_if.else25:
|
|
// CHECK6-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140(i64 [[TMP61]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]], i64 [[TMP63]]) #[[ATTR4]]
|
|
// CHECK6-NEXT: br label [[OMP_IF_END26]]
|
|
// CHECK6: omp_if.end26:
|
|
// CHECK6-NEXT: [[TMP133:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK6-NEXT: [[TMP134:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
|
|
// CHECK6-NEXT: call void @llvm.stackrestore(i8* [[TMP134]])
|
|
// CHECK6-NEXT: ret i32 [[TMP133]]
|
|
//
|
|
//
|
|
// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96
|
|
// CHECK6-SAME: () #[[ATTR2:[0-9]+]] {
|
|
// CHECK6-NEXT: entry:
|
|
// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
|
|
// CHECK6-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined.
|
|
// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] {
|
|
// CHECK6-NEXT: entry:
|
|
// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4
|
|
// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK6-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
|
|
// CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
|
|
// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK6-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5
|
|
// CHECK6-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK6: cond.true:
|
|
// CHECK6-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK6: cond.false:
|
|
// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK6-NEXT: br label [[COND_END]]
|
|
// CHECK6: cond.end:
|
|
// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
|
|
// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK6-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK6: omp.inner.for.cond:
|
|
// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
|
|
// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !10
|
|
// CHECK6-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
|
|
// CHECK6-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK6: omp.inner.for.body:
|
|
// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
|
|
// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5
|
|
// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]]
|
|
// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10
|
|
// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK6: omp.body.continue:
|
|
// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK6: omp.inner.for.inc:
|
|
// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
|
|
// CHECK6-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
|
|
// CHECK6-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
|
|
// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]
|
|
// CHECK6: omp.inner.for.end:
|
|
// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK6: omp.loop.exit:
|
|
// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
|
|
// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK6-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0
|
|
// CHECK6-NEXT: br i1 [[TMP10]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
|
|
// CHECK6: .omp.final.then:
|
|
// CHECK6-NEXT: store i32 33, i32* [[I]], align 4
|
|
// CHECK6-NEXT: br label [[DOTOMP_FINAL_DONE]]
|
|
// CHECK6: .omp.final.done:
|
|
// CHECK6-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK6-LABEL: define {{[^@]+}}@.omp_task_entry.
|
|
// CHECK6-SAME: (i32 signext [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] {
|
|
// CHECK6-NEXT: entry:
|
|
// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
|
|
// CHECK6-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8
|
|
// CHECK6-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8
|
|
// CHECK6-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8
|
|
// CHECK6-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8
|
|
// CHECK6-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 8
|
|
// CHECK6-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4
|
|
// CHECK6-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8
|
|
// CHECK6-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4
|
|
// CHECK6-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8
|
|
// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4
|
|
// CHECK6-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8
|
|
// CHECK6-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
|
|
// CHECK6-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
|
|
// CHECK6-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0
|
|
// CHECK6-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8
|
|
// CHECK6-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon*
|
|
// CHECK6-NEXT: [[TMP9:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8*
|
|
// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META16:![0-9]+]])
|
|
// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]])
|
|
// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META21:![0-9]+]])
|
|
// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META23:![0-9]+]])
|
|
// CHECK6-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !25
|
|
// CHECK6-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !25
|
|
// CHECK6-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !25
|
|
// CHECK6-NEXT: store void (i8*, ...)* null, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !25
|
|
// CHECK6-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !25
|
|
// CHECK6-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !25
|
|
// CHECK6-NEXT: [[TMP10:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !25
|
|
// CHECK6-NEXT: [[TMP11:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 0, i32 0, i8* null, i32 0, i8* null) #[[ATTR4]]
|
|
// CHECK6-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
|
|
// CHECK6-NEXT: br i1 [[TMP12]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]]
|
|
// CHECK6: omp_offload.failed.i:
|
|
// CHECK6-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96() #[[ATTR4]]
|
|
// CHECK6-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]]
|
|
// CHECK6: .omp_outlined..1.exit:
|
|
// CHECK6-NEXT: ret i32 0
|
|
//
|
|
//
|
|
// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101
|
|
// CHECK6-SAME: (i64 [[A:%.*]], i64 [[K:%.*]]) #[[ATTR3]] {
|
|
// CHECK6-NEXT: entry:
|
|
// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK6-NEXT: [[K_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK6-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK6-NEXT: [[K_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK6-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK6-NEXT: store i64 [[K]], i64* [[K_ADDR]], align 8
|
|
// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
|
|
// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32*
|
|
// CHECK6-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
|
|
// CHECK6-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
|
|
// CHECK6-NEXT: [[TMP2:%.*]] = load i64, i64* [[K_ADDR]], align 8
|
|
// CHECK6-NEXT: store i64 [[TMP2]], i64* [[K_CASTED]], align 8
|
|
// CHECK6-NEXT: [[TMP3:%.*]] = load i64, i64* [[K_CASTED]], align 8
|
|
// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
|
|
// CHECK6-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..2
|
|
// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[K:%.*]]) #[[ATTR3]] {
|
|
// CHECK6-NEXT: entry:
|
|
// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK6-NEXT: [[K_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK6-NEXT: [[DOTLINEAR_START:%.*]] = alloca i64, align 8
|
|
// CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4
|
|
// CHECK6-NEXT: [[K1:%.*]] = alloca i64, align 8
|
|
// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK6-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK6-NEXT: store i64 [[K]], i64* [[K_ADDR]], align 8
|
|
// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK6-NEXT: [[TMP0:%.*]] = load i64, i64* [[K_ADDR]], align 8
|
|
// CHECK6-NEXT: store i64 [[TMP0]], i64* [[DOTLINEAR_START]], align 8
|
|
// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK6-NEXT: store i32 8, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK6-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
|
|
// CHECK6-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP2]])
|
|
// CHECK6-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32 1073741859, i32 0, i32 8, i32 1, i32 1)
|
|
// CHECK6-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
|
|
// CHECK6: omp.dispatch.cond:
|
|
// CHECK6-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
|
|
// CHECK6-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP3]], 0
|
|
// CHECK6-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
|
|
// CHECK6: omp.dispatch.body:
|
|
// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK6-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK6: omp.inner.for.cond:
|
|
// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !26
|
|
// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !26
|
|
// CHECK6-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
|
|
// CHECK6-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK6: omp.inner.for.body:
|
|
// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !26
|
|
// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
|
|
// CHECK6-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL]]
|
|
// CHECK6-NEXT: store i32 [[SUB]], i32* [[I]], align 4, !llvm.access.group !26
|
|
// CHECK6-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8, !llvm.access.group !26
|
|
// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !26
|
|
// CHECK6-NEXT: [[MUL2:%.*]] = mul nsw i32 [[TMP9]], 3
|
|
// CHECK6-NEXT: [[CONV3:%.*]] = sext i32 [[MUL2]] to i64
|
|
// CHECK6-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP8]], [[CONV3]]
|
|
// CHECK6-NEXT: store i64 [[ADD]], i64* [[K1]], align 8, !llvm.access.group !26
|
|
// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !26
|
|
// CHECK6-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], 1
|
|
// CHECK6-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 8, !llvm.access.group !26
|
|
// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK6: omp.body.continue:
|
|
// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK6: omp.inner.for.inc:
|
|
// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !26
|
|
// CHECK6-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1
|
|
// CHECK6-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !26
|
|
// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP27:![0-9]+]]
|
|
// CHECK6: omp.inner.for.end:
|
|
// CHECK6-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
|
|
// CHECK6: omp.dispatch.inc:
|
|
// CHECK6-NEXT: br label [[OMP_DISPATCH_COND]]
|
|
// CHECK6: omp.dispatch.end:
|
|
// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK6-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0
|
|
// CHECK6-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
|
|
// CHECK6: .omp.final.then:
|
|
// CHECK6-NEXT: store i32 1, i32* [[I]], align 4
|
|
// CHECK6-NEXT: br label [[DOTOMP_FINAL_DONE]]
|
|
// CHECK6: .omp.final.done:
|
|
// CHECK6-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK6-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0
|
|
// CHECK6-NEXT: br i1 [[TMP15]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
|
|
// CHECK6: .omp.linear.pu:
|
|
// CHECK6-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8
|
|
// CHECK6-NEXT: [[ADD6:%.*]] = add nsw i64 [[TMP16]], 27
|
|
// CHECK6-NEXT: store i64 [[ADD6]], i64* [[K_ADDR]], align 8
|
|
// CHECK6-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]]
|
|
// CHECK6: .omp.linear.pu.done:
|
|
// CHECK6-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108
|
|
// CHECK6-SAME: (i64 [[AA:%.*]], i64 [[LIN:%.*]], i64 [[A:%.*]]) #[[ATTR2]] {
|
|
// CHECK6-NEXT: entry:
|
|
// CHECK6-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK6-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK6-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK6-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK6-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK6-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
|
|
// CHECK6-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8
|
|
// CHECK6-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
|
|
// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32*
|
|
// CHECK6-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK6-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8
|
|
// CHECK6-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
|
|
// CHECK6-NEXT: store i16 [[TMP0]], i16* [[CONV3]], align 2
|
|
// CHECK6-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
|
|
// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8
|
|
// CHECK6-NEXT: [[CONV4:%.*]] = bitcast i64* [[LIN_CASTED]] to i32*
|
|
// CHECK6-NEXT: store i32 [[TMP2]], i32* [[CONV4]], align 4
|
|
// CHECK6-NEXT: [[TMP3:%.*]] = load i64, i64* [[LIN_CASTED]], align 8
|
|
// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV2]], align 8
|
|
// CHECK6-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
|
|
// CHECK6-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4
|
|
// CHECK6-NEXT: [[TMP5:%.*]] = load i64, i64* [[A_CASTED]], align 8
|
|
// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]])
|
|
// CHECK6-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..3
|
|
// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]], i64 [[LIN:%.*]], i64 [[A:%.*]]) #[[ATTR3]] {
|
|
// CHECK6-NEXT: entry:
|
|
// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK6-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK6-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
|
|
// CHECK6-NEXT: [[TMP:%.*]] = alloca i64, align 8
|
|
// CHECK6-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4
|
|
// CHECK6-NEXT: [[DOTLINEAR_START3:%.*]] = alloca i32, align 4
|
|
// CHECK6-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8
|
|
// CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
|
|
// CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
|
|
// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
|
|
// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK6-NEXT: [[IT:%.*]] = alloca i64, align 8
|
|
// CHECK6-NEXT: [[LIN4:%.*]] = alloca i32, align 4
|
|
// CHECK6-NEXT: [[A5:%.*]] = alloca i32, align 4
|
|
// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK6-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
|
|
// CHECK6-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8
|
|
// CHECK6-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
|
|
// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32*
|
|
// CHECK6-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV1]], align 8
|
|
// CHECK6-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4
|
|
// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 8
|
|
// CHECK6-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START3]], align 4
|
|
// CHECK6-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv()
|
|
// CHECK6-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8
|
|
// CHECK6-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK6-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK6-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
|
|
// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK6-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
|
|
// CHECK6-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3]], i32 [[TMP3]])
|
|
// CHECK6-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
|
|
// CHECK6-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK6-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3
|
|
// CHECK6-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK6: cond.true:
|
|
// CHECK6-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK6: cond.false:
|
|
// CHECK6-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK6-NEXT: br label [[COND_END]]
|
|
// CHECK6: cond.end:
|
|
// CHECK6-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
|
|
// CHECK6-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
|
|
// CHECK6-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK6-NEXT: store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK6: omp.inner.for.cond:
|
|
// CHECK6-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !29
|
|
// CHECK6-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !29
|
|
// CHECK6-NEXT: [[CMP6:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]]
|
|
// CHECK6-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK6: omp.inner.for.body:
|
|
// CHECK6-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !29
|
|
// CHECK6-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400
|
|
// CHECK6-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]
|
|
// CHECK6-NEXT: store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !29
|
|
// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4, !llvm.access.group !29
|
|
// CHECK6-NEXT: [[CONV7:%.*]] = sext i32 [[TMP10]] to i64
|
|
// CHECK6-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !29
|
|
// CHECK6-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !29
|
|
// CHECK6-NEXT: [[MUL8:%.*]] = mul i64 [[TMP11]], [[TMP12]]
|
|
// CHECK6-NEXT: [[ADD:%.*]] = add i64 [[CONV7]], [[MUL8]]
|
|
// CHECK6-NEXT: [[CONV9:%.*]] = trunc i64 [[ADD]] to i32
|
|
// CHECK6-NEXT: store i32 [[CONV9]], i32* [[LIN4]], align 4, !llvm.access.group !29
|
|
// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START3]], align 4, !llvm.access.group !29
|
|
// CHECK6-NEXT: [[CONV10:%.*]] = sext i32 [[TMP13]] to i64
|
|
// CHECK6-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !29
|
|
// CHECK6-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !29
|
|
// CHECK6-NEXT: [[MUL11:%.*]] = mul i64 [[TMP14]], [[TMP15]]
|
|
// CHECK6-NEXT: [[ADD12:%.*]] = add i64 [[CONV10]], [[MUL11]]
|
|
// CHECK6-NEXT: [[CONV13:%.*]] = trunc i64 [[ADD12]] to i32
|
|
// CHECK6-NEXT: store i32 [[CONV13]], i32* [[A5]], align 4, !llvm.access.group !29
|
|
// CHECK6-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 8, !llvm.access.group !29
|
|
// CHECK6-NEXT: [[CONV14:%.*]] = sext i16 [[TMP16]] to i32
|
|
// CHECK6-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1
|
|
// CHECK6-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16
|
|
// CHECK6-NEXT: store i16 [[CONV16]], i16* [[CONV]], align 8, !llvm.access.group !29
|
|
// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK6: omp.body.continue:
|
|
// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK6: omp.inner.for.inc:
|
|
// CHECK6-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !29
|
|
// CHECK6-NEXT: [[ADD17:%.*]] = add i64 [[TMP17]], 1
|
|
// CHECK6-NEXT: store i64 [[ADD17]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !29
|
|
// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP30:![0-9]+]]
|
|
// CHECK6: omp.inner.for.end:
|
|
// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK6: omp.loop.exit:
|
|
// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
|
|
// CHECK6-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK6-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
|
|
// CHECK6-NEXT: br i1 [[TMP19]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
|
|
// CHECK6: .omp.final.then:
|
|
// CHECK6-NEXT: store i64 400, i64* [[IT]], align 8
|
|
// CHECK6-NEXT: br label [[DOTOMP_FINAL_DONE]]
|
|
// CHECK6: .omp.final.done:
|
|
// CHECK6-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK6-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0
|
|
// CHECK6-NEXT: br i1 [[TMP21]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
|
|
// CHECK6: .omp.linear.pu:
|
|
// CHECK6-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4
|
|
// CHECK6-NEXT: [[CONV18:%.*]] = sext i32 [[TMP22]] to i64
|
|
// CHECK6-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
|
|
// CHECK6-NEXT: [[MUL19:%.*]] = mul i64 4, [[TMP23]]
|
|
// CHECK6-NEXT: [[ADD20:%.*]] = add i64 [[CONV18]], [[MUL19]]
|
|
// CHECK6-NEXT: [[CONV21:%.*]] = trunc i64 [[ADD20]] to i32
|
|
// CHECK6-NEXT: store i32 [[CONV21]], i32* [[CONV1]], align 8
|
|
// CHECK6-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTLINEAR_START3]], align 4
|
|
// CHECK6-NEXT: [[CONV22:%.*]] = sext i32 [[TMP24]] to i64
|
|
// CHECK6-NEXT: [[TMP25:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
|
|
// CHECK6-NEXT: [[MUL23:%.*]] = mul i64 4, [[TMP25]]
|
|
// CHECK6-NEXT: [[ADD24:%.*]] = add i64 [[CONV22]], [[MUL23]]
|
|
// CHECK6-NEXT: [[CONV25:%.*]] = trunc i64 [[ADD24]] to i32
|
|
// CHECK6-NEXT: store i32 [[CONV25]], i32* [[CONV2]], align 8
|
|
// CHECK6-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]]
|
|
// CHECK6: .omp.linear.pu.done:
|
|
// CHECK6-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116
|
|
// CHECK6-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] {
|
|
// CHECK6-NEXT: entry:
|
|
// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK6-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK6-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK6-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK6-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK6-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
|
|
// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
|
|
// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
|
|
// CHECK6-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
|
|
// CHECK6-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4
|
|
// CHECK6-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
|
|
// CHECK6-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
|
|
// CHECK6-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
|
|
// CHECK6-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2
|
|
// CHECK6-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
|
|
// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
|
|
// CHECK6-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..4
|
|
// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR3]] {
|
|
// CHECK6-NEXT: entry:
|
|
// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK6-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK6-NEXT: [[TMP:%.*]] = alloca i16, align 2
|
|
// CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK6-NEXT: [[IT:%.*]] = alloca i16, align 2
|
|
// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK6-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK6-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
|
|
// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
|
|
// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK6-NEXT: store i32 3, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
|
|
// CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
|
|
// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK6-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3
|
|
// CHECK6-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK6: cond.true:
|
|
// CHECK6-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK6: cond.false:
|
|
// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK6-NEXT: br label [[COND_END]]
|
|
// CHECK6: cond.end:
|
|
// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
|
|
// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK6-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK6: omp.inner.for.cond:
|
|
// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !32
|
|
// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !32
|
|
// CHECK6-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
|
|
// CHECK6-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK6: omp.inner.for.body:
|
|
// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !32
|
|
// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4
|
|
// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]]
|
|
// CHECK6-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD]] to i16
|
|
// CHECK6-NEXT: store i16 [[CONV3]], i16* [[IT]], align 2, !llvm.access.group !32
|
|
// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !32
|
|
// CHECK6-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1
|
|
// CHECK6-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 8, !llvm.access.group !32
|
|
// CHECK6-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 8, !llvm.access.group !32
|
|
// CHECK6-NEXT: [[CONV5:%.*]] = sext i16 [[TMP9]] to i32
|
|
// CHECK6-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1
|
|
// CHECK6-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16
|
|
// CHECK6-NEXT: store i16 [[CONV7]], i16* [[CONV1]], align 8, !llvm.access.group !32
|
|
// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK6: omp.body.continue:
|
|
// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK6: omp.inner.for.inc:
|
|
// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !32
|
|
// CHECK6-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP10]], 1
|
|
// CHECK6-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !32
|
|
// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP33:![0-9]+]]
|
|
// CHECK6: omp.inner.for.end:
|
|
// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK6: omp.loop.exit:
|
|
// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
|
|
// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK6-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
|
|
// CHECK6-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
|
|
// CHECK6: .omp.final.then:
|
|
// CHECK6-NEXT: store i16 22, i16* [[IT]], align 2
|
|
// CHECK6-NEXT: br label [[DOTOMP_FINAL_DONE]]
|
|
// CHECK6: .omp.final.done:
|
|
// CHECK6-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140
|
|
// CHECK6-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] {
|
|
// CHECK6-NEXT: entry:
|
|
// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK6-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
|
|
// CHECK6-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK6-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8
|
|
// CHECK6-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
|
|
// CHECK6-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
|
|
// CHECK6-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8
|
|
// CHECK6-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8
|
|
// CHECK6-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
|
|
// CHECK6-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK6-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK6-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK6-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK6-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
|
|
// CHECK6-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
|
|
// CHECK6-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8
|
|
// CHECK6-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
|
|
// CHECK6-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
|
|
// CHECK6-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
|
|
// CHECK6-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8
|
|
// CHECK6-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
|
|
// CHECK6-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
|
|
// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK6-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
|
|
// CHECK6-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
|
|
// CHECK6-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
|
|
// CHECK6-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
|
|
// CHECK6-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
|
|
// CHECK6-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
|
|
// CHECK6-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
|
|
// CHECK6-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
|
|
// CHECK6-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
|
|
// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
|
|
// CHECK6-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32*
|
|
// CHECK6-NEXT: store i32 [[TMP8]], i32* [[CONV6]], align 4
|
|
// CHECK6-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
|
|
// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 8
|
|
// CHECK6-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
|
|
// CHECK6-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4
|
|
// CHECK6-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
|
|
// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]])
|
|
// CHECK6-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..7
|
|
// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] {
|
|
// CHECK6-NEXT: entry:
|
|
// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK6-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
|
|
// CHECK6-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK6-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8
|
|
// CHECK6-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
|
|
// CHECK6-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
|
|
// CHECK6-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8
|
|
// CHECK6-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8
|
|
// CHECK6-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
|
|
// CHECK6-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK6-NEXT: [[TMP:%.*]] = alloca i8, align 1
|
|
// CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK6-NEXT: [[IT:%.*]] = alloca i8, align 1
|
|
// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK6-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK6-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
|
|
// CHECK6-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
|
|
// CHECK6-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8
|
|
// CHECK6-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
|
|
// CHECK6-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
|
|
// CHECK6-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
|
|
// CHECK6-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8
|
|
// CHECK6-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
|
|
// CHECK6-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
|
|
// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK6-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
|
|
// CHECK6-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
|
|
// CHECK6-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
|
|
// CHECK6-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
|
|
// CHECK6-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
|
|
// CHECK6-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
|
|
// CHECK6-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
|
|
// CHECK6-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
|
|
// CHECK6-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
|
|
// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK6-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 8
|
|
// CHECK6-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
|
|
// CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
|
|
// CHECK6-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
|
|
// CHECK6: omp.dispatch.cond:
|
|
// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK6-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25
|
|
// CHECK6-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK6: cond.true:
|
|
// CHECK6-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK6: cond.false:
|
|
// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK6-NEXT: br label [[COND_END]]
|
|
// CHECK6: cond.end:
|
|
// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
|
|
// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK6-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK6-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK6-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK6-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
|
|
// CHECK6-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
|
|
// CHECK6: omp.dispatch.body:
|
|
// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK6: omp.inner.for.cond:
|
|
// CHECK6-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !35
|
|
// CHECK6-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !35
|
|
// CHECK6-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
|
|
// CHECK6-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK6: omp.inner.for.body:
|
|
// CHECK6-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !35
|
|
// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
|
|
// CHECK6-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]]
|
|
// CHECK6-NEXT: [[CONV8:%.*]] = trunc i32 [[SUB]] to i8
|
|
// CHECK6-NEXT: store i8 [[CONV8]], i8* [[IT]], align 1, !llvm.access.group !35
|
|
// CHECK6-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !35
|
|
// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1
|
|
// CHECK6-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8, !llvm.access.group !35
|
|
// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
|
|
// CHECK6-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !35
|
|
// CHECK6-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double
|
|
// CHECK6-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00
|
|
// CHECK6-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float
|
|
// CHECK6-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4, !llvm.access.group !35
|
|
// CHECK6-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3
|
|
// CHECK6-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4, !llvm.access.group !35
|
|
// CHECK6-NEXT: [[CONV13:%.*]] = fpext float [[TMP21]] to double
|
|
// CHECK6-NEXT: [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00
|
|
// CHECK6-NEXT: [[CONV15:%.*]] = fptrunc double [[ADD14]] to float
|
|
// CHECK6-NEXT: store float [[CONV15]], float* [[ARRAYIDX12]], align 4, !llvm.access.group !35
|
|
// CHECK6-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1
|
|
// CHECK6-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX16]], i64 0, i64 2
|
|
// CHECK6-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX17]], align 8, !llvm.access.group !35
|
|
// CHECK6-NEXT: [[ADD18:%.*]] = fadd double [[TMP22]], 1.000000e+00
|
|
// CHECK6-NEXT: store double [[ADD18]], double* [[ARRAYIDX17]], align 8, !llvm.access.group !35
|
|
// CHECK6-NEXT: [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]]
|
|
// CHECK6-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP23]]
|
|
// CHECK6-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX19]], i64 3
|
|
// CHECK6-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX20]], align 8, !llvm.access.group !35
|
|
// CHECK6-NEXT: [[ADD21:%.*]] = fadd double [[TMP24]], 1.000000e+00
|
|
// CHECK6-NEXT: store double [[ADD21]], double* [[ARRAYIDX20]], align 8, !llvm.access.group !35
|
|
// CHECK6-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0
|
|
// CHECK6-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 8, !llvm.access.group !35
|
|
// CHECK6-NEXT: [[ADD22:%.*]] = add nsw i64 [[TMP25]], 1
|
|
// CHECK6-NEXT: store i64 [[ADD22]], i64* [[X]], align 8, !llvm.access.group !35
|
|
// CHECK6-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1
|
|
// CHECK6-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 8, !llvm.access.group !35
|
|
// CHECK6-NEXT: [[CONV23:%.*]] = sext i8 [[TMP26]] to i32
|
|
// CHECK6-NEXT: [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1
|
|
// CHECK6-NEXT: [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8
|
|
// CHECK6-NEXT: store i8 [[CONV25]], i8* [[Y]], align 8, !llvm.access.group !35
|
|
// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK6: omp.body.continue:
|
|
// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK6: omp.inner.for.inc:
|
|
// CHECK6-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !35
|
|
// CHECK6-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP27]], 1
|
|
// CHECK6-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !35
|
|
// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP36:![0-9]+]]
|
|
// CHECK6: omp.inner.for.end:
|
|
// CHECK6-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
|
|
// CHECK6: omp.dispatch.inc:
|
|
// CHECK6-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK6-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK6-NEXT: [[ADD27:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]
|
|
// CHECK6-NEXT: store i32 [[ADD27]], i32* [[DOTOMP_LB]], align 4
|
|
// CHECK6-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK6-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK6-NEXT: [[ADD28:%.*]] = add nsw i32 [[TMP30]], [[TMP31]]
|
|
// CHECK6-NEXT: store i32 [[ADD28]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK6-NEXT: br label [[OMP_DISPATCH_COND]]
|
|
// CHECK6: omp.dispatch.end:
|
|
// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]])
|
|
// CHECK6-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK6-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0
|
|
// CHECK6-NEXT: br i1 [[TMP33]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
|
|
// CHECK6: .omp.final.then:
|
|
// CHECK6-NEXT: store i8 96, i8* [[IT]], align 1
|
|
// CHECK6-NEXT: br label [[DOTOMP_FINAL_DONE]]
|
|
// CHECK6: .omp.final.done:
|
|
// CHECK6-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK6-LABEL: define {{[^@]+}}@_Z3bari
|
|
// CHECK6-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
|
|
// CHECK6-NEXT: entry:
|
|
// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK6-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK6-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8
|
|
// CHECK6-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK6-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK6-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]])
|
|
// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
|
|
// CHECK6-NEXT: store i32 [[ADD]], i32* [[A]], align 4
|
|
// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK6-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]])
|
|
// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK6-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
|
|
// CHECK6-NEXT: store i32 [[ADD2]], i32* [[A]], align 4
|
|
// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK6-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]])
|
|
// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK6-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
|
|
// CHECK6-NEXT: store i32 [[ADD4]], i32* [[A]], align 4
|
|
// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK6-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]])
|
|
// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK6-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
|
|
// CHECK6-NEXT: store i32 [[ADD6]], i32* [[A]], align 4
|
|
// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK6-NEXT: ret i32 [[TMP8]]
|
|
//
|
|
//
|
|
// CHECK6-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
|
|
// CHECK6-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 {
|
|
// CHECK6-NEXT: entry:
|
|
// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
|
|
// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK6-NEXT: [[B:%.*]] = alloca i32, align 4
|
|
// CHECK6-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8
|
|
// CHECK6-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8
|
|
// CHECK6-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
|
|
// CHECK6-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK6-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK6-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [6 x i8*], align 8
|
|
// CHECK6-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [6 x i8*], align 8
|
|
// CHECK6-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [6 x i8*], align 8
|
|
// CHECK6-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [6 x i64], align 8
|
|
// CHECK6-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK6-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
|
|
// CHECK6-NEXT: store i32 [[ADD]], i32* [[B]], align 4
|
|
// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK6-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
|
|
// CHECK6-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave()
|
|
// CHECK6-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8
|
|
// CHECK6-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]]
|
|
// CHECK6-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2
|
|
// CHECK6-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8
|
|
// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK6-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 60
|
|
// CHECK6-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8
|
|
// CHECK6-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
|
|
// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[B]], align 4
|
|
// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i32*
|
|
// CHECK6-NEXT: store i32 [[TMP6]], i32* [[CONV]], align 4
|
|
// CHECK6-NEXT: [[TMP7:%.*]] = load i64, i64* [[B_CASTED]], align 8
|
|
// CHECK6-NEXT: [[TMP8:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
|
|
// CHECK6-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP8]] to i1
|
|
// CHECK6-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
|
|
// CHECK6-NEXT: [[FROMBOOL3:%.*]] = zext i1 [[TOBOOL]] to i8
|
|
// CHECK6-NEXT: store i8 [[FROMBOOL3]], i8* [[CONV2]], align 1
|
|
// CHECK6-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
|
|
// CHECK6-NEXT: [[TMP10:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
|
|
// CHECK6-NEXT: [[TOBOOL4:%.*]] = trunc i8 [[TMP10]] to i1
|
|
// CHECK6-NEXT: br i1 [[TOBOOL4]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
|
|
// CHECK6: omp_if.then:
|
|
// CHECK6-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
|
|
// CHECK6-NEXT: [[TMP11:%.*]] = mul nuw i64 2, [[TMP2]]
|
|
// CHECK6-NEXT: [[TMP12:%.*]] = mul nuw i64 [[TMP11]], 2
|
|
// CHECK6-NEXT: [[TMP13:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK6-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to %struct.S1**
|
|
// CHECK6-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP14]], align 8
|
|
// CHECK6-NEXT: [[TMP15:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK6-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to double**
|
|
// CHECK6-NEXT: store double* [[A]], double** [[TMP16]], align 8
|
|
// CHECK6-NEXT: [[TMP17:%.*]] = getelementptr inbounds [6 x i64], [6 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
|
|
// CHECK6-NEXT: store i64 8, i64* [[TMP17]], align 8
|
|
// CHECK6-NEXT: [[TMP18:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
|
|
// CHECK6-NEXT: store i8* null, i8** [[TMP18]], align 8
|
|
// CHECK6-NEXT: [[TMP19:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
|
|
// CHECK6-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64*
|
|
// CHECK6-NEXT: store i64 [[TMP7]], i64* [[TMP20]], align 8
|
|
// CHECK6-NEXT: [[TMP21:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
|
|
// CHECK6-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i64*
|
|
// CHECK6-NEXT: store i64 [[TMP7]], i64* [[TMP22]], align 8
|
|
// CHECK6-NEXT: [[TMP23:%.*]] = getelementptr inbounds [6 x i64], [6 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1
|
|
// CHECK6-NEXT: store i64 4, i64* [[TMP23]], align 8
|
|
// CHECK6-NEXT: [[TMP24:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
|
|
// CHECK6-NEXT: store i8* null, i8** [[TMP24]], align 8
|
|
// CHECK6-NEXT: [[TMP25:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
|
|
// CHECK6-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i64*
|
|
// CHECK6-NEXT: store i64 2, i64* [[TMP26]], align 8
|
|
// CHECK6-NEXT: [[TMP27:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
|
|
// CHECK6-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i64*
|
|
// CHECK6-NEXT: store i64 2, i64* [[TMP28]], align 8
|
|
// CHECK6-NEXT: [[TMP29:%.*]] = getelementptr inbounds [6 x i64], [6 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2
|
|
// CHECK6-NEXT: store i64 8, i64* [[TMP29]], align 8
|
|
// CHECK6-NEXT: [[TMP30:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
|
|
// CHECK6-NEXT: store i8* null, i8** [[TMP30]], align 8
|
|
// CHECK6-NEXT: [[TMP31:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
|
|
// CHECK6-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i64*
|
|
// CHECK6-NEXT: store i64 [[TMP2]], i64* [[TMP32]], align 8
|
|
// CHECK6-NEXT: [[TMP33:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
|
|
// CHECK6-NEXT: [[TMP34:%.*]] = bitcast i8** [[TMP33]] to i64*
|
|
// CHECK6-NEXT: store i64 [[TMP2]], i64* [[TMP34]], align 8
|
|
// CHECK6-NEXT: [[TMP35:%.*]] = getelementptr inbounds [6 x i64], [6 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3
|
|
// CHECK6-NEXT: store i64 8, i64* [[TMP35]], align 8
|
|
// CHECK6-NEXT: [[TMP36:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
|
|
// CHECK6-NEXT: store i8* null, i8** [[TMP36]], align 8
|
|
// CHECK6-NEXT: [[TMP37:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
|
|
// CHECK6-NEXT: [[TMP38:%.*]] = bitcast i8** [[TMP37]] to i16**
|
|
// CHECK6-NEXT: store i16* [[VLA]], i16** [[TMP38]], align 8
|
|
// CHECK6-NEXT: [[TMP39:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
|
|
// CHECK6-NEXT: [[TMP40:%.*]] = bitcast i8** [[TMP39]] to i16**
|
|
// CHECK6-NEXT: store i16* [[VLA]], i16** [[TMP40]], align 8
|
|
// CHECK6-NEXT: [[TMP41:%.*]] = getelementptr inbounds [6 x i64], [6 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4
|
|
// CHECK6-NEXT: store i64 [[TMP12]], i64* [[TMP41]], align 8
|
|
// CHECK6-NEXT: [[TMP42:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4
|
|
// CHECK6-NEXT: store i8* null, i8** [[TMP42]], align 8
|
|
// CHECK6-NEXT: [[TMP43:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 5
|
|
// CHECK6-NEXT: [[TMP44:%.*]] = bitcast i8** [[TMP43]] to i64*
|
|
// CHECK6-NEXT: store i64 [[TMP9]], i64* [[TMP44]], align 8
|
|
// CHECK6-NEXT: [[TMP45:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 5
|
|
// CHECK6-NEXT: [[TMP46:%.*]] = bitcast i8** [[TMP45]] to i64*
|
|
// CHECK6-NEXT: store i64 [[TMP9]], i64* [[TMP46]], align 8
|
|
// CHECK6-NEXT: [[TMP47:%.*]] = getelementptr inbounds [6 x i64], [6 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 5
|
|
// CHECK6-NEXT: store i64 1, i64* [[TMP47]], align 8
|
|
// CHECK6-NEXT: [[TMP48:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 5
|
|
// CHECK6-NEXT: store i8* null, i8** [[TMP48]], align 8
|
|
// CHECK6-NEXT: [[TMP49:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK6-NEXT: [[TMP50:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK6-NEXT: [[TMP51:%.*]] = getelementptr inbounds [6 x i64], [6 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
|
|
// CHECK6-NEXT: [[TMP52:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
|
|
// CHECK6-NEXT: [[TOBOOL5:%.*]] = trunc i8 [[TMP52]] to i1
|
|
// CHECK6-NEXT: [[TMP53:%.*]] = select i1 [[TOBOOL5]], i32 0, i32 1
|
|
// CHECK6-NEXT: [[TMP54:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214.region_id, i32 6, i8** [[TMP49]], i8** [[TMP50]], i64* [[TMP51]], i64* getelementptr inbounds ([6 x i64], [6 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP53]])
|
|
// CHECK6-NEXT: [[TMP55:%.*]] = icmp ne i32 [[TMP54]], 0
|
|
// CHECK6-NEXT: br i1 [[TMP55]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
|
// CHECK6: omp_offload.failed:
|
|
// CHECK6-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214(%struct.S1* [[THIS1]], i64 [[TMP7]], i64 2, i64 [[TMP2]], i16* [[VLA]], i64 [[TMP9]]) #[[ATTR4]]
|
|
// CHECK6-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
|
// CHECK6: omp_offload.cont:
|
|
// CHECK6-NEXT: br label [[OMP_IF_END:%.*]]
|
|
// CHECK6: omp_if.else:
|
|
// CHECK6-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214(%struct.S1* [[THIS1]], i64 [[TMP7]], i64 2, i64 [[TMP2]], i16* [[VLA]], i64 [[TMP9]]) #[[ATTR4]]
|
|
// CHECK6-NEXT: br label [[OMP_IF_END]]
|
|
// CHECK6: omp_if.end:
|
|
// CHECK6-NEXT: [[TMP56:%.*]] = mul nsw i64 1, [[TMP2]]
|
|
// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP56]]
|
|
// CHECK6-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
|
|
// CHECK6-NEXT: [[TMP57:%.*]] = load i16, i16* [[ARRAYIDX6]], align 2
|
|
// CHECK6-NEXT: [[CONV7:%.*]] = sext i16 [[TMP57]] to i32
|
|
// CHECK6-NEXT: [[TMP58:%.*]] = load i32, i32* [[B]], align 4
|
|
// CHECK6-NEXT: [[ADD8:%.*]] = add nsw i32 [[CONV7]], [[TMP58]]
|
|
// CHECK6-NEXT: [[TMP59:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
|
|
// CHECK6-NEXT: call void @llvm.stackrestore(i8* [[TMP59]])
|
|
// CHECK6-NEXT: ret i32 [[ADD8]]
|
|
//
|
|
//
|
|
// CHECK6-LABEL: define {{[^@]+}}@_ZL7fstatici
|
|
// CHECK6-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
|
|
// CHECK6-NEXT: entry:
|
|
// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK6-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK6-NEXT: [[AA:%.*]] = alloca i16, align 2
|
|
// CHECK6-NEXT: [[AAA:%.*]] = alloca i8, align 1
|
|
// CHECK6-NEXT: [[B:%.*]] = alloca [10 x i32], align 4
|
|
// CHECK6-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK6-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK6-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK6-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8
|
|
// CHECK6-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8
|
|
// CHECK6-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8
|
|
// CHECK6-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK6-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK6-NEXT: store i16 0, i16* [[AA]], align 2
|
|
// CHECK6-NEXT: store i8 0, i8* [[AAA]], align 1
|
|
// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32*
|
|
// CHECK6-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4
|
|
// CHECK6-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
|
|
// CHECK6-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
|
|
// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
|
|
// CHECK6-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
|
|
// CHECK6-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
|
|
// CHECK6-NEXT: [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1
|
|
// CHECK6-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
|
|
// CHECK6-NEXT: store i8 [[TMP4]], i8* [[CONV2]], align 1
|
|
// CHECK6-NEXT: [[TMP5:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
|
|
// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK6-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50
|
|
// CHECK6-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
|
|
// CHECK6: omp_if.then:
|
|
// CHECK6-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK6-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64*
|
|
// CHECK6-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8
|
|
// CHECK6-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK6-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64*
|
|
// CHECK6-NEXT: store i64 [[TMP1]], i64* [[TMP10]], align 8
|
|
// CHECK6-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
|
|
// CHECK6-NEXT: store i8* null, i8** [[TMP11]], align 8
|
|
// CHECK6-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
|
|
// CHECK6-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64*
|
|
// CHECK6-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8
|
|
// CHECK6-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
|
|
// CHECK6-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64*
|
|
// CHECK6-NEXT: store i64 [[TMP3]], i64* [[TMP15]], align 8
|
|
// CHECK6-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
|
|
// CHECK6-NEXT: store i8* null, i8** [[TMP16]], align 8
|
|
// CHECK6-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
|
|
// CHECK6-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64*
|
|
// CHECK6-NEXT: store i64 [[TMP5]], i64* [[TMP18]], align 8
|
|
// CHECK6-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
|
|
// CHECK6-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64*
|
|
// CHECK6-NEXT: store i64 [[TMP5]], i64* [[TMP20]], align 8
|
|
// CHECK6-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
|
|
// CHECK6-NEXT: store i8* null, i8** [[TMP21]], align 8
|
|
// CHECK6-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
|
|
// CHECK6-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]**
|
|
// CHECK6-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 8
|
|
// CHECK6-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
|
|
// CHECK6-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]**
|
|
// CHECK6-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 8
|
|
// CHECK6-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
|
|
// CHECK6-NEXT: store i8* null, i8** [[TMP26]], align 8
|
|
// CHECK6-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK6-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK6-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
|
|
// CHECK6-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0
|
|
// CHECK6-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
|
// CHECK6: omp_offload.failed:
|
|
// CHECK6-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]]
|
|
// CHECK6-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
|
// CHECK6: omp_offload.cont:
|
|
// CHECK6-NEXT: br label [[OMP_IF_END:%.*]]
|
|
// CHECK6: omp_if.else:
|
|
// CHECK6-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]]
|
|
// CHECK6-NEXT: br label [[OMP_IF_END]]
|
|
// CHECK6: omp_if.end:
|
|
// CHECK6-NEXT: [[TMP31:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK6-NEXT: ret i32 [[TMP31]]
|
|
//
|
|
//
|
|
// CHECK6-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
|
|
// CHECK6-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat {
|
|
// CHECK6-NEXT: entry:
|
|
// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK6-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK6-NEXT: [[AA:%.*]] = alloca i16, align 2
|
|
// CHECK6-NEXT: [[B:%.*]] = alloca [10 x i32], align 4
|
|
// CHECK6-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK6-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK6-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8
|
|
// CHECK6-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8
|
|
// CHECK6-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8
|
|
// CHECK6-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK6-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK6-NEXT: store i16 0, i16* [[AA]], align 2
|
|
// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32*
|
|
// CHECK6-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4
|
|
// CHECK6-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
|
|
// CHECK6-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
|
|
// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
|
|
// CHECK6-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
|
|
// CHECK6-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
|
|
// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK6-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40
|
|
// CHECK6-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
|
|
// CHECK6: omp_if.then:
|
|
// CHECK6-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK6-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64*
|
|
// CHECK6-NEXT: store i64 [[TMP1]], i64* [[TMP6]], align 8
|
|
// CHECK6-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK6-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64*
|
|
// CHECK6-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8
|
|
// CHECK6-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
|
|
// CHECK6-NEXT: store i8* null, i8** [[TMP9]], align 8
|
|
// CHECK6-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
|
|
// CHECK6-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i64*
|
|
// CHECK6-NEXT: store i64 [[TMP3]], i64* [[TMP11]], align 8
|
|
// CHECK6-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
|
|
// CHECK6-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64*
|
|
// CHECK6-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8
|
|
// CHECK6-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
|
|
// CHECK6-NEXT: store i8* null, i8** [[TMP14]], align 8
|
|
// CHECK6-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
|
|
// CHECK6-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]**
|
|
// CHECK6-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 8
|
|
// CHECK6-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
|
|
// CHECK6-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]**
|
|
// CHECK6-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 8
|
|
// CHECK6-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
|
|
// CHECK6-NEXT: store i8* null, i8** [[TMP19]], align 8
|
|
// CHECK6-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK6-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK6-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.15, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.16, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
|
|
// CHECK6-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0
|
|
// CHECK6-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
|
// CHECK6: omp_offload.failed:
|
|
// CHECK6-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]]
|
|
// CHECK6-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
|
// CHECK6: omp_offload.cont:
|
|
// CHECK6-NEXT: br label [[OMP_IF_END:%.*]]
|
|
// CHECK6: omp_if.else:
|
|
// CHECK6-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]]
|
|
// CHECK6-NEXT: br label [[OMP_IF_END]]
|
|
// CHECK6: omp_if.end:
|
|
// CHECK6-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK6-NEXT: ret i32 [[TMP24]]
|
|
//
|
|
//
|
|
// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214
|
|
// CHECK6-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] {
|
|
// CHECK6-NEXT: entry:
|
|
// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
|
|
// CHECK6-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK6-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK6-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
|
|
// CHECK6-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8
|
|
// CHECK6-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK6-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK6-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK6-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
|
|
// CHECK6-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK6-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4
|
|
// CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]])
|
|
// CHECK6-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK6-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
|
|
// CHECK6-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
|
|
// CHECK6-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
|
|
// CHECK6-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8
|
|
// CHECK6-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
|
|
// CHECK6-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
|
|
// CHECK6-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
|
|
// CHECK6-NEXT: [[TMP3:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
|
|
// CHECK6-NEXT: [[TMP4:%.*]] = load i16*, i16** [[C_ADDR]], align 8
|
|
// CHECK6-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
|
|
// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV]], align 8
|
|
// CHECK6-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i32*
|
|
// CHECK6-NEXT: store i32 [[TMP5]], i32* [[CONV4]], align 4
|
|
// CHECK6-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8
|
|
// CHECK6-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV3]], align 8
|
|
// CHECK6-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP7]] to i1
|
|
// CHECK6-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
|
|
// CHECK6-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
|
|
// CHECK6-NEXT: store i8 [[FROMBOOL]], i8* [[CONV5]], align 1
|
|
// CHECK6-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
|
|
// CHECK6-NEXT: [[TMP9:%.*]] = load i8, i8* [[CONV3]], align 8
|
|
// CHECK6-NEXT: [[TOBOOL6:%.*]] = trunc i8 [[TMP9]] to i1
|
|
// CHECK6-NEXT: br i1 [[TOBOOL6]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
|
|
// CHECK6: omp_if.then:
|
|
// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP6]], i64 [[TMP2]], i64 [[TMP3]], i16* [[TMP4]], i64 [[TMP8]])
|
|
// CHECK6-NEXT: br label [[OMP_IF_END:%.*]]
|
|
// CHECK6: omp_if.else:
|
|
// CHECK6-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]])
|
|
// CHECK6-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
|
|
// CHECK6-NEXT: call void @.omp_outlined..9(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]], i64 [[TMP6]], i64 [[TMP2]], i64 [[TMP3]], i16* [[TMP4]], i64 [[TMP8]]) #[[ATTR4]]
|
|
// CHECK6-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]])
|
|
// CHECK6-NEXT: br label [[OMP_IF_END]]
|
|
// CHECK6: omp_if.end:
|
|
// CHECK6-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..9
|
|
// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] {
|
|
// CHECK6-NEXT: entry:
|
|
// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
|
|
// CHECK6-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK6-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK6-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
|
|
// CHECK6-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8
|
|
// CHECK6-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
|
|
// CHECK6-NEXT: [[TMP:%.*]] = alloca i64, align 8
|
|
// CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
|
|
// CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
|
|
// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
|
|
// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK6-NEXT: [[IT:%.*]] = alloca i64, align 8
|
|
// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK6-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK6-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
|
|
// CHECK6-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
|
|
// CHECK6-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
|
|
// CHECK6-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8
|
|
// CHECK6-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
|
|
// CHECK6-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
|
|
// CHECK6-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
|
|
// CHECK6-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
|
|
// CHECK6-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
|
|
// CHECK6-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
|
|
// CHECK6-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK6-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK6-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
|
|
// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK6-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV3]], align 8
|
|
// CHECK6-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1
|
|
// CHECK6-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
|
|
// CHECK6: omp_if.then:
|
|
// CHECK6-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4
|
|
// CHECK6-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
|
|
// CHECK6-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK6-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP7]], 3
|
|
// CHECK6-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK6: cond.true:
|
|
// CHECK6-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK6: cond.false:
|
|
// CHECK6-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK6-NEXT: br label [[COND_END]]
|
|
// CHECK6: cond.end:
|
|
// CHECK6-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ]
|
|
// CHECK6-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
|
|
// CHECK6-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK6-NEXT: store i64 [[TMP9]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK6: omp.inner.for.cond:
|
|
// CHECK6-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !38
|
|
// CHECK6-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !38
|
|
// CHECK6-NEXT: [[CMP4:%.*]] = icmp ule i64 [[TMP10]], [[TMP11]]
|
|
// CHECK6-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK6: omp.inner.for.body:
|
|
// CHECK6-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !38
|
|
// CHECK6-NEXT: [[MUL:%.*]] = mul i64 [[TMP12]], 400
|
|
// CHECK6-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]
|
|
// CHECK6-NEXT: store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !38
|
|
// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !38
|
|
// CHECK6-NEXT: [[CONV5:%.*]] = sitofp i32 [[TMP13]] to double
|
|
// CHECK6-NEXT: [[ADD:%.*]] = fadd double [[CONV5]], 1.500000e+00
|
|
// CHECK6-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
|
|
// CHECK6-NEXT: store double [[ADD]], double* [[A]], align 8, !nontemporal !39, !llvm.access.group !38
|
|
// CHECK6-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
|
|
// CHECK6-NEXT: [[TMP14:%.*]] = load double, double* [[A6]], align 8, !nontemporal !39, !llvm.access.group !38
|
|
// CHECK6-NEXT: [[INC:%.*]] = fadd double [[TMP14]], 1.000000e+00
|
|
// CHECK6-NEXT: store double [[INC]], double* [[A6]], align 8, !nontemporal !39, !llvm.access.group !38
|
|
// CHECK6-NEXT: [[CONV7:%.*]] = fptosi double [[INC]] to i16
|
|
// CHECK6-NEXT: [[TMP15:%.*]] = mul nsw i64 1, [[TMP2]]
|
|
// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP15]]
|
|
// CHECK6-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
|
|
// CHECK6-NEXT: store i16 [[CONV7]], i16* [[ARRAYIDX8]], align 2, !llvm.access.group !38
|
|
// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK6: omp.body.continue:
|
|
// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK6: omp.inner.for.inc:
|
|
// CHECK6-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !38
|
|
// CHECK6-NEXT: [[ADD9:%.*]] = add i64 [[TMP16]], 1
|
|
// CHECK6-NEXT: store i64 [[ADD9]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !38
|
|
// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP40:![0-9]+]]
|
|
// CHECK6: omp.inner.for.end:
|
|
// CHECK6-NEXT: br label [[OMP_IF_END:%.*]]
|
|
// CHECK6: omp_if.else:
|
|
// CHECK6-NEXT: [[TMP17:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK6-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP17]], align 4
|
|
// CHECK6-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP18]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
|
|
// CHECK6-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK6-NEXT: [[CMP10:%.*]] = icmp ugt i64 [[TMP19]], 3
|
|
// CHECK6-NEXT: br i1 [[CMP10]], label [[COND_TRUE11:%.*]], label [[COND_FALSE12:%.*]]
|
|
// CHECK6: cond.true11:
|
|
// CHECK6-NEXT: br label [[COND_END13:%.*]]
|
|
// CHECK6: cond.false12:
|
|
// CHECK6-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK6-NEXT: br label [[COND_END13]]
|
|
// CHECK6: cond.end13:
|
|
// CHECK6-NEXT: [[COND14:%.*]] = phi i64 [ 3, [[COND_TRUE11]] ], [ [[TMP20]], [[COND_FALSE12]] ]
|
|
// CHECK6-NEXT: store i64 [[COND14]], i64* [[DOTOMP_UB]], align 8
|
|
// CHECK6-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK6-NEXT: store i64 [[TMP21]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND15:%.*]]
|
|
// CHECK6: omp.inner.for.cond15:
|
|
// CHECK6-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK6-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK6-NEXT: [[CMP16:%.*]] = icmp ule i64 [[TMP22]], [[TMP23]]
|
|
// CHECK6-NEXT: br i1 [[CMP16]], label [[OMP_INNER_FOR_BODY17:%.*]], label [[OMP_INNER_FOR_END31:%.*]]
|
|
// CHECK6: omp.inner.for.body17:
|
|
// CHECK6-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK6-NEXT: [[MUL18:%.*]] = mul i64 [[TMP24]], 400
|
|
// CHECK6-NEXT: [[SUB19:%.*]] = sub i64 2000, [[MUL18]]
|
|
// CHECK6-NEXT: store i64 [[SUB19]], i64* [[IT]], align 8
|
|
// CHECK6-NEXT: [[TMP25:%.*]] = load i32, i32* [[CONV]], align 8
|
|
// CHECK6-NEXT: [[CONV20:%.*]] = sitofp i32 [[TMP25]] to double
|
|
// CHECK6-NEXT: [[ADD21:%.*]] = fadd double [[CONV20]], 1.500000e+00
|
|
// CHECK6-NEXT: [[A22:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
|
|
// CHECK6-NEXT: store double [[ADD21]], double* [[A22]], align 8
|
|
// CHECK6-NEXT: [[A23:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
|
|
// CHECK6-NEXT: [[TMP26:%.*]] = load double, double* [[A23]], align 8
|
|
// CHECK6-NEXT: [[INC24:%.*]] = fadd double [[TMP26]], 1.000000e+00
|
|
// CHECK6-NEXT: store double [[INC24]], double* [[A23]], align 8
|
|
// CHECK6-NEXT: [[CONV25:%.*]] = fptosi double [[INC24]] to i16
|
|
// CHECK6-NEXT: [[TMP27:%.*]] = mul nsw i64 1, [[TMP2]]
|
|
// CHECK6-NEXT: [[ARRAYIDX26:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP27]]
|
|
// CHECK6-NEXT: [[ARRAYIDX27:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX26]], i64 1
|
|
// CHECK6-NEXT: store i16 [[CONV25]], i16* [[ARRAYIDX27]], align 2
|
|
// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE28:%.*]]
|
|
// CHECK6: omp.body.continue28:
|
|
// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC29:%.*]]
|
|
// CHECK6: omp.inner.for.inc29:
|
|
// CHECK6-NEXT: [[TMP28:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK6-NEXT: [[ADD30:%.*]] = add i64 [[TMP28]], 1
|
|
// CHECK6-NEXT: store i64 [[ADD30]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND15]], !llvm.loop [[LOOP42:![0-9]+]]
|
|
// CHECK6: omp.inner.for.end31:
|
|
// CHECK6-NEXT: br label [[OMP_IF_END]]
|
|
// CHECK6: omp_if.end:
|
|
// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK6: omp.loop.exit:
|
|
// CHECK6-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK6-NEXT: [[TMP30:%.*]] = load i32, i32* [[TMP29]], align 4
|
|
// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP30]])
|
|
// CHECK6-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK6-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0
|
|
// CHECK6-NEXT: br i1 [[TMP32]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
|
|
// CHECK6: .omp.final.then:
|
|
// CHECK6-NEXT: store i64 400, i64* [[IT]], align 8
|
|
// CHECK6-NEXT: br label [[DOTOMP_FINAL_DONE]]
|
|
// CHECK6: .omp.final.done:
|
|
// CHECK6-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195
|
|
// CHECK6-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
|
|
// CHECK6-NEXT: entry:
|
|
// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK6-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK6-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK6-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
|
|
// CHECK6-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK6-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK6-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK6-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK6-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
|
|
// CHECK6-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
|
|
// CHECK6-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
|
|
// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
|
|
// CHECK6-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
|
|
// CHECK6-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
|
|
// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
|
|
// CHECK6-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
|
|
// CHECK6-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4
|
|
// CHECK6-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
|
|
// CHECK6-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
|
|
// CHECK6-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
|
|
// CHECK6-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2
|
|
// CHECK6-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
|
|
// CHECK6-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 8
|
|
// CHECK6-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
|
|
// CHECK6-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1
|
|
// CHECK6-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
|
|
// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]])
|
|
// CHECK6-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..11
|
|
// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] {
|
|
// CHECK6-NEXT: entry:
|
|
// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK6-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK6-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK6-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
|
|
// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK6-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK6-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
|
|
// CHECK6-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
|
|
// CHECK6-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
|
|
// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
|
|
// CHECK6-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
|
|
// CHECK6-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
|
|
// CHECK6-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178
|
|
// CHECK6-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
|
|
// CHECK6-NEXT: entry:
|
|
// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK6-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK6-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
|
|
// CHECK6-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK6-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK6-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK6-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
|
|
// CHECK6-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
|
|
// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
|
|
// CHECK6-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
|
|
// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
|
|
// CHECK6-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
|
|
// CHECK6-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4
|
|
// CHECK6-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
|
|
// CHECK6-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
|
|
// CHECK6-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
|
|
// CHECK6-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
|
|
// CHECK6-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
|
|
// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]])
|
|
// CHECK6-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..14
|
|
// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] {
|
|
// CHECK6-NEXT: entry:
|
|
// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK6-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK6-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
|
|
// CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
|
|
// CHECK6-NEXT: [[TMP:%.*]] = alloca i64, align 8
|
|
// CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
|
|
// CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
|
|
// CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
|
|
// CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK6-NEXT: [[I:%.*]] = alloca i64, align 8
|
|
// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK6-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK6-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
|
|
// CHECK6-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
|
|
// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
|
|
// CHECK6-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
|
|
// CHECK6-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK6-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK6-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
|
|
// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK6-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
|
|
// CHECK6-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
|
|
// CHECK6-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK6-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6
|
|
// CHECK6-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK6: cond.true:
|
|
// CHECK6-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK6: cond.false:
|
|
// CHECK6-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK6-NEXT: br label [[COND_END]]
|
|
// CHECK6: cond.end:
|
|
// CHECK6-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
|
|
// CHECK6-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
|
|
// CHECK6-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK6-NEXT: store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK6: omp.inner.for.cond:
|
|
// CHECK6-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !44
|
|
// CHECK6-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !44
|
|
// CHECK6-NEXT: [[CMP2:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]]
|
|
// CHECK6-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK6: omp.inner.for.body:
|
|
// CHECK6-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !44
|
|
// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3
|
|
// CHECK6-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
|
|
// CHECK6-NEXT: store i64 [[ADD]], i64* [[I]], align 8, !llvm.access.group !44
|
|
// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !44
|
|
// CHECK6-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1
|
|
// CHECK6-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 8, !llvm.access.group !44
|
|
// CHECK6-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 8, !llvm.access.group !44
|
|
// CHECK6-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32
|
|
// CHECK6-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
|
|
// CHECK6-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
|
|
// CHECK6-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 8, !llvm.access.group !44
|
|
// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
|
|
// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !44
|
|
// CHECK6-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1
|
|
// CHECK6-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !44
|
|
// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK6: omp.body.continue:
|
|
// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK6: omp.inner.for.inc:
|
|
// CHECK6-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !44
|
|
// CHECK6-NEXT: [[ADD8:%.*]] = add nsw i64 [[TMP12]], 1
|
|
// CHECK6-NEXT: store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !44
|
|
// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP45:![0-9]+]]
|
|
// CHECK6: omp.inner.for.end:
|
|
// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK6: omp.loop.exit:
|
|
// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
|
|
// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK6-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
|
|
// CHECK6-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
|
|
// CHECK6: .omp.final.then:
|
|
// CHECK6-NEXT: store i64 11, i64* [[I]], align 8
|
|
// CHECK6-NEXT: br label [[DOTOMP_FINAL_DONE]]
|
|
// CHECK6: .omp.final.done:
|
|
// CHECK6-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK6-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
|
|
// CHECK6-SAME: () #[[ATTR7:[0-9]+]] {
|
|
// CHECK6-NEXT: entry:
|
|
// CHECK6-NEXT: call void @__tgt_register_requires(i64 1)
|
|
// CHECK6-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK7-LABEL: define {{[^@]+}}@_Z7get_valv
|
|
// CHECK7-SAME: () #[[ATTR0:[0-9]+]] {
|
|
// CHECK7-NEXT: entry:
|
|
// CHECK7-NEXT: ret i64 0
|
|
//
|
|
//
|
|
// CHECK7-LABEL: define {{[^@]+}}@_Z3fooi
|
|
// CHECK7-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
|
|
// CHECK7-NEXT: entry:
|
|
// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK7-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK7-NEXT: [[AA:%.*]] = alloca i16, align 2
|
|
// CHECK7-NEXT: [[B:%.*]] = alloca [10 x float], align 4
|
|
// CHECK7-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4
|
|
// CHECK7-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4
|
|
// CHECK7-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8
|
|
// CHECK7-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4
|
|
// CHECK7-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4
|
|
// CHECK7-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 1
|
|
// CHECK7-NEXT: [[K:%.*]] = alloca i64, align 8
|
|
// CHECK7-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK7-NEXT: [[LIN:%.*]] = alloca i32, align 4
|
|
// CHECK7-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK7-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK7-NEXT: [[A_CASTED2:%.*]] = alloca i32, align 4
|
|
// CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4
|
|
// CHECK7-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4
|
|
// CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4
|
|
// CHECK7-NEXT: [[A_CASTED3:%.*]] = alloca i32, align 4
|
|
// CHECK7-NEXT: [[AA_CASTED4:%.*]] = alloca i32, align 4
|
|
// CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS6:%.*]] = alloca [2 x i8*], align 4
|
|
// CHECK7-NEXT: [[DOTOFFLOAD_PTRS7:%.*]] = alloca [2 x i8*], align 4
|
|
// CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS8:%.*]] = alloca [2 x i8*], align 4
|
|
// CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
|
// CHECK7-NEXT: [[A_CASTED11:%.*]] = alloca i32, align 4
|
|
// CHECK7-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS14:%.*]] = alloca [10 x i8*], align 4
|
|
// CHECK7-NEXT: [[DOTOFFLOAD_PTRS15:%.*]] = alloca [10 x i8*], align 4
|
|
// CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS16:%.*]] = alloca [10 x i8*], align 4
|
|
// CHECK7-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 4
|
|
// CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]])
|
|
// CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK7-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK7-NEXT: store i16 0, i16* [[AA]], align 2
|
|
// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK7-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave()
|
|
// CHECK7-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4
|
|
// CHECK7-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP1]], align 4
|
|
// CHECK7-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4
|
|
// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK7-NEXT: [[TMP4:%.*]] = mul nuw i32 5, [[TMP3]]
|
|
// CHECK7-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP4]], align 8
|
|
// CHECK7-NEXT: store i32 [[TMP3]], i32* [[__VLA_EXPR1]], align 4
|
|
// CHECK7-NEXT: [[TMP5:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 1, i32 20, i32 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1)
|
|
// CHECK7-NEXT: [[TMP6:%.*]] = bitcast i8* [[TMP5]] to %struct.kmp_task_t_with_privates*
|
|
// CHECK7-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP6]], i32 0, i32 0
|
|
// CHECK7-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i8* [[TMP5]])
|
|
// CHECK7-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv()
|
|
// CHECK7-NEXT: store i64 [[CALL]], i64* [[K]], align 8
|
|
// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK7-NEXT: store i32 [[TMP9]], i32* [[A_CASTED]], align 4
|
|
// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[A_CASTED]], align 4
|
|
// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101(i32 [[TMP10]], i64* [[K]]) #[[ATTR4:[0-9]+]]
|
|
// CHECK7-NEXT: store i32 12, i32* [[LIN]], align 4
|
|
// CHECK7-NEXT: [[TMP11:%.*]] = load i16, i16* [[AA]], align 2
|
|
// CHECK7-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
|
|
// CHECK7-NEXT: store i16 [[TMP11]], i16* [[CONV]], align 2
|
|
// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[AA_CASTED]], align 4
|
|
// CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[LIN]], align 4
|
|
// CHECK7-NEXT: store i32 [[TMP13]], i32* [[LIN_CASTED]], align 4
|
|
// CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[LIN_CASTED]], align 4
|
|
// CHECK7-NEXT: [[TMP15:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK7-NEXT: store i32 [[TMP15]], i32* [[A_CASTED2]], align 4
|
|
// CHECK7-NEXT: [[TMP16:%.*]] = load i32, i32* [[A_CASTED2]], align 4
|
|
// CHECK7-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK7-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32*
|
|
// CHECK7-NEXT: store i32 [[TMP12]], i32* [[TMP18]], align 4
|
|
// CHECK7-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK7-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32*
|
|
// CHECK7-NEXT: store i32 [[TMP12]], i32* [[TMP20]], align 4
|
|
// CHECK7-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
|
|
// CHECK7-NEXT: store i8* null, i8** [[TMP21]], align 4
|
|
// CHECK7-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
|
|
// CHECK7-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i32*
|
|
// CHECK7-NEXT: store i32 [[TMP14]], i32* [[TMP23]], align 4
|
|
// CHECK7-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
|
|
// CHECK7-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i32*
|
|
// CHECK7-NEXT: store i32 [[TMP14]], i32* [[TMP25]], align 4
|
|
// CHECK7-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
|
|
// CHECK7-NEXT: store i8* null, i8** [[TMP26]], align 4
|
|
// CHECK7-NEXT: [[TMP27:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
|
|
// CHECK7-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i32*
|
|
// CHECK7-NEXT: store i32 [[TMP16]], i32* [[TMP28]], align 4
|
|
// CHECK7-NEXT: [[TMP29:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
|
|
// CHECK7-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i32*
|
|
// CHECK7-NEXT: store i32 [[TMP16]], i32* [[TMP30]], align 4
|
|
// CHECK7-NEXT: [[TMP31:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
|
|
// CHECK7-NEXT: store i8* null, i8** [[TMP31]], align 4
|
|
// CHECK7-NEXT: [[TMP32:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK7-NEXT: [[TMP33:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK7-NEXT: [[TMP34:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108.region_id, i32 3, i8** [[TMP32]], i8** [[TMP33]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
|
|
// CHECK7-NEXT: [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 0
|
|
// CHECK7-NEXT: br i1 [[TMP35]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
|
// CHECK7: omp_offload.failed:
|
|
// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108(i32 [[TMP12]], i32 [[TMP14]], i32 [[TMP16]]) #[[ATTR4]]
|
|
// CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
|
// CHECK7: omp_offload.cont:
|
|
// CHECK7-NEXT: [[TMP36:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK7-NEXT: store i32 [[TMP36]], i32* [[A_CASTED3]], align 4
|
|
// CHECK7-NEXT: [[TMP37:%.*]] = load i32, i32* [[A_CASTED3]], align 4
|
|
// CHECK7-NEXT: [[TMP38:%.*]] = load i16, i16* [[AA]], align 2
|
|
// CHECK7-NEXT: [[CONV5:%.*]] = bitcast i32* [[AA_CASTED4]] to i16*
|
|
// CHECK7-NEXT: store i16 [[TMP38]], i16* [[CONV5]], align 2
|
|
// CHECK7-NEXT: [[TMP39:%.*]] = load i32, i32* [[AA_CASTED4]], align 4
|
|
// CHECK7-NEXT: [[TMP40:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP40]], 10
|
|
// CHECK7-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
|
|
// CHECK7: omp_if.then:
|
|
// CHECK7-NEXT: [[TMP41:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0
|
|
// CHECK7-NEXT: [[TMP42:%.*]] = bitcast i8** [[TMP41]] to i32*
|
|
// CHECK7-NEXT: store i32 [[TMP37]], i32* [[TMP42]], align 4
|
|
// CHECK7-NEXT: [[TMP43:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0
|
|
// CHECK7-NEXT: [[TMP44:%.*]] = bitcast i8** [[TMP43]] to i32*
|
|
// CHECK7-NEXT: store i32 [[TMP37]], i32* [[TMP44]], align 4
|
|
// CHECK7-NEXT: [[TMP45:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS8]], i32 0, i32 0
|
|
// CHECK7-NEXT: store i8* null, i8** [[TMP45]], align 4
|
|
// CHECK7-NEXT: [[TMP46:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 1
|
|
// CHECK7-NEXT: [[TMP47:%.*]] = bitcast i8** [[TMP46]] to i32*
|
|
// CHECK7-NEXT: store i32 [[TMP39]], i32* [[TMP47]], align 4
|
|
// CHECK7-NEXT: [[TMP48:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 1
|
|
// CHECK7-NEXT: [[TMP49:%.*]] = bitcast i8** [[TMP48]] to i32*
|
|
// CHECK7-NEXT: store i32 [[TMP39]], i32* [[TMP49]], align 4
|
|
// CHECK7-NEXT: [[TMP50:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS8]], i32 0, i32 1
|
|
// CHECK7-NEXT: store i8* null, i8** [[TMP50]], align 4
|
|
// CHECK7-NEXT: [[TMP51:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0
|
|
// CHECK7-NEXT: [[TMP52:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0
|
|
// CHECK7-NEXT: [[TMP53:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116.region_id, i32 2, i8** [[TMP51]], i8** [[TMP52]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
|
|
// CHECK7-NEXT: [[TMP54:%.*]] = icmp ne i32 [[TMP53]], 0
|
|
// CHECK7-NEXT: br i1 [[TMP54]], label [[OMP_OFFLOAD_FAILED9:%.*]], label [[OMP_OFFLOAD_CONT10:%.*]]
|
|
// CHECK7: omp_offload.failed9:
|
|
// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116(i32 [[TMP37]], i32 [[TMP39]]) #[[ATTR4]]
|
|
// CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT10]]
|
|
// CHECK7: omp_offload.cont10:
|
|
// CHECK7-NEXT: br label [[OMP_IF_END:%.*]]
|
|
// CHECK7: omp_if.else:
|
|
// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116(i32 [[TMP37]], i32 [[TMP39]]) #[[ATTR4]]
|
|
// CHECK7-NEXT: br label [[OMP_IF_END]]
|
|
// CHECK7: omp_if.end:
|
|
// CHECK7-NEXT: [[TMP55:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK7-NEXT: store i32 [[TMP55]], i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK7-NEXT: [[TMP56:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK7-NEXT: store i32 [[TMP56]], i32* [[A_CASTED11]], align 4
|
|
// CHECK7-NEXT: [[TMP57:%.*]] = load i32, i32* [[A_CASTED11]], align 4
|
|
// CHECK7-NEXT: [[TMP58:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK7-NEXT: store i32 [[TMP58]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
|
|
// CHECK7-NEXT: [[TMP59:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
|
|
// CHECK7-NEXT: [[TMP60:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK7-NEXT: [[CMP12:%.*]] = icmp sgt i32 [[TMP60]], 20
|
|
// CHECK7-NEXT: br i1 [[CMP12]], label [[OMP_IF_THEN13:%.*]], label [[OMP_IF_ELSE19:%.*]]
|
|
// CHECK7: omp_if.then13:
|
|
// CHECK7-NEXT: [[TMP61:%.*]] = mul nuw i32 [[TMP1]], 4
|
|
// CHECK7-NEXT: [[TMP62:%.*]] = sext i32 [[TMP61]] to i64
|
|
// CHECK7-NEXT: [[TMP63:%.*]] = mul nuw i32 5, [[TMP3]]
|
|
// CHECK7-NEXT: [[TMP64:%.*]] = mul nuw i32 [[TMP63]], 8
|
|
// CHECK7-NEXT: [[TMP65:%.*]] = sext i32 [[TMP64]] to i64
|
|
// CHECK7-NEXT: [[TMP66:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 0
|
|
// CHECK7-NEXT: [[TMP67:%.*]] = bitcast i8** [[TMP66]] to i32*
|
|
// CHECK7-NEXT: store i32 [[TMP57]], i32* [[TMP67]], align 4
|
|
// CHECK7-NEXT: [[TMP68:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 0
|
|
// CHECK7-NEXT: [[TMP69:%.*]] = bitcast i8** [[TMP68]] to i32*
|
|
// CHECK7-NEXT: store i32 [[TMP57]], i32* [[TMP69]], align 4
|
|
// CHECK7-NEXT: [[TMP70:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
|
|
// CHECK7-NEXT: store i64 4, i64* [[TMP70]], align 4
|
|
// CHECK7-NEXT: [[TMP71:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 0
|
|
// CHECK7-NEXT: store i8* null, i8** [[TMP71]], align 4
|
|
// CHECK7-NEXT: [[TMP72:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 1
|
|
// CHECK7-NEXT: [[TMP73:%.*]] = bitcast i8** [[TMP72]] to [10 x float]**
|
|
// CHECK7-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP73]], align 4
|
|
// CHECK7-NEXT: [[TMP74:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 1
|
|
// CHECK7-NEXT: [[TMP75:%.*]] = bitcast i8** [[TMP74]] to [10 x float]**
|
|
// CHECK7-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP75]], align 4
|
|
// CHECK7-NEXT: [[TMP76:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1
|
|
// CHECK7-NEXT: store i64 40, i64* [[TMP76]], align 4
|
|
// CHECK7-NEXT: [[TMP77:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 1
|
|
// CHECK7-NEXT: store i8* null, i8** [[TMP77]], align 4
|
|
// CHECK7-NEXT: [[TMP78:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 2
|
|
// CHECK7-NEXT: [[TMP79:%.*]] = bitcast i8** [[TMP78]] to i32*
|
|
// CHECK7-NEXT: store i32 [[TMP1]], i32* [[TMP79]], align 4
|
|
// CHECK7-NEXT: [[TMP80:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 2
|
|
// CHECK7-NEXT: [[TMP81:%.*]] = bitcast i8** [[TMP80]] to i32*
|
|
// CHECK7-NEXT: store i32 [[TMP1]], i32* [[TMP81]], align 4
|
|
// CHECK7-NEXT: [[TMP82:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2
|
|
// CHECK7-NEXT: store i64 4, i64* [[TMP82]], align 4
|
|
// CHECK7-NEXT: [[TMP83:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 2
|
|
// CHECK7-NEXT: store i8* null, i8** [[TMP83]], align 4
|
|
// CHECK7-NEXT: [[TMP84:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 3
|
|
// CHECK7-NEXT: [[TMP85:%.*]] = bitcast i8** [[TMP84]] to float**
|
|
// CHECK7-NEXT: store float* [[VLA]], float** [[TMP85]], align 4
|
|
// CHECK7-NEXT: [[TMP86:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 3
|
|
// CHECK7-NEXT: [[TMP87:%.*]] = bitcast i8** [[TMP86]] to float**
|
|
// CHECK7-NEXT: store float* [[VLA]], float** [[TMP87]], align 4
|
|
// CHECK7-NEXT: [[TMP88:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3
|
|
// CHECK7-NEXT: store i64 [[TMP62]], i64* [[TMP88]], align 4
|
|
// CHECK7-NEXT: [[TMP89:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 3
|
|
// CHECK7-NEXT: store i8* null, i8** [[TMP89]], align 4
|
|
// CHECK7-NEXT: [[TMP90:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 4
|
|
// CHECK7-NEXT: [[TMP91:%.*]] = bitcast i8** [[TMP90]] to [5 x [10 x double]]**
|
|
// CHECK7-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP91]], align 4
|
|
// CHECK7-NEXT: [[TMP92:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 4
|
|
// CHECK7-NEXT: [[TMP93:%.*]] = bitcast i8** [[TMP92]] to [5 x [10 x double]]**
|
|
// CHECK7-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP93]], align 4
|
|
// CHECK7-NEXT: [[TMP94:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4
|
|
// CHECK7-NEXT: store i64 400, i64* [[TMP94]], align 4
|
|
// CHECK7-NEXT: [[TMP95:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 4
|
|
// CHECK7-NEXT: store i8* null, i8** [[TMP95]], align 4
|
|
// CHECK7-NEXT: [[TMP96:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 5
|
|
// CHECK7-NEXT: [[TMP97:%.*]] = bitcast i8** [[TMP96]] to i32*
|
|
// CHECK7-NEXT: store i32 5, i32* [[TMP97]], align 4
|
|
// CHECK7-NEXT: [[TMP98:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 5
|
|
// CHECK7-NEXT: [[TMP99:%.*]] = bitcast i8** [[TMP98]] to i32*
|
|
// CHECK7-NEXT: store i32 5, i32* [[TMP99]], align 4
|
|
// CHECK7-NEXT: [[TMP100:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 5
|
|
// CHECK7-NEXT: store i64 4, i64* [[TMP100]], align 4
|
|
// CHECK7-NEXT: [[TMP101:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 5
|
|
// CHECK7-NEXT: store i8* null, i8** [[TMP101]], align 4
|
|
// CHECK7-NEXT: [[TMP102:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 6
|
|
// CHECK7-NEXT: [[TMP103:%.*]] = bitcast i8** [[TMP102]] to i32*
|
|
// CHECK7-NEXT: store i32 [[TMP3]], i32* [[TMP103]], align 4
|
|
// CHECK7-NEXT: [[TMP104:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 6
|
|
// CHECK7-NEXT: [[TMP105:%.*]] = bitcast i8** [[TMP104]] to i32*
|
|
// CHECK7-NEXT: store i32 [[TMP3]], i32* [[TMP105]], align 4
|
|
// CHECK7-NEXT: [[TMP106:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 6
|
|
// CHECK7-NEXT: store i64 4, i64* [[TMP106]], align 4
|
|
// CHECK7-NEXT: [[TMP107:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 6
|
|
// CHECK7-NEXT: store i8* null, i8** [[TMP107]], align 4
|
|
// CHECK7-NEXT: [[TMP108:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 7
|
|
// CHECK7-NEXT: [[TMP109:%.*]] = bitcast i8** [[TMP108]] to double**
|
|
// CHECK7-NEXT: store double* [[VLA1]], double** [[TMP109]], align 4
|
|
// CHECK7-NEXT: [[TMP110:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 7
|
|
// CHECK7-NEXT: [[TMP111:%.*]] = bitcast i8** [[TMP110]] to double**
|
|
// CHECK7-NEXT: store double* [[VLA1]], double** [[TMP111]], align 4
|
|
// CHECK7-NEXT: [[TMP112:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7
|
|
// CHECK7-NEXT: store i64 [[TMP65]], i64* [[TMP112]], align 4
|
|
// CHECK7-NEXT: [[TMP113:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 7
|
|
// CHECK7-NEXT: store i8* null, i8** [[TMP113]], align 4
|
|
// CHECK7-NEXT: [[TMP114:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 8
|
|
// CHECK7-NEXT: [[TMP115:%.*]] = bitcast i8** [[TMP114]] to %struct.TT**
|
|
// CHECK7-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP115]], align 4
|
|
// CHECK7-NEXT: [[TMP116:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 8
|
|
// CHECK7-NEXT: [[TMP117:%.*]] = bitcast i8** [[TMP116]] to %struct.TT**
|
|
// CHECK7-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP117]], align 4
|
|
// CHECK7-NEXT: [[TMP118:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 8
|
|
// CHECK7-NEXT: store i64 12, i64* [[TMP118]], align 4
|
|
// CHECK7-NEXT: [[TMP119:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 8
|
|
// CHECK7-NEXT: store i8* null, i8** [[TMP119]], align 4
|
|
// CHECK7-NEXT: [[TMP120:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 9
|
|
// CHECK7-NEXT: [[TMP121:%.*]] = bitcast i8** [[TMP120]] to i32*
|
|
// CHECK7-NEXT: store i32 [[TMP59]], i32* [[TMP121]], align 4
|
|
// CHECK7-NEXT: [[TMP122:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 9
|
|
// CHECK7-NEXT: [[TMP123:%.*]] = bitcast i8** [[TMP122]] to i32*
|
|
// CHECK7-NEXT: store i32 [[TMP59]], i32* [[TMP123]], align 4
|
|
// CHECK7-NEXT: [[TMP124:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 9
|
|
// CHECK7-NEXT: store i64 4, i64* [[TMP124]], align 4
|
|
// CHECK7-NEXT: [[TMP125:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 9
|
|
// CHECK7-NEXT: store i8* null, i8** [[TMP125]], align 4
|
|
// CHECK7-NEXT: [[TMP126:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 0
|
|
// CHECK7-NEXT: [[TMP127:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 0
|
|
// CHECK7-NEXT: [[TMP128:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
|
|
// CHECK7-NEXT: [[TMP129:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140.region_id, i32 10, i8** [[TMP126]], i8** [[TMP127]], i64* [[TMP128]], i64* getelementptr inbounds ([10 x i64], [10 x i64]* @.offload_maptypes.8, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
|
|
// CHECK7-NEXT: [[TMP130:%.*]] = icmp ne i32 [[TMP129]], 0
|
|
// CHECK7-NEXT: br i1 [[TMP130]], label [[OMP_OFFLOAD_FAILED17:%.*]], label [[OMP_OFFLOAD_CONT18:%.*]]
|
|
// CHECK7: omp_offload.failed17:
|
|
// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140(i32 [[TMP57]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]], i32 [[TMP59]]) #[[ATTR4]]
|
|
// CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT18]]
|
|
// CHECK7: omp_offload.cont18:
|
|
// CHECK7-NEXT: br label [[OMP_IF_END20:%.*]]
|
|
// CHECK7: omp_if.else19:
|
|
// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140(i32 [[TMP57]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]], i32 [[TMP59]]) #[[ATTR4]]
|
|
// CHECK7-NEXT: br label [[OMP_IF_END20]]
|
|
// CHECK7: omp_if.end20:
|
|
// CHECK7-NEXT: [[TMP131:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK7-NEXT: [[TMP132:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
|
|
// CHECK7-NEXT: call void @llvm.stackrestore(i8* [[TMP132]])
|
|
// CHECK7-NEXT: ret i32 [[TMP131]]
|
|
//
|
|
//
|
|
// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96
|
|
// CHECK7-SAME: () #[[ATTR2:[0-9]+]] {
|
|
// CHECK7-NEXT: entry:
|
|
// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
|
|
// CHECK7-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined.
|
|
// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] {
|
|
// CHECK7-NEXT: entry:
|
|
// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4
|
|
// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK7-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK7-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
|
|
// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
|
|
// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5
|
|
// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK7: cond.true:
|
|
// CHECK7-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK7: cond.false:
|
|
// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK7-NEXT: br label [[COND_END]]
|
|
// CHECK7: cond.end:
|
|
// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
|
|
// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK7-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK7: omp.inner.for.cond:
|
|
// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
|
|
// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !11
|
|
// CHECK7-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
|
|
// CHECK7-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK7: omp.inner.for.body:
|
|
// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
|
|
// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5
|
|
// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]]
|
|
// CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11
|
|
// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK7: omp.body.continue:
|
|
// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK7: omp.inner.for.inc:
|
|
// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
|
|
// CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
|
|
// CHECK7-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
|
|
// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]
|
|
// CHECK7: omp.inner.for.end:
|
|
// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK7: omp.loop.exit:
|
|
// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
|
|
// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK7-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0
|
|
// CHECK7-NEXT: br i1 [[TMP10]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
|
|
// CHECK7: .omp.final.then:
|
|
// CHECK7-NEXT: store i32 33, i32* [[I]], align 4
|
|
// CHECK7-NEXT: br label [[DOTOMP_FINAL_DONE]]
|
|
// CHECK7: .omp.final.done:
|
|
// CHECK7-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK7-LABEL: define {{[^@]+}}@.omp_task_entry.
|
|
// CHECK7-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] {
|
|
// CHECK7-NEXT: entry:
|
|
// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
|
|
// CHECK7-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 4
|
|
// CHECK7-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 4
|
|
// CHECK7-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 4
|
|
// CHECK7-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 4
|
|
// CHECK7-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 4
|
|
// CHECK7-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4
|
|
// CHECK7-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 4
|
|
// CHECK7-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4
|
|
// CHECK7-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4
|
|
// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4
|
|
// CHECK7-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4
|
|
// CHECK7-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
|
|
// CHECK7-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
|
|
// CHECK7-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0
|
|
// CHECK7-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 4
|
|
// CHECK7-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon*
|
|
// CHECK7-NEXT: [[TMP9:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8*
|
|
// CHECK7-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META17:![0-9]+]])
|
|
// CHECK7-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]])
|
|
// CHECK7-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META22:![0-9]+]])
|
|
// CHECK7-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META24:![0-9]+]])
|
|
// CHECK7-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !26
|
|
// CHECK7-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 4, !noalias !26
|
|
// CHECK7-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !26
|
|
// CHECK7-NEXT: store void (i8*, ...)* null, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !26
|
|
// CHECK7-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 4, !noalias !26
|
|
// CHECK7-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !26
|
|
// CHECK7-NEXT: [[TMP10:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !26
|
|
// CHECK7-NEXT: [[TMP11:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 0, i32 0, i8* null, i32 0, i8* null) #[[ATTR4]]
|
|
// CHECK7-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
|
|
// CHECK7-NEXT: br i1 [[TMP12]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]]
|
|
// CHECK7: omp_offload.failed.i:
|
|
// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96() #[[ATTR4]]
|
|
// CHECK7-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]]
|
|
// CHECK7: .omp_outlined..1.exit:
|
|
// CHECK7-NEXT: ret i32 0
|
|
//
|
|
//
|
|
// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101
|
|
// CHECK7-SAME: (i32 [[A:%.*]], i64* nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR3]] {
|
|
// CHECK7-NEXT: entry:
|
|
// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK7-NEXT: [[K_ADDR:%.*]] = alloca i64*, align 4
|
|
// CHECK7-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK7-NEXT: store i64* [[K]], i64** [[K_ADDR]], align 4
|
|
// CHECK7-NEXT: [[TMP0:%.*]] = load i64*, i64** [[K_ADDR]], align 4
|
|
// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK7-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
|
|
// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
|
|
// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i64*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP2]], i64* [[TMP0]])
|
|
// CHECK7-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..2
|
|
// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i64* nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR3]] {
|
|
// CHECK7-NEXT: entry:
|
|
// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK7-NEXT: [[K_ADDR:%.*]] = alloca i64*, align 4
|
|
// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK7-NEXT: [[DOTLINEAR_START:%.*]] = alloca i64, align 8
|
|
// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4
|
|
// CHECK7-NEXT: [[K1:%.*]] = alloca i64, align 8
|
|
// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK7-NEXT: store i64* [[K]], i64** [[K_ADDR]], align 4
|
|
// CHECK7-NEXT: [[TMP0:%.*]] = load i64*, i64** [[K_ADDR]], align 4
|
|
// CHECK7-NEXT: [[TMP1:%.*]] = load i64, i64* [[TMP0]], align 8
|
|
// CHECK7-NEXT: store i64 [[TMP1]], i64* [[DOTLINEAR_START]], align 8
|
|
// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK7-NEXT: store i32 8, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK7-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
|
|
// CHECK7-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP3]])
|
|
// CHECK7-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 1073741859, i32 0, i32 8, i32 1, i32 1)
|
|
// CHECK7-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
|
|
// CHECK7: omp.dispatch.cond:
|
|
// CHECK7-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
|
|
// CHECK7-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP4]], 0
|
|
// CHECK7-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
|
|
// CHECK7: omp.dispatch.body:
|
|
// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK7-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK7: omp.inner.for.cond:
|
|
// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27
|
|
// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !27
|
|
// CHECK7-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
|
|
// CHECK7-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK7: omp.inner.for.body:
|
|
// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27
|
|
// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
|
|
// CHECK7-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL]]
|
|
// CHECK7-NEXT: store i32 [[SUB]], i32* [[I]], align 4, !llvm.access.group !27
|
|
// CHECK7-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8, !llvm.access.group !27
|
|
// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27
|
|
// CHECK7-NEXT: [[MUL2:%.*]] = mul nsw i32 [[TMP10]], 3
|
|
// CHECK7-NEXT: [[CONV:%.*]] = sext i32 [[MUL2]] to i64
|
|
// CHECK7-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP9]], [[CONV]]
|
|
// CHECK7-NEXT: store i64 [[ADD]], i64* [[K1]], align 8, !llvm.access.group !27
|
|
// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !27
|
|
// CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP11]], 1
|
|
// CHECK7-NEXT: store i32 [[ADD3]], i32* [[A_ADDR]], align 4, !llvm.access.group !27
|
|
// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK7: omp.body.continue:
|
|
// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK7: omp.inner.for.inc:
|
|
// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27
|
|
// CHECK7-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1
|
|
// CHECK7-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27
|
|
// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]]
|
|
// CHECK7: omp.inner.for.end:
|
|
// CHECK7-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
|
|
// CHECK7: omp.dispatch.inc:
|
|
// CHECK7-NEXT: br label [[OMP_DISPATCH_COND]]
|
|
// CHECK7: omp.dispatch.end:
|
|
// CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK7-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
|
|
// CHECK7-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
|
|
// CHECK7: .omp.final.then:
|
|
// CHECK7-NEXT: store i32 1, i32* [[I]], align 4
|
|
// CHECK7-NEXT: br label [[DOTOMP_FINAL_DONE]]
|
|
// CHECK7: .omp.final.done:
|
|
// CHECK7-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK7-NEXT: [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0
|
|
// CHECK7-NEXT: br i1 [[TMP16]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
|
|
// CHECK7: .omp.linear.pu:
|
|
// CHECK7-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8
|
|
// CHECK7-NEXT: [[ADD5:%.*]] = add nsw i64 [[TMP17]], 27
|
|
// CHECK7-NEXT: store i64 [[ADD5]], i64* [[TMP0]], align 8
|
|
// CHECK7-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]]
|
|
// CHECK7: .omp.linear.pu.done:
|
|
// CHECK7-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108
|
|
// CHECK7-SAME: (i32 [[AA:%.*]], i32 [[LIN:%.*]], i32 [[A:%.*]]) #[[ATTR2]] {
|
|
// CHECK7-NEXT: entry:
|
|
// CHECK7-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK7-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK7-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK7-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK7-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK7-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
|
|
// CHECK7-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4
|
|
// CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK7-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
|
|
// CHECK7-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
|
|
// CHECK7-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
|
|
// CHECK7-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
|
|
// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
|
|
// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[LIN_ADDR]], align 4
|
|
// CHECK7-NEXT: store i32 [[TMP2]], i32* [[LIN_CASTED]], align 4
|
|
// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[LIN_CASTED]], align 4
|
|
// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK7-NEXT: store i32 [[TMP4]], i32* [[A_CASTED]], align 4
|
|
// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[A_CASTED]], align 4
|
|
// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]])
|
|
// CHECK7-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..3
|
|
// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]], i32 [[LIN:%.*]], i32 [[A:%.*]]) #[[ATTR3]] {
|
|
// CHECK7-NEXT: entry:
|
|
// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK7-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK7-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
|
|
// CHECK7-NEXT: [[TMP:%.*]] = alloca i64, align 4
|
|
// CHECK7-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4
|
|
// CHECK7-NEXT: [[DOTLINEAR_START1:%.*]] = alloca i32, align 4
|
|
// CHECK7-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8
|
|
// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
|
|
// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
|
|
// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
|
|
// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK7-NEXT: [[IT:%.*]] = alloca i64, align 8
|
|
// CHECK7-NEXT: [[LIN2:%.*]] = alloca i32, align 4
|
|
// CHECK7-NEXT: [[A3:%.*]] = alloca i32, align 4
|
|
// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK7-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
|
|
// CHECK7-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4
|
|
// CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK7-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
|
|
// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[LIN_ADDR]], align 4
|
|
// CHECK7-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4
|
|
// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK7-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START1]], align 4
|
|
// CHECK7-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv()
|
|
// CHECK7-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8
|
|
// CHECK7-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK7-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK7-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
|
|
// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK7-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
|
|
// CHECK7-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3]], i32 [[TMP3]])
|
|
// CHECK7-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
|
|
// CHECK7-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK7-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3
|
|
// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK7: cond.true:
|
|
// CHECK7-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK7: cond.false:
|
|
// CHECK7-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK7-NEXT: br label [[COND_END]]
|
|
// CHECK7: cond.end:
|
|
// CHECK7-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
|
|
// CHECK7-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
|
|
// CHECK7-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK7-NEXT: store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK7: omp.inner.for.cond:
|
|
// CHECK7-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !30
|
|
// CHECK7-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !30
|
|
// CHECK7-NEXT: [[CMP4:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]]
|
|
// CHECK7-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK7: omp.inner.for.body:
|
|
// CHECK7-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !30
|
|
// CHECK7-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400
|
|
// CHECK7-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]
|
|
// CHECK7-NEXT: store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !30
|
|
// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4, !llvm.access.group !30
|
|
// CHECK7-NEXT: [[CONV5:%.*]] = sext i32 [[TMP10]] to i64
|
|
// CHECK7-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !30
|
|
// CHECK7-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !30
|
|
// CHECK7-NEXT: [[MUL6:%.*]] = mul i64 [[TMP11]], [[TMP12]]
|
|
// CHECK7-NEXT: [[ADD:%.*]] = add i64 [[CONV5]], [[MUL6]]
|
|
// CHECK7-NEXT: [[CONV7:%.*]] = trunc i64 [[ADD]] to i32
|
|
// CHECK7-NEXT: store i32 [[CONV7]], i32* [[LIN2]], align 4, !llvm.access.group !30
|
|
// CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START1]], align 4, !llvm.access.group !30
|
|
// CHECK7-NEXT: [[CONV8:%.*]] = sext i32 [[TMP13]] to i64
|
|
// CHECK7-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !30
|
|
// CHECK7-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !30
|
|
// CHECK7-NEXT: [[MUL9:%.*]] = mul i64 [[TMP14]], [[TMP15]]
|
|
// CHECK7-NEXT: [[ADD10:%.*]] = add i64 [[CONV8]], [[MUL9]]
|
|
// CHECK7-NEXT: [[CONV11:%.*]] = trunc i64 [[ADD10]] to i32
|
|
// CHECK7-NEXT: store i32 [[CONV11]], i32* [[A3]], align 4, !llvm.access.group !30
|
|
// CHECK7-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !30
|
|
// CHECK7-NEXT: [[CONV12:%.*]] = sext i16 [[TMP16]] to i32
|
|
// CHECK7-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1
|
|
// CHECK7-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16
|
|
// CHECK7-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 4, !llvm.access.group !30
|
|
// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK7: omp.body.continue:
|
|
// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK7: omp.inner.for.inc:
|
|
// CHECK7-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !30
|
|
// CHECK7-NEXT: [[ADD15:%.*]] = add i64 [[TMP17]], 1
|
|
// CHECK7-NEXT: store i64 [[ADD15]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !30
|
|
// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP31:![0-9]+]]
|
|
// CHECK7: omp.inner.for.end:
|
|
// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK7: omp.loop.exit:
|
|
// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
|
|
// CHECK7-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK7-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
|
|
// CHECK7-NEXT: br i1 [[TMP19]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
|
|
// CHECK7: .omp.final.then:
|
|
// CHECK7-NEXT: store i64 400, i64* [[IT]], align 8
|
|
// CHECK7-NEXT: br label [[DOTOMP_FINAL_DONE]]
|
|
// CHECK7: .omp.final.done:
|
|
// CHECK7-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK7-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0
|
|
// CHECK7-NEXT: br i1 [[TMP21]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
|
|
// CHECK7: .omp.linear.pu:
|
|
// CHECK7-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4
|
|
// CHECK7-NEXT: [[CONV16:%.*]] = sext i32 [[TMP22]] to i64
|
|
// CHECK7-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
|
|
// CHECK7-NEXT: [[MUL17:%.*]] = mul i64 4, [[TMP23]]
|
|
// CHECK7-NEXT: [[ADD18:%.*]] = add i64 [[CONV16]], [[MUL17]]
|
|
// CHECK7-NEXT: [[CONV19:%.*]] = trunc i64 [[ADD18]] to i32
|
|
// CHECK7-NEXT: store i32 [[CONV19]], i32* [[LIN_ADDR]], align 4
|
|
// CHECK7-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTLINEAR_START1]], align 4
|
|
// CHECK7-NEXT: [[CONV20:%.*]] = sext i32 [[TMP24]] to i64
|
|
// CHECK7-NEXT: [[TMP25:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
|
|
// CHECK7-NEXT: [[MUL21:%.*]] = mul i64 4, [[TMP25]]
|
|
// CHECK7-NEXT: [[ADD22:%.*]] = add i64 [[CONV20]], [[MUL21]]
|
|
// CHECK7-NEXT: [[CONV23:%.*]] = trunc i64 [[ADD22]] to i32
|
|
// CHECK7-NEXT: store i32 [[CONV23]], i32* [[A_ADDR]], align 4
|
|
// CHECK7-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]]
|
|
// CHECK7: .omp.linear.pu.done:
|
|
// CHECK7-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116
|
|
// CHECK7-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] {
|
|
// CHECK7-NEXT: entry:
|
|
// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK7-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK7-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK7-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK7-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
|
|
// CHECK7-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
|
|
// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK7-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
|
|
// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
|
|
// CHECK7-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
|
|
// CHECK7-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
|
|
// CHECK7-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
|
|
// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
|
|
// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]])
|
|
// CHECK7-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..4
|
|
// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR3]] {
|
|
// CHECK7-NEXT: entry:
|
|
// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK7-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK7-NEXT: [[TMP:%.*]] = alloca i16, align 2
|
|
// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK7-NEXT: [[IT:%.*]] = alloca i16, align 2
|
|
// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK7-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
|
|
// CHECK7-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
|
|
// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK7-NEXT: store i32 3, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK7-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
|
|
// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
|
|
// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3
|
|
// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK7: cond.true:
|
|
// CHECK7-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK7: cond.false:
|
|
// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK7-NEXT: br label [[COND_END]]
|
|
// CHECK7: cond.end:
|
|
// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
|
|
// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK7-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK7: omp.inner.for.cond:
|
|
// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33
|
|
// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !33
|
|
// CHECK7-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
|
|
// CHECK7-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK7: omp.inner.for.body:
|
|
// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33
|
|
// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4
|
|
// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]]
|
|
// CHECK7-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
|
|
// CHECK7-NEXT: store i16 [[CONV2]], i16* [[IT]], align 2, !llvm.access.group !33
|
|
// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !33
|
|
// CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1
|
|
// CHECK7-NEXT: store i32 [[ADD3]], i32* [[A_ADDR]], align 4, !llvm.access.group !33
|
|
// CHECK7-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !33
|
|
// CHECK7-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32
|
|
// CHECK7-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
|
|
// CHECK7-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
|
|
// CHECK7-NEXT: store i16 [[CONV6]], i16* [[CONV]], align 4, !llvm.access.group !33
|
|
// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK7: omp.body.continue:
|
|
// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK7: omp.inner.for.inc:
|
|
// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33
|
|
// CHECK7-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1
|
|
// CHECK7-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33
|
|
// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP34:![0-9]+]]
|
|
// CHECK7: omp.inner.for.end:
|
|
// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK7: omp.loop.exit:
|
|
// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
|
|
// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK7-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
|
|
// CHECK7-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
|
|
// CHECK7: .omp.final.then:
|
|
// CHECK7-NEXT: store i16 22, i16* [[IT]], align 2
|
|
// CHECK7-NEXT: br label [[DOTOMP_FINAL_DONE]]
|
|
// CHECK7: .omp.final.done:
|
|
// CHECK7-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140
|
|
// CHECK7-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] {
|
|
// CHECK7-NEXT: entry:
|
|
// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK7-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
|
|
// CHECK7-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK7-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4
|
|
// CHECK7-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
|
|
// CHECK7-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
|
|
// CHECK7-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4
|
|
// CHECK7-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4
|
|
// CHECK7-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
|
|
// CHECK7-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK7-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK7-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK7-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
|
|
// CHECK7-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
|
|
// CHECK7-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4
|
|
// CHECK7-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
|
|
// CHECK7-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
|
|
// CHECK7-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
|
|
// CHECK7-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4
|
|
// CHECK7-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
|
|
// CHECK7-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK7-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
|
|
// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
|
|
// CHECK7-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
|
|
// CHECK7-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
|
|
// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
|
|
// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
|
|
// CHECK7-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
|
|
// CHECK7-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
|
|
// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK7-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4
|
|
// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4
|
|
// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK7-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
|
|
// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
|
|
// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*, i32)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i32 [[TMP11]])
|
|
// CHECK7-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..7
|
|
// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] {
|
|
// CHECK7-NEXT: entry:
|
|
// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK7-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
|
|
// CHECK7-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK7-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4
|
|
// CHECK7-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
|
|
// CHECK7-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
|
|
// CHECK7-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4
|
|
// CHECK7-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4
|
|
// CHECK7-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
|
|
// CHECK7-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK7-NEXT: [[TMP:%.*]] = alloca i8, align 1
|
|
// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK7-NEXT: [[IT:%.*]] = alloca i8, align 1
|
|
// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK7-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
|
|
// CHECK7-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
|
|
// CHECK7-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4
|
|
// CHECK7-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
|
|
// CHECK7-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
|
|
// CHECK7-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
|
|
// CHECK7-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4
|
|
// CHECK7-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
|
|
// CHECK7-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK7-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
|
|
// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
|
|
// CHECK7-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
|
|
// CHECK7-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
|
|
// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
|
|
// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
|
|
// CHECK7-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
|
|
// CHECK7-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
|
|
// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK7-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK7-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
|
|
// CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
|
|
// CHECK7-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
|
|
// CHECK7: omp.dispatch.cond:
|
|
// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25
|
|
// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK7: cond.true:
|
|
// CHECK7-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK7: cond.false:
|
|
// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK7-NEXT: br label [[COND_END]]
|
|
// CHECK7: cond.end:
|
|
// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
|
|
// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK7-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK7-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK7-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
|
|
// CHECK7-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
|
|
// CHECK7: omp.dispatch.body:
|
|
// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK7: omp.inner.for.cond:
|
|
// CHECK7-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36
|
|
// CHECK7-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !36
|
|
// CHECK7-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
|
|
// CHECK7-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK7: omp.inner.for.body:
|
|
// CHECK7-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36
|
|
// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
|
|
// CHECK7-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]]
|
|
// CHECK7-NEXT: [[CONV:%.*]] = trunc i32 [[SUB]] to i8
|
|
// CHECK7-NEXT: store i8 [[CONV]], i8* [[IT]], align 1, !llvm.access.group !36
|
|
// CHECK7-NEXT: [[TMP19:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !36
|
|
// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1
|
|
// CHECK7-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4, !llvm.access.group !36
|
|
// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2
|
|
// CHECK7-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !36
|
|
// CHECK7-NEXT: [[CONV7:%.*]] = fpext float [[TMP20]] to double
|
|
// CHECK7-NEXT: [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00
|
|
// CHECK7-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float
|
|
// CHECK7-NEXT: store float [[CONV9]], float* [[ARRAYIDX]], align 4, !llvm.access.group !36
|
|
// CHECK7-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3
|
|
// CHECK7-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX10]], align 4, !llvm.access.group !36
|
|
// CHECK7-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double
|
|
// CHECK7-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00
|
|
// CHECK7-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float
|
|
// CHECK7-NEXT: store float [[CONV13]], float* [[ARRAYIDX10]], align 4, !llvm.access.group !36
|
|
// CHECK7-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1
|
|
// CHECK7-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX14]], i32 0, i32 2
|
|
// CHECK7-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX15]], align 8, !llvm.access.group !36
|
|
// CHECK7-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00
|
|
// CHECK7-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8, !llvm.access.group !36
|
|
// CHECK7-NEXT: [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]]
|
|
// CHECK7-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP23]]
|
|
// CHECK7-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX17]], i32 3
|
|
// CHECK7-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX18]], align 8, !llvm.access.group !36
|
|
// CHECK7-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00
|
|
// CHECK7-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8, !llvm.access.group !36
|
|
// CHECK7-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0
|
|
// CHECK7-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 4, !llvm.access.group !36
|
|
// CHECK7-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1
|
|
// CHECK7-NEXT: store i64 [[ADD20]], i64* [[X]], align 4, !llvm.access.group !36
|
|
// CHECK7-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1
|
|
// CHECK7-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 4, !llvm.access.group !36
|
|
// CHECK7-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i32
|
|
// CHECK7-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1
|
|
// CHECK7-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8
|
|
// CHECK7-NEXT: store i8 [[CONV23]], i8* [[Y]], align 4, !llvm.access.group !36
|
|
// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK7: omp.body.continue:
|
|
// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK7: omp.inner.for.inc:
|
|
// CHECK7-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36
|
|
// CHECK7-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1
|
|
// CHECK7-NEXT: store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36
|
|
// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP37:![0-9]+]]
|
|
// CHECK7: omp.inner.for.end:
|
|
// CHECK7-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
|
|
// CHECK7: omp.dispatch.inc:
|
|
// CHECK7-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK7-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK7-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]
|
|
// CHECK7-NEXT: store i32 [[ADD25]], i32* [[DOTOMP_LB]], align 4
|
|
// CHECK7-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK7-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK7-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]]
|
|
// CHECK7-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK7-NEXT: br label [[OMP_DISPATCH_COND]]
|
|
// CHECK7: omp.dispatch.end:
|
|
// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]])
|
|
// CHECK7-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK7-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0
|
|
// CHECK7-NEXT: br i1 [[TMP33]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
|
|
// CHECK7: .omp.final.then:
|
|
// CHECK7-NEXT: store i8 96, i8* [[IT]], align 1
|
|
// CHECK7-NEXT: br label [[DOTOMP_FINAL_DONE]]
|
|
// CHECK7: .omp.final.done:
|
|
// CHECK7-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK7-LABEL: define {{[^@]+}}@_Z3bari
|
|
// CHECK7-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
|
|
// CHECK7-NEXT: entry:
|
|
// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK7-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK7-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4
|
|
// CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK7-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK7-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]])
|
|
// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
|
|
// CHECK7-NEXT: store i32 [[ADD]], i32* [[A]], align 4
|
|
// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK7-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]])
|
|
// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
|
|
// CHECK7-NEXT: store i32 [[ADD2]], i32* [[A]], align 4
|
|
// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK7-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]])
|
|
// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK7-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
|
|
// CHECK7-NEXT: store i32 [[ADD4]], i32* [[A]], align 4
|
|
// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK7-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]])
|
|
// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK7-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
|
|
// CHECK7-NEXT: store i32 [[ADD6]], i32* [[A]], align 4
|
|
// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK7-NEXT: ret i32 [[TMP8]]
|
|
//
|
|
//
|
|
// CHECK7-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
|
|
// CHECK7-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 {
|
|
// CHECK7-NEXT: entry:
|
|
// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
|
|
// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK7-NEXT: [[B:%.*]] = alloca i32, align 4
|
|
// CHECK7-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4
|
|
// CHECK7-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4
|
|
// CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
|
|
// CHECK7-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK7-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [6 x i8*], align 4
|
|
// CHECK7-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [6 x i8*], align 4
|
|
// CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [6 x i8*], align 4
|
|
// CHECK7-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [6 x i64], align 4
|
|
// CHECK7-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
|
|
// CHECK7-NEXT: store i32 [[ADD]], i32* [[B]], align 4
|
|
// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK7-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave()
|
|
// CHECK7-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4
|
|
// CHECK7-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]]
|
|
// CHECK7-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2
|
|
// CHECK7-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4
|
|
// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 60
|
|
// CHECK7-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8
|
|
// CHECK7-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
|
|
// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4
|
|
// CHECK7-NEXT: store i32 [[TMP5]], i32* [[B_CASTED]], align 4
|
|
// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4
|
|
// CHECK7-NEXT: [[TMP7:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
|
|
// CHECK7-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP7]] to i1
|
|
// CHECK7-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__CASTED]] to i8*
|
|
// CHECK7-NEXT: [[FROMBOOL2:%.*]] = zext i1 [[TOBOOL]] to i8
|
|
// CHECK7-NEXT: store i8 [[FROMBOOL2]], i8* [[CONV]], align 1
|
|
// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
|
|
// CHECK7-NEXT: [[TMP9:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
|
|
// CHECK7-NEXT: [[TOBOOL3:%.*]] = trunc i8 [[TMP9]] to i1
|
|
// CHECK7-NEXT: br i1 [[TOBOOL3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
|
|
// CHECK7: omp_if.then:
|
|
// CHECK7-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
|
|
// CHECK7-NEXT: [[TMP10:%.*]] = mul nuw i32 2, [[TMP1]]
|
|
// CHECK7-NEXT: [[TMP11:%.*]] = mul nuw i32 [[TMP10]], 2
|
|
// CHECK7-NEXT: [[TMP12:%.*]] = sext i32 [[TMP11]] to i64
|
|
// CHECK7-NEXT: [[TMP13:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK7-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to %struct.S1**
|
|
// CHECK7-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP14]], align 4
|
|
// CHECK7-NEXT: [[TMP15:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK7-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to double**
|
|
// CHECK7-NEXT: store double* [[A]], double** [[TMP16]], align 4
|
|
// CHECK7-NEXT: [[TMP17:%.*]] = getelementptr inbounds [6 x i64], [6 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
|
|
// CHECK7-NEXT: store i64 8, i64* [[TMP17]], align 4
|
|
// CHECK7-NEXT: [[TMP18:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
|
|
// CHECK7-NEXT: store i8* null, i8** [[TMP18]], align 4
|
|
// CHECK7-NEXT: [[TMP19:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
|
|
// CHECK7-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32*
|
|
// CHECK7-NEXT: store i32 [[TMP6]], i32* [[TMP20]], align 4
|
|
// CHECK7-NEXT: [[TMP21:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
|
|
// CHECK7-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i32*
|
|
// CHECK7-NEXT: store i32 [[TMP6]], i32* [[TMP22]], align 4
|
|
// CHECK7-NEXT: [[TMP23:%.*]] = getelementptr inbounds [6 x i64], [6 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1
|
|
// CHECK7-NEXT: store i64 4, i64* [[TMP23]], align 4
|
|
// CHECK7-NEXT: [[TMP24:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
|
|
// CHECK7-NEXT: store i8* null, i8** [[TMP24]], align 4
|
|
// CHECK7-NEXT: [[TMP25:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
|
|
// CHECK7-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i32*
|
|
// CHECK7-NEXT: store i32 2, i32* [[TMP26]], align 4
|
|
// CHECK7-NEXT: [[TMP27:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
|
|
// CHECK7-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i32*
|
|
// CHECK7-NEXT: store i32 2, i32* [[TMP28]], align 4
|
|
// CHECK7-NEXT: [[TMP29:%.*]] = getelementptr inbounds [6 x i64], [6 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2
|
|
// CHECK7-NEXT: store i64 4, i64* [[TMP29]], align 4
|
|
// CHECK7-NEXT: [[TMP30:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
|
|
// CHECK7-NEXT: store i8* null, i8** [[TMP30]], align 4
|
|
// CHECK7-NEXT: [[TMP31:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
|
|
// CHECK7-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i32*
|
|
// CHECK7-NEXT: store i32 [[TMP1]], i32* [[TMP32]], align 4
|
|
// CHECK7-NEXT: [[TMP33:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
|
|
// CHECK7-NEXT: [[TMP34:%.*]] = bitcast i8** [[TMP33]] to i32*
|
|
// CHECK7-NEXT: store i32 [[TMP1]], i32* [[TMP34]], align 4
|
|
// CHECK7-NEXT: [[TMP35:%.*]] = getelementptr inbounds [6 x i64], [6 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3
|
|
// CHECK7-NEXT: store i64 4, i64* [[TMP35]], align 4
|
|
// CHECK7-NEXT: [[TMP36:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
|
|
// CHECK7-NEXT: store i8* null, i8** [[TMP36]], align 4
|
|
// CHECK7-NEXT: [[TMP37:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
|
|
// CHECK7-NEXT: [[TMP38:%.*]] = bitcast i8** [[TMP37]] to i16**
|
|
// CHECK7-NEXT: store i16* [[VLA]], i16** [[TMP38]], align 4
|
|
// CHECK7-NEXT: [[TMP39:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
|
|
// CHECK7-NEXT: [[TMP40:%.*]] = bitcast i8** [[TMP39]] to i16**
|
|
// CHECK7-NEXT: store i16* [[VLA]], i16** [[TMP40]], align 4
|
|
// CHECK7-NEXT: [[TMP41:%.*]] = getelementptr inbounds [6 x i64], [6 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4
|
|
// CHECK7-NEXT: store i64 [[TMP12]], i64* [[TMP41]], align 4
|
|
// CHECK7-NEXT: [[TMP42:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4
|
|
// CHECK7-NEXT: store i8* null, i8** [[TMP42]], align 4
|
|
// CHECK7-NEXT: [[TMP43:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 5
|
|
// CHECK7-NEXT: [[TMP44:%.*]] = bitcast i8** [[TMP43]] to i32*
|
|
// CHECK7-NEXT: store i32 [[TMP8]], i32* [[TMP44]], align 4
|
|
// CHECK7-NEXT: [[TMP45:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 5
|
|
// CHECK7-NEXT: [[TMP46:%.*]] = bitcast i8** [[TMP45]] to i32*
|
|
// CHECK7-NEXT: store i32 [[TMP8]], i32* [[TMP46]], align 4
|
|
// CHECK7-NEXT: [[TMP47:%.*]] = getelementptr inbounds [6 x i64], [6 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 5
|
|
// CHECK7-NEXT: store i64 1, i64* [[TMP47]], align 4
|
|
// CHECK7-NEXT: [[TMP48:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 5
|
|
// CHECK7-NEXT: store i8* null, i8** [[TMP48]], align 4
|
|
// CHECK7-NEXT: [[TMP49:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK7-NEXT: [[TMP50:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK7-NEXT: [[TMP51:%.*]] = getelementptr inbounds [6 x i64], [6 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
|
|
// CHECK7-NEXT: [[TMP52:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
|
|
// CHECK7-NEXT: [[TOBOOL4:%.*]] = trunc i8 [[TMP52]] to i1
|
|
// CHECK7-NEXT: [[TMP53:%.*]] = select i1 [[TOBOOL4]], i32 0, i32 1
|
|
// CHECK7-NEXT: [[TMP54:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214.region_id, i32 6, i8** [[TMP49]], i8** [[TMP50]], i64* [[TMP51]], i64* getelementptr inbounds ([6 x i64], [6 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP53]])
|
|
// CHECK7-NEXT: [[TMP55:%.*]] = icmp ne i32 [[TMP54]], 0
|
|
// CHECK7-NEXT: br i1 [[TMP55]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
|
// CHECK7: omp_offload.failed:
|
|
// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214(%struct.S1* [[THIS1]], i32 [[TMP6]], i32 2, i32 [[TMP1]], i16* [[VLA]], i32 [[TMP8]]) #[[ATTR4]]
|
|
// CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
|
// CHECK7: omp_offload.cont:
|
|
// CHECK7-NEXT: br label [[OMP_IF_END:%.*]]
|
|
// CHECK7: omp_if.else:
|
|
// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214(%struct.S1* [[THIS1]], i32 [[TMP6]], i32 2, i32 [[TMP1]], i16* [[VLA]], i32 [[TMP8]]) #[[ATTR4]]
|
|
// CHECK7-NEXT: br label [[OMP_IF_END]]
|
|
// CHECK7: omp_if.end:
|
|
// CHECK7-NEXT: [[TMP56:%.*]] = mul nsw i32 1, [[TMP1]]
|
|
// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP56]]
|
|
// CHECK7-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
|
|
// CHECK7-NEXT: [[TMP57:%.*]] = load i16, i16* [[ARRAYIDX5]], align 2
|
|
// CHECK7-NEXT: [[CONV6:%.*]] = sext i16 [[TMP57]] to i32
|
|
// CHECK7-NEXT: [[TMP58:%.*]] = load i32, i32* [[B]], align 4
|
|
// CHECK7-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], [[TMP58]]
|
|
// CHECK7-NEXT: [[TMP59:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
|
|
// CHECK7-NEXT: call void @llvm.stackrestore(i8* [[TMP59]])
|
|
// CHECK7-NEXT: ret i32 [[ADD7]]
|
|
//
|
|
//
|
|
// CHECK7-LABEL: define {{[^@]+}}@_ZL7fstatici
|
|
// CHECK7-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
|
|
// CHECK7-NEXT: entry:
|
|
// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK7-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK7-NEXT: [[AA:%.*]] = alloca i16, align 2
|
|
// CHECK7-NEXT: [[AAA:%.*]] = alloca i8, align 1
|
|
// CHECK7-NEXT: [[B:%.*]] = alloca [10 x i32], align 4
|
|
// CHECK7-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK7-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK7-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4
|
|
// CHECK7-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4
|
|
// CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4
|
|
// CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK7-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK7-NEXT: store i16 0, i16* [[AA]], align 2
|
|
// CHECK7-NEXT: store i8 0, i8* [[AAA]], align 1
|
|
// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK7-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
|
|
// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
|
|
// CHECK7-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
|
|
// CHECK7-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
|
|
// CHECK7-NEXT: store i16 [[TMP2]], i16* [[CONV]], align 2
|
|
// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
|
|
// CHECK7-NEXT: [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1
|
|
// CHECK7-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
|
|
// CHECK7-NEXT: store i8 [[TMP4]], i8* [[CONV1]], align 1
|
|
// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
|
|
// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50
|
|
// CHECK7-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
|
|
// CHECK7: omp_if.then:
|
|
// CHECK7-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK7-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32*
|
|
// CHECK7-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4
|
|
// CHECK7-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK7-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32*
|
|
// CHECK7-NEXT: store i32 [[TMP1]], i32* [[TMP10]], align 4
|
|
// CHECK7-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
|
|
// CHECK7-NEXT: store i8* null, i8** [[TMP11]], align 4
|
|
// CHECK7-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
|
|
// CHECK7-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32*
|
|
// CHECK7-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4
|
|
// CHECK7-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
|
|
// CHECK7-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32*
|
|
// CHECK7-NEXT: store i32 [[TMP3]], i32* [[TMP15]], align 4
|
|
// CHECK7-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
|
|
// CHECK7-NEXT: store i8* null, i8** [[TMP16]], align 4
|
|
// CHECK7-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
|
|
// CHECK7-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32*
|
|
// CHECK7-NEXT: store i32 [[TMP5]], i32* [[TMP18]], align 4
|
|
// CHECK7-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
|
|
// CHECK7-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32*
|
|
// CHECK7-NEXT: store i32 [[TMP5]], i32* [[TMP20]], align 4
|
|
// CHECK7-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
|
|
// CHECK7-NEXT: store i8* null, i8** [[TMP21]], align 4
|
|
// CHECK7-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
|
|
// CHECK7-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]**
|
|
// CHECK7-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 4
|
|
// CHECK7-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
|
|
// CHECK7-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]**
|
|
// CHECK7-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 4
|
|
// CHECK7-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
|
|
// CHECK7-NEXT: store i8* null, i8** [[TMP26]], align 4
|
|
// CHECK7-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK7-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK7-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
|
|
// CHECK7-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0
|
|
// CHECK7-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
|
// CHECK7: omp_offload.failed:
|
|
// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]]
|
|
// CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
|
// CHECK7: omp_offload.cont:
|
|
// CHECK7-NEXT: br label [[OMP_IF_END:%.*]]
|
|
// CHECK7: omp_if.else:
|
|
// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]]
|
|
// CHECK7-NEXT: br label [[OMP_IF_END]]
|
|
// CHECK7: omp_if.end:
|
|
// CHECK7-NEXT: [[TMP31:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK7-NEXT: ret i32 [[TMP31]]
|
|
//
|
|
//
|
|
// CHECK7-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
|
|
// CHECK7-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat {
|
|
// CHECK7-NEXT: entry:
|
|
// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK7-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK7-NEXT: [[AA:%.*]] = alloca i16, align 2
|
|
// CHECK7-NEXT: [[B:%.*]] = alloca [10 x i32], align 4
|
|
// CHECK7-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK7-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4
|
|
// CHECK7-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4
|
|
// CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4
|
|
// CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK7-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK7-NEXT: store i16 0, i16* [[AA]], align 2
|
|
// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK7-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
|
|
// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
|
|
// CHECK7-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
|
|
// CHECK7-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
|
|
// CHECK7-NEXT: store i16 [[TMP2]], i16* [[CONV]], align 2
|
|
// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
|
|
// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40
|
|
// CHECK7-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
|
|
// CHECK7: omp_if.then:
|
|
// CHECK7-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK7-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i32*
|
|
// CHECK7-NEXT: store i32 [[TMP1]], i32* [[TMP6]], align 4
|
|
// CHECK7-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK7-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32*
|
|
// CHECK7-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4
|
|
// CHECK7-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
|
|
// CHECK7-NEXT: store i8* null, i8** [[TMP9]], align 4
|
|
// CHECK7-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
|
|
// CHECK7-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i32*
|
|
// CHECK7-NEXT: store i32 [[TMP3]], i32* [[TMP11]], align 4
|
|
// CHECK7-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
|
|
// CHECK7-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32*
|
|
// CHECK7-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4
|
|
// CHECK7-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
|
|
// CHECK7-NEXT: store i8* null, i8** [[TMP14]], align 4
|
|
// CHECK7-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
|
|
// CHECK7-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]**
|
|
// CHECK7-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 4
|
|
// CHECK7-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
|
|
// CHECK7-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]**
|
|
// CHECK7-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 4
|
|
// CHECK7-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
|
|
// CHECK7-NEXT: store i8* null, i8** [[TMP19]], align 4
|
|
// CHECK7-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK7-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK7-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.15, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.16, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
|
|
// CHECK7-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0
|
|
// CHECK7-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
|
// CHECK7: omp_offload.failed:
|
|
// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]]
|
|
// CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
|
// CHECK7: omp_offload.cont:
|
|
// CHECK7-NEXT: br label [[OMP_IF_END:%.*]]
|
|
// CHECK7: omp_if.else:
|
|
// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]]
|
|
// CHECK7-NEXT: br label [[OMP_IF_END]]
|
|
// CHECK7: omp_if.end:
|
|
// CHECK7-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK7-NEXT: ret i32 [[TMP24]]
|
|
//
|
|
//
|
|
// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214
|
|
// CHECK7-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] {
|
|
// CHECK7-NEXT: entry:
|
|
// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
|
|
// CHECK7-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK7-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK7-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
|
|
// CHECK7-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4
|
|
// CHECK7-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK7-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK7-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK7-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
|
|
// CHECK7-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK7-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4
|
|
// CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]])
|
|
// CHECK7-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK7-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
|
|
// CHECK7-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
|
|
// CHECK7-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
|
|
// CHECK7-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4
|
|
// CHECK7-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK7-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
|
|
// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
|
|
// CHECK7-NEXT: [[TMP4:%.*]] = load i16*, i16** [[C_ADDR]], align 4
|
|
// CHECK7-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8*
|
|
// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_ADDR]], align 4
|
|
// CHECK7-NEXT: store i32 [[TMP5]], i32* [[B_CASTED]], align 4
|
|
// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4
|
|
// CHECK7-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV]], align 4
|
|
// CHECK7-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP7]] to i1
|
|
// CHECK7-NEXT: [[CONV3:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__CASTED]] to i8*
|
|
// CHECK7-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
|
|
// CHECK7-NEXT: store i8 [[FROMBOOL]], i8* [[CONV3]], align 1
|
|
// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
|
|
// CHECK7-NEXT: [[TMP9:%.*]] = load i8, i8* [[CONV]], align 4
|
|
// CHECK7-NEXT: [[TOBOOL4:%.*]] = trunc i8 [[TMP9]] to i1
|
|
// CHECK7-NEXT: br i1 [[TOBOOL4]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
|
|
// CHECK7: omp_if.then:
|
|
// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*, i32)* @.omp_outlined..9 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP6]], i32 [[TMP2]], i32 [[TMP3]], i16* [[TMP4]], i32 [[TMP8]])
|
|
// CHECK7-NEXT: br label [[OMP_IF_END:%.*]]
|
|
// CHECK7: omp_if.else:
|
|
// CHECK7-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]])
|
|
// CHECK7-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
|
|
// CHECK7-NEXT: call void @.omp_outlined..9(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]], i32 [[TMP6]], i32 [[TMP2]], i32 [[TMP3]], i16* [[TMP4]], i32 [[TMP8]]) #[[ATTR4]]
|
|
// CHECK7-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]])
|
|
// CHECK7-NEXT: br label [[OMP_IF_END]]
|
|
// CHECK7: omp_if.end:
|
|
// CHECK7-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..9
|
|
// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] {
|
|
// CHECK7-NEXT: entry:
|
|
// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
|
|
// CHECK7-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK7-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK7-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
|
|
// CHECK7-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4
|
|
// CHECK7-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
|
|
// CHECK7-NEXT: [[TMP:%.*]] = alloca i64, align 4
|
|
// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
|
|
// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
|
|
// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
|
|
// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK7-NEXT: [[IT:%.*]] = alloca i64, align 8
|
|
// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK7-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK7-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
|
|
// CHECK7-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
|
|
// CHECK7-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
|
|
// CHECK7-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4
|
|
// CHECK7-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK7-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
|
|
// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
|
|
// CHECK7-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
|
|
// CHECK7-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8*
|
|
// CHECK7-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK7-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK7-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
|
|
// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK7-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV]], align 4
|
|
// CHECK7-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1
|
|
// CHECK7-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
|
|
// CHECK7: omp_if.then:
|
|
// CHECK7-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4
|
|
// CHECK7-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
|
|
// CHECK7-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK7-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP7]], 3
|
|
// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK7: cond.true:
|
|
// CHECK7-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK7: cond.false:
|
|
// CHECK7-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK7-NEXT: br label [[COND_END]]
|
|
// CHECK7: cond.end:
|
|
// CHECK7-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ]
|
|
// CHECK7-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
|
|
// CHECK7-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK7-NEXT: store i64 [[TMP9]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK7: omp.inner.for.cond:
|
|
// CHECK7-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !39
|
|
// CHECK7-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !39
|
|
// CHECK7-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP10]], [[TMP11]]
|
|
// CHECK7-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK7: omp.inner.for.body:
|
|
// CHECK7-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !39
|
|
// CHECK7-NEXT: [[MUL:%.*]] = mul i64 [[TMP12]], 400
|
|
// CHECK7-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]
|
|
// CHECK7-NEXT: store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !39
|
|
// CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[B_ADDR]], align 4, !llvm.access.group !39
|
|
// CHECK7-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP13]] to double
|
|
// CHECK7-NEXT: [[ADD:%.*]] = fadd double [[CONV4]], 1.500000e+00
|
|
// CHECK7-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
|
|
// CHECK7-NEXT: store double [[ADD]], double* [[A]], align 4, !nontemporal !40, !llvm.access.group !39
|
|
// CHECK7-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
|
|
// CHECK7-NEXT: [[TMP14:%.*]] = load double, double* [[A5]], align 4, !nontemporal !40, !llvm.access.group !39
|
|
// CHECK7-NEXT: [[INC:%.*]] = fadd double [[TMP14]], 1.000000e+00
|
|
// CHECK7-NEXT: store double [[INC]], double* [[A5]], align 4, !nontemporal !40, !llvm.access.group !39
|
|
// CHECK7-NEXT: [[CONV6:%.*]] = fptosi double [[INC]] to i16
|
|
// CHECK7-NEXT: [[TMP15:%.*]] = mul nsw i32 1, [[TMP2]]
|
|
// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP15]]
|
|
// CHECK7-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
|
|
// CHECK7-NEXT: store i16 [[CONV6]], i16* [[ARRAYIDX7]], align 2, !llvm.access.group !39
|
|
// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK7: omp.body.continue:
|
|
// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK7: omp.inner.for.inc:
|
|
// CHECK7-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !39
|
|
// CHECK7-NEXT: [[ADD8:%.*]] = add i64 [[TMP16]], 1
|
|
// CHECK7-NEXT: store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !39
|
|
// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP41:![0-9]+]]
|
|
// CHECK7: omp.inner.for.end:
|
|
// CHECK7-NEXT: br label [[OMP_IF_END:%.*]]
|
|
// CHECK7: omp_if.else:
|
|
// CHECK7-NEXT: [[TMP17:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK7-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP17]], align 4
|
|
// CHECK7-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP18]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
|
|
// CHECK7-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK7-NEXT: [[CMP9:%.*]] = icmp ugt i64 [[TMP19]], 3
|
|
// CHECK7-NEXT: br i1 [[CMP9]], label [[COND_TRUE10:%.*]], label [[COND_FALSE11:%.*]]
|
|
// CHECK7: cond.true10:
|
|
// CHECK7-NEXT: br label [[COND_END12:%.*]]
|
|
// CHECK7: cond.false11:
|
|
// CHECK7-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK7-NEXT: br label [[COND_END12]]
|
|
// CHECK7: cond.end12:
|
|
// CHECK7-NEXT: [[COND13:%.*]] = phi i64 [ 3, [[COND_TRUE10]] ], [ [[TMP20]], [[COND_FALSE11]] ]
|
|
// CHECK7-NEXT: store i64 [[COND13]], i64* [[DOTOMP_UB]], align 8
|
|
// CHECK7-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK7-NEXT: store i64 [[TMP21]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND14:%.*]]
|
|
// CHECK7: omp.inner.for.cond14:
|
|
// CHECK7-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK7-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK7-NEXT: [[CMP15:%.*]] = icmp ule i64 [[TMP22]], [[TMP23]]
|
|
// CHECK7-NEXT: br i1 [[CMP15]], label [[OMP_INNER_FOR_BODY16:%.*]], label [[OMP_INNER_FOR_END30:%.*]]
|
|
// CHECK7: omp.inner.for.body16:
|
|
// CHECK7-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK7-NEXT: [[MUL17:%.*]] = mul i64 [[TMP24]], 400
|
|
// CHECK7-NEXT: [[SUB18:%.*]] = sub i64 2000, [[MUL17]]
|
|
// CHECK7-NEXT: store i64 [[SUB18]], i64* [[IT]], align 8
|
|
// CHECK7-NEXT: [[TMP25:%.*]] = load i32, i32* [[B_ADDR]], align 4
|
|
// CHECK7-NEXT: [[CONV19:%.*]] = sitofp i32 [[TMP25]] to double
|
|
// CHECK7-NEXT: [[ADD20:%.*]] = fadd double [[CONV19]], 1.500000e+00
|
|
// CHECK7-NEXT: [[A21:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
|
|
// CHECK7-NEXT: store double [[ADD20]], double* [[A21]], align 4
|
|
// CHECK7-NEXT: [[A22:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
|
|
// CHECK7-NEXT: [[TMP26:%.*]] = load double, double* [[A22]], align 4
|
|
// CHECK7-NEXT: [[INC23:%.*]] = fadd double [[TMP26]], 1.000000e+00
|
|
// CHECK7-NEXT: store double [[INC23]], double* [[A22]], align 4
|
|
// CHECK7-NEXT: [[CONV24:%.*]] = fptosi double [[INC23]] to i16
|
|
// CHECK7-NEXT: [[TMP27:%.*]] = mul nsw i32 1, [[TMP2]]
|
|
// CHECK7-NEXT: [[ARRAYIDX25:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP27]]
|
|
// CHECK7-NEXT: [[ARRAYIDX26:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX25]], i32 1
|
|
// CHECK7-NEXT: store i16 [[CONV24]], i16* [[ARRAYIDX26]], align 2
|
|
// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE27:%.*]]
|
|
// CHECK7: omp.body.continue27:
|
|
// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC28:%.*]]
|
|
// CHECK7: omp.inner.for.inc28:
|
|
// CHECK7-NEXT: [[TMP28:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK7-NEXT: [[ADD29:%.*]] = add i64 [[TMP28]], 1
|
|
// CHECK7-NEXT: store i64 [[ADD29]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND14]], !llvm.loop [[LOOP43:![0-9]+]]
|
|
// CHECK7: omp.inner.for.end30:
|
|
// CHECK7-NEXT: br label [[OMP_IF_END]]
|
|
// CHECK7: omp_if.end:
|
|
// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK7: omp.loop.exit:
|
|
// CHECK7-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK7-NEXT: [[TMP30:%.*]] = load i32, i32* [[TMP29]], align 4
|
|
// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP30]])
|
|
// CHECK7-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK7-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0
|
|
// CHECK7-NEXT: br i1 [[TMP32]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
|
|
// CHECK7: .omp.final.then:
|
|
// CHECK7-NEXT: store i64 400, i64* [[IT]], align 8
|
|
// CHECK7-NEXT: br label [[DOTOMP_FINAL_DONE]]
|
|
// CHECK7: .omp.final.done:
|
|
// CHECK7-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195
|
|
// CHECK7-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
|
|
// CHECK7-NEXT: entry:
|
|
// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK7-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK7-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK7-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
|
|
// CHECK7-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK7-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK7-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK7-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
|
|
// CHECK7-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
|
|
// CHECK7-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
|
|
// CHECK7-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
|
|
// CHECK7-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
|
|
// CHECK7-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
|
|
// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK7-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
|
|
// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
|
|
// CHECK7-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
|
|
// CHECK7-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
|
|
// CHECK7-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2
|
|
// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
|
|
// CHECK7-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 4
|
|
// CHECK7-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
|
|
// CHECK7-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1
|
|
// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
|
|
// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]])
|
|
// CHECK7-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..11
|
|
// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] {
|
|
// CHECK7-NEXT: entry:
|
|
// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK7-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK7-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK7-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
|
|
// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK7-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
|
|
// CHECK7-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
|
|
// CHECK7-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
|
|
// CHECK7-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
|
|
// CHECK7-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
|
|
// CHECK7-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
|
|
// CHECK7-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178
|
|
// CHECK7-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
|
|
// CHECK7-NEXT: entry:
|
|
// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK7-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK7-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
|
|
// CHECK7-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK7-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK7-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
|
|
// CHECK7-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
|
|
// CHECK7-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
|
|
// CHECK7-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
|
|
// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK7-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
|
|
// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
|
|
// CHECK7-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
|
|
// CHECK7-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
|
|
// CHECK7-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2
|
|
// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
|
|
// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]])
|
|
// CHECK7-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..14
|
|
// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] {
|
|
// CHECK7-NEXT: entry:
|
|
// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK7-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK7-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
|
|
// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
|
|
// CHECK7-NEXT: [[TMP:%.*]] = alloca i64, align 4
|
|
// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
|
|
// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
|
|
// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
|
|
// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK7-NEXT: [[I:%.*]] = alloca i64, align 8
|
|
// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK7-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
|
|
// CHECK7-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
|
|
// CHECK7-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
|
|
// CHECK7-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
|
|
// CHECK7-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK7-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK7-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
|
|
// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK7-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
|
|
// CHECK7-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
|
|
// CHECK7-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6
|
|
// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK7: cond.true:
|
|
// CHECK7-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK7: cond.false:
|
|
// CHECK7-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK7-NEXT: br label [[COND_END]]
|
|
// CHECK7: cond.end:
|
|
// CHECK7-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
|
|
// CHECK7-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
|
|
// CHECK7-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK7-NEXT: store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK7: omp.inner.for.cond:
|
|
// CHECK7-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !45
|
|
// CHECK7-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !45
|
|
// CHECK7-NEXT: [[CMP1:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]]
|
|
// CHECK7-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK7: omp.inner.for.body:
|
|
// CHECK7-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !45
|
|
// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3
|
|
// CHECK7-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
|
|
// CHECK7-NEXT: store i64 [[ADD]], i64* [[I]], align 8, !llvm.access.group !45
|
|
// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !45
|
|
// CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
|
|
// CHECK7-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4, !llvm.access.group !45
|
|
// CHECK7-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !45
|
|
// CHECK7-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32
|
|
// CHECK7-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
|
|
// CHECK7-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
|
|
// CHECK7-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 4, !llvm.access.group !45
|
|
// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
|
|
// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !45
|
|
// CHECK7-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1
|
|
// CHECK7-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !45
|
|
// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK7: omp.body.continue:
|
|
// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK7: omp.inner.for.inc:
|
|
// CHECK7-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !45
|
|
// CHECK7-NEXT: [[ADD7:%.*]] = add nsw i64 [[TMP12]], 1
|
|
// CHECK7-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !45
|
|
// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP46:![0-9]+]]
|
|
// CHECK7: omp.inner.for.end:
|
|
// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK7: omp.loop.exit:
|
|
// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
|
|
// CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK7-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
|
|
// CHECK7-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
|
|
// CHECK7: .omp.final.then:
|
|
// CHECK7-NEXT: store i64 11, i64* [[I]], align 8
|
|
// CHECK7-NEXT: br label [[DOTOMP_FINAL_DONE]]
|
|
// CHECK7: .omp.final.done:
|
|
// CHECK7-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK7-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
|
|
// CHECK7-SAME: () #[[ATTR7:[0-9]+]] {
|
|
// CHECK7-NEXT: entry:
|
|
// CHECK7-NEXT: call void @__tgt_register_requires(i64 1)
|
|
// CHECK7-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK8-LABEL: define {{[^@]+}}@_Z7get_valv
|
|
// CHECK8-SAME: () #[[ATTR0:[0-9]+]] {
|
|
// CHECK8-NEXT: entry:
|
|
// CHECK8-NEXT: ret i64 0
|
|
//
|
|
//
|
|
// CHECK8-LABEL: define {{[^@]+}}@_Z3fooi
|
|
// CHECK8-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
|
|
// CHECK8-NEXT: entry:
|
|
// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK8-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK8-NEXT: [[AA:%.*]] = alloca i16, align 2
|
|
// CHECK8-NEXT: [[B:%.*]] = alloca [10 x float], align 4
|
|
// CHECK8-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4
|
|
// CHECK8-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4
|
|
// CHECK8-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8
|
|
// CHECK8-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4
|
|
// CHECK8-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4
|
|
// CHECK8-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 1
|
|
// CHECK8-NEXT: [[K:%.*]] = alloca i64, align 8
|
|
// CHECK8-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK8-NEXT: [[LIN:%.*]] = alloca i32, align 4
|
|
// CHECK8-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK8-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK8-NEXT: [[A_CASTED2:%.*]] = alloca i32, align 4
|
|
// CHECK8-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4
|
|
// CHECK8-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4
|
|
// CHECK8-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4
|
|
// CHECK8-NEXT: [[A_CASTED3:%.*]] = alloca i32, align 4
|
|
// CHECK8-NEXT: [[AA_CASTED4:%.*]] = alloca i32, align 4
|
|
// CHECK8-NEXT: [[DOTOFFLOAD_BASEPTRS6:%.*]] = alloca [2 x i8*], align 4
|
|
// CHECK8-NEXT: [[DOTOFFLOAD_PTRS7:%.*]] = alloca [2 x i8*], align 4
|
|
// CHECK8-NEXT: [[DOTOFFLOAD_MAPPERS8:%.*]] = alloca [2 x i8*], align 4
|
|
// CHECK8-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
|
// CHECK8-NEXT: [[A_CASTED11:%.*]] = alloca i32, align 4
|
|
// CHECK8-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK8-NEXT: [[DOTOFFLOAD_BASEPTRS14:%.*]] = alloca [10 x i8*], align 4
|
|
// CHECK8-NEXT: [[DOTOFFLOAD_PTRS15:%.*]] = alloca [10 x i8*], align 4
|
|
// CHECK8-NEXT: [[DOTOFFLOAD_MAPPERS16:%.*]] = alloca [10 x i8*], align 4
|
|
// CHECK8-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 4
|
|
// CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]])
|
|
// CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK8-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK8-NEXT: store i16 0, i16* [[AA]], align 2
|
|
// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK8-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave()
|
|
// CHECK8-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4
|
|
// CHECK8-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP1]], align 4
|
|
// CHECK8-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4
|
|
// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK8-NEXT: [[TMP4:%.*]] = mul nuw i32 5, [[TMP3]]
|
|
// CHECK8-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP4]], align 8
|
|
// CHECK8-NEXT: store i32 [[TMP3]], i32* [[__VLA_EXPR1]], align 4
|
|
// CHECK8-NEXT: [[TMP5:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 1, i32 20, i32 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1)
|
|
// CHECK8-NEXT: [[TMP6:%.*]] = bitcast i8* [[TMP5]] to %struct.kmp_task_t_with_privates*
|
|
// CHECK8-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP6]], i32 0, i32 0
|
|
// CHECK8-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i8* [[TMP5]])
|
|
// CHECK8-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv()
|
|
// CHECK8-NEXT: store i64 [[CALL]], i64* [[K]], align 8
|
|
// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK8-NEXT: store i32 [[TMP9]], i32* [[A_CASTED]], align 4
|
|
// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[A_CASTED]], align 4
|
|
// CHECK8-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101(i32 [[TMP10]], i64* [[K]]) #[[ATTR4:[0-9]+]]
|
|
// CHECK8-NEXT: store i32 12, i32* [[LIN]], align 4
|
|
// CHECK8-NEXT: [[TMP11:%.*]] = load i16, i16* [[AA]], align 2
|
|
// CHECK8-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
|
|
// CHECK8-NEXT: store i16 [[TMP11]], i16* [[CONV]], align 2
|
|
// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[AA_CASTED]], align 4
|
|
// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[LIN]], align 4
|
|
// CHECK8-NEXT: store i32 [[TMP13]], i32* [[LIN_CASTED]], align 4
|
|
// CHECK8-NEXT: [[TMP14:%.*]] = load i32, i32* [[LIN_CASTED]], align 4
|
|
// CHECK8-NEXT: [[TMP15:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK8-NEXT: store i32 [[TMP15]], i32* [[A_CASTED2]], align 4
|
|
// CHECK8-NEXT: [[TMP16:%.*]] = load i32, i32* [[A_CASTED2]], align 4
|
|
// CHECK8-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK8-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32*
|
|
// CHECK8-NEXT: store i32 [[TMP12]], i32* [[TMP18]], align 4
|
|
// CHECK8-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK8-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32*
|
|
// CHECK8-NEXT: store i32 [[TMP12]], i32* [[TMP20]], align 4
|
|
// CHECK8-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
|
|
// CHECK8-NEXT: store i8* null, i8** [[TMP21]], align 4
|
|
// CHECK8-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
|
|
// CHECK8-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i32*
|
|
// CHECK8-NEXT: store i32 [[TMP14]], i32* [[TMP23]], align 4
|
|
// CHECK8-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
|
|
// CHECK8-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i32*
|
|
// CHECK8-NEXT: store i32 [[TMP14]], i32* [[TMP25]], align 4
|
|
// CHECK8-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
|
|
// CHECK8-NEXT: store i8* null, i8** [[TMP26]], align 4
|
|
// CHECK8-NEXT: [[TMP27:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
|
|
// CHECK8-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i32*
|
|
// CHECK8-NEXT: store i32 [[TMP16]], i32* [[TMP28]], align 4
|
|
// CHECK8-NEXT: [[TMP29:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
|
|
// CHECK8-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i32*
|
|
// CHECK8-NEXT: store i32 [[TMP16]], i32* [[TMP30]], align 4
|
|
// CHECK8-NEXT: [[TMP31:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
|
|
// CHECK8-NEXT: store i8* null, i8** [[TMP31]], align 4
|
|
// CHECK8-NEXT: [[TMP32:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK8-NEXT: [[TMP33:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK8-NEXT: [[TMP34:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108.region_id, i32 3, i8** [[TMP32]], i8** [[TMP33]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
|
|
// CHECK8-NEXT: [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 0
|
|
// CHECK8-NEXT: br i1 [[TMP35]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
|
// CHECK8: omp_offload.failed:
|
|
// CHECK8-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108(i32 [[TMP12]], i32 [[TMP14]], i32 [[TMP16]]) #[[ATTR4]]
|
|
// CHECK8-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
|
// CHECK8: omp_offload.cont:
|
|
// CHECK8-NEXT: [[TMP36:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK8-NEXT: store i32 [[TMP36]], i32* [[A_CASTED3]], align 4
|
|
// CHECK8-NEXT: [[TMP37:%.*]] = load i32, i32* [[A_CASTED3]], align 4
|
|
// CHECK8-NEXT: [[TMP38:%.*]] = load i16, i16* [[AA]], align 2
|
|
// CHECK8-NEXT: [[CONV5:%.*]] = bitcast i32* [[AA_CASTED4]] to i16*
|
|
// CHECK8-NEXT: store i16 [[TMP38]], i16* [[CONV5]], align 2
|
|
// CHECK8-NEXT: [[TMP39:%.*]] = load i32, i32* [[AA_CASTED4]], align 4
|
|
// CHECK8-NEXT: [[TMP40:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP40]], 10
|
|
// CHECK8-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
|
|
// CHECK8: omp_if.then:
|
|
// CHECK8-NEXT: [[TMP41:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0
|
|
// CHECK8-NEXT: [[TMP42:%.*]] = bitcast i8** [[TMP41]] to i32*
|
|
// CHECK8-NEXT: store i32 [[TMP37]], i32* [[TMP42]], align 4
|
|
// CHECK8-NEXT: [[TMP43:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0
|
|
// CHECK8-NEXT: [[TMP44:%.*]] = bitcast i8** [[TMP43]] to i32*
|
|
// CHECK8-NEXT: store i32 [[TMP37]], i32* [[TMP44]], align 4
|
|
// CHECK8-NEXT: [[TMP45:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS8]], i32 0, i32 0
|
|
// CHECK8-NEXT: store i8* null, i8** [[TMP45]], align 4
|
|
// CHECK8-NEXT: [[TMP46:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 1
|
|
// CHECK8-NEXT: [[TMP47:%.*]] = bitcast i8** [[TMP46]] to i32*
|
|
// CHECK8-NEXT: store i32 [[TMP39]], i32* [[TMP47]], align 4
|
|
// CHECK8-NEXT: [[TMP48:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 1
|
|
// CHECK8-NEXT: [[TMP49:%.*]] = bitcast i8** [[TMP48]] to i32*
|
|
// CHECK8-NEXT: store i32 [[TMP39]], i32* [[TMP49]], align 4
|
|
// CHECK8-NEXT: [[TMP50:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS8]], i32 0, i32 1
|
|
// CHECK8-NEXT: store i8* null, i8** [[TMP50]], align 4
|
|
// CHECK8-NEXT: [[TMP51:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0
|
|
// CHECK8-NEXT: [[TMP52:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0
|
|
// CHECK8-NEXT: [[TMP53:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116.region_id, i32 2, i8** [[TMP51]], i8** [[TMP52]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
|
|
// CHECK8-NEXT: [[TMP54:%.*]] = icmp ne i32 [[TMP53]], 0
|
|
// CHECK8-NEXT: br i1 [[TMP54]], label [[OMP_OFFLOAD_FAILED9:%.*]], label [[OMP_OFFLOAD_CONT10:%.*]]
|
|
// CHECK8: omp_offload.failed9:
|
|
// CHECK8-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116(i32 [[TMP37]], i32 [[TMP39]]) #[[ATTR4]]
|
|
// CHECK8-NEXT: br label [[OMP_OFFLOAD_CONT10]]
|
|
// CHECK8: omp_offload.cont10:
|
|
// CHECK8-NEXT: br label [[OMP_IF_END:%.*]]
|
|
// CHECK8: omp_if.else:
|
|
// CHECK8-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116(i32 [[TMP37]], i32 [[TMP39]]) #[[ATTR4]]
|
|
// CHECK8-NEXT: br label [[OMP_IF_END]]
|
|
// CHECK8: omp_if.end:
|
|
// CHECK8-NEXT: [[TMP55:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK8-NEXT: store i32 [[TMP55]], i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK8-NEXT: [[TMP56:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK8-NEXT: store i32 [[TMP56]], i32* [[A_CASTED11]], align 4
|
|
// CHECK8-NEXT: [[TMP57:%.*]] = load i32, i32* [[A_CASTED11]], align 4
|
|
// CHECK8-NEXT: [[TMP58:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK8-NEXT: store i32 [[TMP58]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
|
|
// CHECK8-NEXT: [[TMP59:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
|
|
// CHECK8-NEXT: [[TMP60:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK8-NEXT: [[CMP12:%.*]] = icmp sgt i32 [[TMP60]], 20
|
|
// CHECK8-NEXT: br i1 [[CMP12]], label [[OMP_IF_THEN13:%.*]], label [[OMP_IF_ELSE19:%.*]]
|
|
// CHECK8: omp_if.then13:
|
|
// CHECK8-NEXT: [[TMP61:%.*]] = mul nuw i32 [[TMP1]], 4
|
|
// CHECK8-NEXT: [[TMP62:%.*]] = sext i32 [[TMP61]] to i64
|
|
// CHECK8-NEXT: [[TMP63:%.*]] = mul nuw i32 5, [[TMP3]]
|
|
// CHECK8-NEXT: [[TMP64:%.*]] = mul nuw i32 [[TMP63]], 8
|
|
// CHECK8-NEXT: [[TMP65:%.*]] = sext i32 [[TMP64]] to i64
|
|
// CHECK8-NEXT: [[TMP66:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 0
|
|
// CHECK8-NEXT: [[TMP67:%.*]] = bitcast i8** [[TMP66]] to i32*
|
|
// CHECK8-NEXT: store i32 [[TMP57]], i32* [[TMP67]], align 4
|
|
// CHECK8-NEXT: [[TMP68:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 0
|
|
// CHECK8-NEXT: [[TMP69:%.*]] = bitcast i8** [[TMP68]] to i32*
|
|
// CHECK8-NEXT: store i32 [[TMP57]], i32* [[TMP69]], align 4
|
|
// CHECK8-NEXT: [[TMP70:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
|
|
// CHECK8-NEXT: store i64 4, i64* [[TMP70]], align 4
|
|
// CHECK8-NEXT: [[TMP71:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 0
|
|
// CHECK8-NEXT: store i8* null, i8** [[TMP71]], align 4
|
|
// CHECK8-NEXT: [[TMP72:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 1
|
|
// CHECK8-NEXT: [[TMP73:%.*]] = bitcast i8** [[TMP72]] to [10 x float]**
|
|
// CHECK8-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP73]], align 4
|
|
// CHECK8-NEXT: [[TMP74:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 1
|
|
// CHECK8-NEXT: [[TMP75:%.*]] = bitcast i8** [[TMP74]] to [10 x float]**
|
|
// CHECK8-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP75]], align 4
|
|
// CHECK8-NEXT: [[TMP76:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1
|
|
// CHECK8-NEXT: store i64 40, i64* [[TMP76]], align 4
|
|
// CHECK8-NEXT: [[TMP77:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 1
|
|
// CHECK8-NEXT: store i8* null, i8** [[TMP77]], align 4
|
|
// CHECK8-NEXT: [[TMP78:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 2
|
|
// CHECK8-NEXT: [[TMP79:%.*]] = bitcast i8** [[TMP78]] to i32*
|
|
// CHECK8-NEXT: store i32 [[TMP1]], i32* [[TMP79]], align 4
|
|
// CHECK8-NEXT: [[TMP80:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 2
|
|
// CHECK8-NEXT: [[TMP81:%.*]] = bitcast i8** [[TMP80]] to i32*
|
|
// CHECK8-NEXT: store i32 [[TMP1]], i32* [[TMP81]], align 4
|
|
// CHECK8-NEXT: [[TMP82:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2
|
|
// CHECK8-NEXT: store i64 4, i64* [[TMP82]], align 4
|
|
// CHECK8-NEXT: [[TMP83:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 2
|
|
// CHECK8-NEXT: store i8* null, i8** [[TMP83]], align 4
|
|
// CHECK8-NEXT: [[TMP84:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 3
|
|
// CHECK8-NEXT: [[TMP85:%.*]] = bitcast i8** [[TMP84]] to float**
|
|
// CHECK8-NEXT: store float* [[VLA]], float** [[TMP85]], align 4
|
|
// CHECK8-NEXT: [[TMP86:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 3
|
|
// CHECK8-NEXT: [[TMP87:%.*]] = bitcast i8** [[TMP86]] to float**
|
|
// CHECK8-NEXT: store float* [[VLA]], float** [[TMP87]], align 4
|
|
// CHECK8-NEXT: [[TMP88:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3
|
|
// CHECK8-NEXT: store i64 [[TMP62]], i64* [[TMP88]], align 4
|
|
// CHECK8-NEXT: [[TMP89:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 3
|
|
// CHECK8-NEXT: store i8* null, i8** [[TMP89]], align 4
|
|
// CHECK8-NEXT: [[TMP90:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 4
|
|
// CHECK8-NEXT: [[TMP91:%.*]] = bitcast i8** [[TMP90]] to [5 x [10 x double]]**
|
|
// CHECK8-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP91]], align 4
|
|
// CHECK8-NEXT: [[TMP92:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 4
|
|
// CHECK8-NEXT: [[TMP93:%.*]] = bitcast i8** [[TMP92]] to [5 x [10 x double]]**
|
|
// CHECK8-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP93]], align 4
|
|
// CHECK8-NEXT: [[TMP94:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4
|
|
// CHECK8-NEXT: store i64 400, i64* [[TMP94]], align 4
|
|
// CHECK8-NEXT: [[TMP95:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 4
|
|
// CHECK8-NEXT: store i8* null, i8** [[TMP95]], align 4
|
|
// CHECK8-NEXT: [[TMP96:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 5
|
|
// CHECK8-NEXT: [[TMP97:%.*]] = bitcast i8** [[TMP96]] to i32*
|
|
// CHECK8-NEXT: store i32 5, i32* [[TMP97]], align 4
|
|
// CHECK8-NEXT: [[TMP98:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 5
|
|
// CHECK8-NEXT: [[TMP99:%.*]] = bitcast i8** [[TMP98]] to i32*
|
|
// CHECK8-NEXT: store i32 5, i32* [[TMP99]], align 4
|
|
// CHECK8-NEXT: [[TMP100:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 5
|
|
// CHECK8-NEXT: store i64 4, i64* [[TMP100]], align 4
|
|
// CHECK8-NEXT: [[TMP101:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 5
|
|
// CHECK8-NEXT: store i8* null, i8** [[TMP101]], align 4
|
|
// CHECK8-NEXT: [[TMP102:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 6
|
|
// CHECK8-NEXT: [[TMP103:%.*]] = bitcast i8** [[TMP102]] to i32*
|
|
// CHECK8-NEXT: store i32 [[TMP3]], i32* [[TMP103]], align 4
|
|
// CHECK8-NEXT: [[TMP104:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 6
|
|
// CHECK8-NEXT: [[TMP105:%.*]] = bitcast i8** [[TMP104]] to i32*
|
|
// CHECK8-NEXT: store i32 [[TMP3]], i32* [[TMP105]], align 4
|
|
// CHECK8-NEXT: [[TMP106:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 6
|
|
// CHECK8-NEXT: store i64 4, i64* [[TMP106]], align 4
|
|
// CHECK8-NEXT: [[TMP107:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 6
|
|
// CHECK8-NEXT: store i8* null, i8** [[TMP107]], align 4
|
|
// CHECK8-NEXT: [[TMP108:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 7
|
|
// CHECK8-NEXT: [[TMP109:%.*]] = bitcast i8** [[TMP108]] to double**
|
|
// CHECK8-NEXT: store double* [[VLA1]], double** [[TMP109]], align 4
|
|
// CHECK8-NEXT: [[TMP110:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 7
|
|
// CHECK8-NEXT: [[TMP111:%.*]] = bitcast i8** [[TMP110]] to double**
|
|
// CHECK8-NEXT: store double* [[VLA1]], double** [[TMP111]], align 4
|
|
// CHECK8-NEXT: [[TMP112:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7
|
|
// CHECK8-NEXT: store i64 [[TMP65]], i64* [[TMP112]], align 4
|
|
// CHECK8-NEXT: [[TMP113:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 7
|
|
// CHECK8-NEXT: store i8* null, i8** [[TMP113]], align 4
|
|
// CHECK8-NEXT: [[TMP114:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 8
|
|
// CHECK8-NEXT: [[TMP115:%.*]] = bitcast i8** [[TMP114]] to %struct.TT**
|
|
// CHECK8-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP115]], align 4
|
|
// CHECK8-NEXT: [[TMP116:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 8
|
|
// CHECK8-NEXT: [[TMP117:%.*]] = bitcast i8** [[TMP116]] to %struct.TT**
|
|
// CHECK8-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP117]], align 4
|
|
// CHECK8-NEXT: [[TMP118:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 8
|
|
// CHECK8-NEXT: store i64 12, i64* [[TMP118]], align 4
|
|
// CHECK8-NEXT: [[TMP119:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 8
|
|
// CHECK8-NEXT: store i8* null, i8** [[TMP119]], align 4
|
|
// CHECK8-NEXT: [[TMP120:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 9
|
|
// CHECK8-NEXT: [[TMP121:%.*]] = bitcast i8** [[TMP120]] to i32*
|
|
// CHECK8-NEXT: store i32 [[TMP59]], i32* [[TMP121]], align 4
|
|
// CHECK8-NEXT: [[TMP122:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 9
|
|
// CHECK8-NEXT: [[TMP123:%.*]] = bitcast i8** [[TMP122]] to i32*
|
|
// CHECK8-NEXT: store i32 [[TMP59]], i32* [[TMP123]], align 4
|
|
// CHECK8-NEXT: [[TMP124:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 9
|
|
// CHECK8-NEXT: store i64 4, i64* [[TMP124]], align 4
|
|
// CHECK8-NEXT: [[TMP125:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 9
|
|
// CHECK8-NEXT: store i8* null, i8** [[TMP125]], align 4
|
|
// CHECK8-NEXT: [[TMP126:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 0
|
|
// CHECK8-NEXT: [[TMP127:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 0
|
|
// CHECK8-NEXT: [[TMP128:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
|
|
// CHECK8-NEXT: [[TMP129:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140.region_id, i32 10, i8** [[TMP126]], i8** [[TMP127]], i64* [[TMP128]], i64* getelementptr inbounds ([10 x i64], [10 x i64]* @.offload_maptypes.8, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
|
|
// CHECK8-NEXT: [[TMP130:%.*]] = icmp ne i32 [[TMP129]], 0
|
|
// CHECK8-NEXT: br i1 [[TMP130]], label [[OMP_OFFLOAD_FAILED17:%.*]], label [[OMP_OFFLOAD_CONT18:%.*]]
|
|
// CHECK8: omp_offload.failed17:
|
|
// CHECK8-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140(i32 [[TMP57]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]], i32 [[TMP59]]) #[[ATTR4]]
|
|
// CHECK8-NEXT: br label [[OMP_OFFLOAD_CONT18]]
|
|
// CHECK8: omp_offload.cont18:
|
|
// CHECK8-NEXT: br label [[OMP_IF_END20:%.*]]
|
|
// CHECK8: omp_if.else19:
|
|
// CHECK8-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140(i32 [[TMP57]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]], i32 [[TMP59]]) #[[ATTR4]]
|
|
// CHECK8-NEXT: br label [[OMP_IF_END20]]
|
|
// CHECK8: omp_if.end20:
|
|
// CHECK8-NEXT: [[TMP131:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK8-NEXT: [[TMP132:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
|
|
// CHECK8-NEXT: call void @llvm.stackrestore(i8* [[TMP132]])
|
|
// CHECK8-NEXT: ret i32 [[TMP131]]
|
|
//
|
|
//
|
|
// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96
|
|
// CHECK8-SAME: () #[[ATTR2:[0-9]+]] {
|
|
// CHECK8-NEXT: entry:
|
|
// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
|
|
// CHECK8-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined.
|
|
// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] {
|
|
// CHECK8-NEXT: entry:
|
|
// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4
|
|
// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK8-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
|
|
// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
|
|
// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5
|
|
// CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK8: cond.true:
|
|
// CHECK8-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK8: cond.false:
|
|
// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK8-NEXT: br label [[COND_END]]
|
|
// CHECK8: cond.end:
|
|
// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
|
|
// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK8-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK8: omp.inner.for.cond:
|
|
// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
|
|
// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !11
|
|
// CHECK8-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
|
|
// CHECK8-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK8: omp.inner.for.body:
|
|
// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
|
|
// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5
|
|
// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]]
|
|
// CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11
|
|
// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK8: omp.body.continue:
|
|
// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK8: omp.inner.for.inc:
|
|
// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
|
|
// CHECK8-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
|
|
// CHECK8-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
|
|
// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]
|
|
// CHECK8: omp.inner.for.end:
|
|
// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK8: omp.loop.exit:
|
|
// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
|
|
// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK8-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0
|
|
// CHECK8-NEXT: br i1 [[TMP10]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
|
|
// CHECK8: .omp.final.then:
|
|
// CHECK8-NEXT: store i32 33, i32* [[I]], align 4
|
|
// CHECK8-NEXT: br label [[DOTOMP_FINAL_DONE]]
|
|
// CHECK8: .omp.final.done:
|
|
// CHECK8-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK8-LABEL: define {{[^@]+}}@.omp_task_entry.
|
|
// CHECK8-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] {
|
|
// CHECK8-NEXT: entry:
|
|
// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
|
|
// CHECK8-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 4
|
|
// CHECK8-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 4
|
|
// CHECK8-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 4
|
|
// CHECK8-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 4
|
|
// CHECK8-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 4
|
|
// CHECK8-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4
|
|
// CHECK8-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 4
|
|
// CHECK8-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4
|
|
// CHECK8-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4
|
|
// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4
|
|
// CHECK8-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4
|
|
// CHECK8-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
|
|
// CHECK8-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
|
|
// CHECK8-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0
|
|
// CHECK8-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 4
|
|
// CHECK8-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon*
|
|
// CHECK8-NEXT: [[TMP9:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8*
|
|
// CHECK8-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META17:![0-9]+]])
|
|
// CHECK8-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]])
|
|
// CHECK8-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META22:![0-9]+]])
|
|
// CHECK8-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META24:![0-9]+]])
|
|
// CHECK8-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !26
|
|
// CHECK8-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 4, !noalias !26
|
|
// CHECK8-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !26
|
|
// CHECK8-NEXT: store void (i8*, ...)* null, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !26
|
|
// CHECK8-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 4, !noalias !26
|
|
// CHECK8-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !26
|
|
// CHECK8-NEXT: [[TMP10:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !26
|
|
// CHECK8-NEXT: [[TMP11:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 0, i32 0, i8* null, i32 0, i8* null) #[[ATTR4]]
|
|
// CHECK8-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
|
|
// CHECK8-NEXT: br i1 [[TMP12]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]]
|
|
// CHECK8: omp_offload.failed.i:
|
|
// CHECK8-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96() #[[ATTR4]]
|
|
// CHECK8-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]]
|
|
// CHECK8: .omp_outlined..1.exit:
|
|
// CHECK8-NEXT: ret i32 0
|
|
//
|
|
//
|
|
// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101
|
|
// CHECK8-SAME: (i32 [[A:%.*]], i64* nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR3]] {
|
|
// CHECK8-NEXT: entry:
|
|
// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK8-NEXT: [[K_ADDR:%.*]] = alloca i64*, align 4
|
|
// CHECK8-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK8-NEXT: store i64* [[K]], i64** [[K_ADDR]], align 4
|
|
// CHECK8-NEXT: [[TMP0:%.*]] = load i64*, i64** [[K_ADDR]], align 4
|
|
// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK8-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
|
|
// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
|
|
// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i64*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP2]], i64* [[TMP0]])
|
|
// CHECK8-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..2
|
|
// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i64* nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR3]] {
|
|
// CHECK8-NEXT: entry:
|
|
// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK8-NEXT: [[K_ADDR:%.*]] = alloca i64*, align 4
|
|
// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK8-NEXT: [[DOTLINEAR_START:%.*]] = alloca i64, align 8
|
|
// CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4
|
|
// CHECK8-NEXT: [[K1:%.*]] = alloca i64, align 8
|
|
// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK8-NEXT: store i64* [[K]], i64** [[K_ADDR]], align 4
|
|
// CHECK8-NEXT: [[TMP0:%.*]] = load i64*, i64** [[K_ADDR]], align 4
|
|
// CHECK8-NEXT: [[TMP1:%.*]] = load i64, i64* [[TMP0]], align 8
|
|
// CHECK8-NEXT: store i64 [[TMP1]], i64* [[DOTLINEAR_START]], align 8
|
|
// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK8-NEXT: store i32 8, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK8-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
|
|
// CHECK8-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP3]])
|
|
// CHECK8-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 1073741859, i32 0, i32 8, i32 1, i32 1)
|
|
// CHECK8-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
|
|
// CHECK8: omp.dispatch.cond:
|
|
// CHECK8-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
|
|
// CHECK8-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP4]], 0
|
|
// CHECK8-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
|
|
// CHECK8: omp.dispatch.body:
|
|
// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK8-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK8: omp.inner.for.cond:
|
|
// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27
|
|
// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !27
|
|
// CHECK8-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
|
|
// CHECK8-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK8: omp.inner.for.body:
|
|
// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27
|
|
// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
|
|
// CHECK8-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL]]
|
|
// CHECK8-NEXT: store i32 [[SUB]], i32* [[I]], align 4, !llvm.access.group !27
|
|
// CHECK8-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8, !llvm.access.group !27
|
|
// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27
|
|
// CHECK8-NEXT: [[MUL2:%.*]] = mul nsw i32 [[TMP10]], 3
|
|
// CHECK8-NEXT: [[CONV:%.*]] = sext i32 [[MUL2]] to i64
|
|
// CHECK8-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP9]], [[CONV]]
|
|
// CHECK8-NEXT: store i64 [[ADD]], i64* [[K1]], align 8, !llvm.access.group !27
|
|
// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !27
|
|
// CHECK8-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP11]], 1
|
|
// CHECK8-NEXT: store i32 [[ADD3]], i32* [[A_ADDR]], align 4, !llvm.access.group !27
|
|
// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK8: omp.body.continue:
|
|
// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK8: omp.inner.for.inc:
|
|
// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27
|
|
// CHECK8-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1
|
|
// CHECK8-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27
|
|
// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]]
|
|
// CHECK8: omp.inner.for.end:
|
|
// CHECK8-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
|
|
// CHECK8: omp.dispatch.inc:
|
|
// CHECK8-NEXT: br label [[OMP_DISPATCH_COND]]
|
|
// CHECK8: omp.dispatch.end:
|
|
// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK8-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
|
|
// CHECK8-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
|
|
// CHECK8: .omp.final.then:
|
|
// CHECK8-NEXT: store i32 1, i32* [[I]], align 4
|
|
// CHECK8-NEXT: br label [[DOTOMP_FINAL_DONE]]
|
|
// CHECK8: .omp.final.done:
|
|
// CHECK8-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK8-NEXT: [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0
|
|
// CHECK8-NEXT: br i1 [[TMP16]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
|
|
// CHECK8: .omp.linear.pu:
|
|
// CHECK8-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8
|
|
// CHECK8-NEXT: [[ADD5:%.*]] = add nsw i64 [[TMP17]], 27
|
|
// CHECK8-NEXT: store i64 [[ADD5]], i64* [[TMP0]], align 8
|
|
// CHECK8-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]]
|
|
// CHECK8: .omp.linear.pu.done:
|
|
// CHECK8-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108
|
|
// CHECK8-SAME: (i32 [[AA:%.*]], i32 [[LIN:%.*]], i32 [[A:%.*]]) #[[ATTR2]] {
|
|
// CHECK8-NEXT: entry:
|
|
// CHECK8-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK8-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK8-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK8-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK8-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK8-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
|
|
// CHECK8-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4
|
|
// CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK8-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
|
|
// CHECK8-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
|
|
// CHECK8-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
|
|
// CHECK8-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
|
|
// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
|
|
// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[LIN_ADDR]], align 4
|
|
// CHECK8-NEXT: store i32 [[TMP2]], i32* [[LIN_CASTED]], align 4
|
|
// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[LIN_CASTED]], align 4
|
|
// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK8-NEXT: store i32 [[TMP4]], i32* [[A_CASTED]], align 4
|
|
// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[A_CASTED]], align 4
|
|
// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]])
|
|
// CHECK8-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..3
|
|
// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]], i32 [[LIN:%.*]], i32 [[A:%.*]]) #[[ATTR3]] {
|
|
// CHECK8-NEXT: entry:
|
|
// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK8-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK8-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
|
|
// CHECK8-NEXT: [[TMP:%.*]] = alloca i64, align 4
|
|
// CHECK8-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4
|
|
// CHECK8-NEXT: [[DOTLINEAR_START1:%.*]] = alloca i32, align 4
|
|
// CHECK8-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8
|
|
// CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
|
|
// CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
|
|
// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
|
|
// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK8-NEXT: [[IT:%.*]] = alloca i64, align 8
|
|
// CHECK8-NEXT: [[LIN2:%.*]] = alloca i32, align 4
|
|
// CHECK8-NEXT: [[A3:%.*]] = alloca i32, align 4
|
|
// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK8-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
|
|
// CHECK8-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4
|
|
// CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK8-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
|
|
// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[LIN_ADDR]], align 4
|
|
// CHECK8-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4
|
|
// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK8-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START1]], align 4
|
|
// CHECK8-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv()
|
|
// CHECK8-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8
|
|
// CHECK8-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK8-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK8-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
|
|
// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK8-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
|
|
// CHECK8-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3]], i32 [[TMP3]])
|
|
// CHECK8-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
|
|
// CHECK8-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK8-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3
|
|
// CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK8: cond.true:
|
|
// CHECK8-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK8: cond.false:
|
|
// CHECK8-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK8-NEXT: br label [[COND_END]]
|
|
// CHECK8: cond.end:
|
|
// CHECK8-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
|
|
// CHECK8-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
|
|
// CHECK8-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK8-NEXT: store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK8: omp.inner.for.cond:
|
|
// CHECK8-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !30
|
|
// CHECK8-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !30
|
|
// CHECK8-NEXT: [[CMP4:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]]
|
|
// CHECK8-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK8: omp.inner.for.body:
|
|
// CHECK8-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !30
|
|
// CHECK8-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400
|
|
// CHECK8-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]
|
|
// CHECK8-NEXT: store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !30
|
|
// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4, !llvm.access.group !30
|
|
// CHECK8-NEXT: [[CONV5:%.*]] = sext i32 [[TMP10]] to i64
|
|
// CHECK8-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !30
|
|
// CHECK8-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !30
|
|
// CHECK8-NEXT: [[MUL6:%.*]] = mul i64 [[TMP11]], [[TMP12]]
|
|
// CHECK8-NEXT: [[ADD:%.*]] = add i64 [[CONV5]], [[MUL6]]
|
|
// CHECK8-NEXT: [[CONV7:%.*]] = trunc i64 [[ADD]] to i32
|
|
// CHECK8-NEXT: store i32 [[CONV7]], i32* [[LIN2]], align 4, !llvm.access.group !30
|
|
// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START1]], align 4, !llvm.access.group !30
|
|
// CHECK8-NEXT: [[CONV8:%.*]] = sext i32 [[TMP13]] to i64
|
|
// CHECK8-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !30
|
|
// CHECK8-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !30
|
|
// CHECK8-NEXT: [[MUL9:%.*]] = mul i64 [[TMP14]], [[TMP15]]
|
|
// CHECK8-NEXT: [[ADD10:%.*]] = add i64 [[CONV8]], [[MUL9]]
|
|
// CHECK8-NEXT: [[CONV11:%.*]] = trunc i64 [[ADD10]] to i32
|
|
// CHECK8-NEXT: store i32 [[CONV11]], i32* [[A3]], align 4, !llvm.access.group !30
|
|
// CHECK8-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !30
|
|
// CHECK8-NEXT: [[CONV12:%.*]] = sext i16 [[TMP16]] to i32
|
|
// CHECK8-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1
|
|
// CHECK8-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16
|
|
// CHECK8-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 4, !llvm.access.group !30
|
|
// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK8: omp.body.continue:
|
|
// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK8: omp.inner.for.inc:
|
|
// CHECK8-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !30
|
|
// CHECK8-NEXT: [[ADD15:%.*]] = add i64 [[TMP17]], 1
|
|
// CHECK8-NEXT: store i64 [[ADD15]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !30
|
|
// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP31:![0-9]+]]
|
|
// CHECK8: omp.inner.for.end:
|
|
// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK8: omp.loop.exit:
|
|
// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
|
|
// CHECK8-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK8-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
|
|
// CHECK8-NEXT: br i1 [[TMP19]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
|
|
// CHECK8: .omp.final.then:
|
|
// CHECK8-NEXT: store i64 400, i64* [[IT]], align 8
|
|
// CHECK8-NEXT: br label [[DOTOMP_FINAL_DONE]]
|
|
// CHECK8: .omp.final.done:
|
|
// CHECK8-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK8-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0
|
|
// CHECK8-NEXT: br i1 [[TMP21]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
|
|
// CHECK8: .omp.linear.pu:
|
|
// CHECK8-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4
|
|
// CHECK8-NEXT: [[CONV16:%.*]] = sext i32 [[TMP22]] to i64
|
|
// CHECK8-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
|
|
// CHECK8-NEXT: [[MUL17:%.*]] = mul i64 4, [[TMP23]]
|
|
// CHECK8-NEXT: [[ADD18:%.*]] = add i64 [[CONV16]], [[MUL17]]
|
|
// CHECK8-NEXT: [[CONV19:%.*]] = trunc i64 [[ADD18]] to i32
|
|
// CHECK8-NEXT: store i32 [[CONV19]], i32* [[LIN_ADDR]], align 4
|
|
// CHECK8-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTLINEAR_START1]], align 4
|
|
// CHECK8-NEXT: [[CONV20:%.*]] = sext i32 [[TMP24]] to i64
|
|
// CHECK8-NEXT: [[TMP25:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
|
|
// CHECK8-NEXT: [[MUL21:%.*]] = mul i64 4, [[TMP25]]
|
|
// CHECK8-NEXT: [[ADD22:%.*]] = add i64 [[CONV20]], [[MUL21]]
|
|
// CHECK8-NEXT: [[CONV23:%.*]] = trunc i64 [[ADD22]] to i32
|
|
// CHECK8-NEXT: store i32 [[CONV23]], i32* [[A_ADDR]], align 4
|
|
// CHECK8-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]]
|
|
// CHECK8: .omp.linear.pu.done:
|
|
// CHECK8-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116
|
|
// CHECK8-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] {
|
|
// CHECK8-NEXT: entry:
|
|
// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK8-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK8-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK8-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK8-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
|
|
// CHECK8-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
|
|
// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK8-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
|
|
// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
|
|
// CHECK8-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
|
|
// CHECK8-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
|
|
// CHECK8-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
|
|
// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
|
|
// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]])
|
|
// CHECK8-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..4
|
|
// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR3]] {
|
|
// CHECK8-NEXT: entry:
|
|
// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK8-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK8-NEXT: [[TMP:%.*]] = alloca i16, align 2
|
|
// CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK8-NEXT: [[IT:%.*]] = alloca i16, align 2
|
|
// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK8-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
|
|
// CHECK8-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
|
|
// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK8-NEXT: store i32 3, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
|
|
// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
|
|
// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3
|
|
// CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK8: cond.true:
|
|
// CHECK8-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK8: cond.false:
|
|
// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK8-NEXT: br label [[COND_END]]
|
|
// CHECK8: cond.end:
|
|
// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
|
|
// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK8-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK8: omp.inner.for.cond:
|
|
// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33
|
|
// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !33
|
|
// CHECK8-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
|
|
// CHECK8-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK8: omp.inner.for.body:
|
|
// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33
|
|
// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4
|
|
// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]]
|
|
// CHECK8-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
|
|
// CHECK8-NEXT: store i16 [[CONV2]], i16* [[IT]], align 2, !llvm.access.group !33
|
|
// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !33
|
|
// CHECK8-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1
|
|
// CHECK8-NEXT: store i32 [[ADD3]], i32* [[A_ADDR]], align 4, !llvm.access.group !33
|
|
// CHECK8-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !33
|
|
// CHECK8-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32
|
|
// CHECK8-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
|
|
// CHECK8-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
|
|
// CHECK8-NEXT: store i16 [[CONV6]], i16* [[CONV]], align 4, !llvm.access.group !33
|
|
// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK8: omp.body.continue:
|
|
// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK8: omp.inner.for.inc:
|
|
// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33
|
|
// CHECK8-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1
|
|
// CHECK8-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33
|
|
// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP34:![0-9]+]]
|
|
// CHECK8: omp.inner.for.end:
|
|
// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK8: omp.loop.exit:
|
|
// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
|
|
// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK8-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
|
|
// CHECK8-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
|
|
// CHECK8: .omp.final.then:
|
|
// CHECK8-NEXT: store i16 22, i16* [[IT]], align 2
|
|
// CHECK8-NEXT: br label [[DOTOMP_FINAL_DONE]]
|
|
// CHECK8: .omp.final.done:
|
|
// CHECK8-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140
|
|
// CHECK8-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] {
|
|
// CHECK8-NEXT: entry:
|
|
// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK8-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
|
|
// CHECK8-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK8-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4
|
|
// CHECK8-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
|
|
// CHECK8-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
|
|
// CHECK8-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4
|
|
// CHECK8-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4
|
|
// CHECK8-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
|
|
// CHECK8-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK8-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK8-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK8-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
|
|
// CHECK8-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
|
|
// CHECK8-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4
|
|
// CHECK8-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
|
|
// CHECK8-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
|
|
// CHECK8-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
|
|
// CHECK8-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4
|
|
// CHECK8-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
|
|
// CHECK8-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK8-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
|
|
// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
|
|
// CHECK8-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
|
|
// CHECK8-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
|
|
// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
|
|
// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
|
|
// CHECK8-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
|
|
// CHECK8-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
|
|
// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK8-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4
|
|
// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4
|
|
// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK8-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
|
|
// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
|
|
// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*, i32)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i32 [[TMP11]])
|
|
// CHECK8-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..7
|
|
// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] {
|
|
// CHECK8-NEXT: entry:
|
|
// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK8-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
|
|
// CHECK8-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK8-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4
|
|
// CHECK8-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
|
|
// CHECK8-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
|
|
// CHECK8-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4
|
|
// CHECK8-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4
|
|
// CHECK8-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
|
|
// CHECK8-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK8-NEXT: [[TMP:%.*]] = alloca i8, align 1
|
|
// CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK8-NEXT: [[IT:%.*]] = alloca i8, align 1
|
|
// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK8-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
|
|
// CHECK8-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
|
|
// CHECK8-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4
|
|
// CHECK8-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
|
|
// CHECK8-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
|
|
// CHECK8-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
|
|
// CHECK8-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4
|
|
// CHECK8-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
|
|
// CHECK8-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK8-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
|
|
// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
|
|
// CHECK8-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
|
|
// CHECK8-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
|
|
// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
|
|
// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
|
|
// CHECK8-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
|
|
// CHECK8-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
|
|
// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK8-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK8-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
|
|
// CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
|
|
// CHECK8-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
|
|
// CHECK8: omp.dispatch.cond:
|
|
// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25
|
|
// CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK8: cond.true:
|
|
// CHECK8-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK8: cond.false:
|
|
// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK8-NEXT: br label [[COND_END]]
|
|
// CHECK8: cond.end:
|
|
// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
|
|
// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK8-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK8-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK8-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK8-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
|
|
// CHECK8-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
|
|
// CHECK8: omp.dispatch.body:
|
|
// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK8: omp.inner.for.cond:
|
|
// CHECK8-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36
|
|
// CHECK8-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !36
|
|
// CHECK8-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
|
|
// CHECK8-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK8: omp.inner.for.body:
|
|
// CHECK8-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36
|
|
// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
|
|
// CHECK8-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]]
|
|
// CHECK8-NEXT: [[CONV:%.*]] = trunc i32 [[SUB]] to i8
|
|
// CHECK8-NEXT: store i8 [[CONV]], i8* [[IT]], align 1, !llvm.access.group !36
|
|
// CHECK8-NEXT: [[TMP19:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !36
|
|
// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1
|
|
// CHECK8-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4, !llvm.access.group !36
|
|
// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2
|
|
// CHECK8-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !36
|
|
// CHECK8-NEXT: [[CONV7:%.*]] = fpext float [[TMP20]] to double
|
|
// CHECK8-NEXT: [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00
|
|
// CHECK8-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float
|
|
// CHECK8-NEXT: store float [[CONV9]], float* [[ARRAYIDX]], align 4, !llvm.access.group !36
|
|
// CHECK8-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3
|
|
// CHECK8-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX10]], align 4, !llvm.access.group !36
|
|
// CHECK8-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double
|
|
// CHECK8-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00
|
|
// CHECK8-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float
|
|
// CHECK8-NEXT: store float [[CONV13]], float* [[ARRAYIDX10]], align 4, !llvm.access.group !36
|
|
// CHECK8-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1
|
|
// CHECK8-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX14]], i32 0, i32 2
|
|
// CHECK8-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX15]], align 8, !llvm.access.group !36
|
|
// CHECK8-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00
|
|
// CHECK8-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8, !llvm.access.group !36
|
|
// CHECK8-NEXT: [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]]
|
|
// CHECK8-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP23]]
|
|
// CHECK8-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX17]], i32 3
|
|
// CHECK8-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX18]], align 8, !llvm.access.group !36
|
|
// CHECK8-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00
|
|
// CHECK8-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8, !llvm.access.group !36
|
|
// CHECK8-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0
|
|
// CHECK8-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 4, !llvm.access.group !36
|
|
// CHECK8-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1
|
|
// CHECK8-NEXT: store i64 [[ADD20]], i64* [[X]], align 4, !llvm.access.group !36
|
|
// CHECK8-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1
|
|
// CHECK8-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 4, !llvm.access.group !36
|
|
// CHECK8-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i32
|
|
// CHECK8-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1
|
|
// CHECK8-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8
|
|
// CHECK8-NEXT: store i8 [[CONV23]], i8* [[Y]], align 4, !llvm.access.group !36
|
|
// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK8: omp.body.continue:
|
|
// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK8: omp.inner.for.inc:
|
|
// CHECK8-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36
|
|
// CHECK8-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1
|
|
// CHECK8-NEXT: store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36
|
|
// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP37:![0-9]+]]
|
|
// CHECK8: omp.inner.for.end:
|
|
// CHECK8-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
|
|
// CHECK8: omp.dispatch.inc:
|
|
// CHECK8-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK8-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK8-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]
|
|
// CHECK8-NEXT: store i32 [[ADD25]], i32* [[DOTOMP_LB]], align 4
|
|
// CHECK8-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK8-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK8-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]]
|
|
// CHECK8-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK8-NEXT: br label [[OMP_DISPATCH_COND]]
|
|
// CHECK8: omp.dispatch.end:
|
|
// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]])
|
|
// CHECK8-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK8-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0
|
|
// CHECK8-NEXT: br i1 [[TMP33]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
|
|
// CHECK8: .omp.final.then:
|
|
// CHECK8-NEXT: store i8 96, i8* [[IT]], align 1
|
|
// CHECK8-NEXT: br label [[DOTOMP_FINAL_DONE]]
|
|
// CHECK8: .omp.final.done:
|
|
// CHECK8-NEXT: ret void
|
|
//
|
|
//
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// CHECK8-LABEL: define {{[^@]+}}@_Z3bari
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// CHECK8-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
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// CHECK8-NEXT: entry:
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// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
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// CHECK8-NEXT: [[A:%.*]] = alloca i32, align 4
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// CHECK8-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4
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// CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
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// CHECK8-NEXT: store i32 0, i32* [[A]], align 4
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// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
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// CHECK8-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]])
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// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4
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// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
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// CHECK8-NEXT: store i32 [[ADD]], i32* [[A]], align 4
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// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
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// CHECK8-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]])
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// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4
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// CHECK8-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
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// CHECK8-NEXT: store i32 [[ADD2]], i32* [[A]], align 4
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// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
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// CHECK8-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]])
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// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4
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// CHECK8-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
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// CHECK8-NEXT: store i32 [[ADD4]], i32* [[A]], align 4
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// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
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// CHECK8-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]])
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// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4
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// CHECK8-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
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// CHECK8-NEXT: store i32 [[ADD6]], i32* [[A]], align 4
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// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4
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// CHECK8-NEXT: ret i32 [[TMP8]]
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//
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//
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// CHECK8-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
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// CHECK8-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 {
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// CHECK8-NEXT: entry:
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// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
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// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
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// CHECK8-NEXT: [[B:%.*]] = alloca i32, align 4
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// CHECK8-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4
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// CHECK8-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4
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// CHECK8-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
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// CHECK8-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4
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// CHECK8-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
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// CHECK8-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [6 x i8*], align 4
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// CHECK8-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [6 x i8*], align 4
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// CHECK8-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [6 x i8*], align 4
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// CHECK8-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [6 x i64], align 4
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// CHECK8-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
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// CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
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// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
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// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
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// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
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// CHECK8-NEXT: store i32 [[ADD]], i32* [[B]], align 4
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// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
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// CHECK8-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave()
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// CHECK8-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4
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// CHECK8-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]]
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// CHECK8-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2
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// CHECK8-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4
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// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
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// CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 60
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// CHECK8-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8
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// CHECK8-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
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// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4
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// CHECK8-NEXT: store i32 [[TMP5]], i32* [[B_CASTED]], align 4
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// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4
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// CHECK8-NEXT: [[TMP7:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
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// CHECK8-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP7]] to i1
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// CHECK8-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__CASTED]] to i8*
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// CHECK8-NEXT: [[FROMBOOL2:%.*]] = zext i1 [[TOBOOL]] to i8
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// CHECK8-NEXT: store i8 [[FROMBOOL2]], i8* [[CONV]], align 1
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|
// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
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// CHECK8-NEXT: [[TMP9:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
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// CHECK8-NEXT: [[TOBOOL3:%.*]] = trunc i8 [[TMP9]] to i1
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// CHECK8-NEXT: br i1 [[TOBOOL3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
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// CHECK8: omp_if.then:
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// CHECK8-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
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// CHECK8-NEXT: [[TMP10:%.*]] = mul nuw i32 2, [[TMP1]]
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// CHECK8-NEXT: [[TMP11:%.*]] = mul nuw i32 [[TMP10]], 2
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// CHECK8-NEXT: [[TMP12:%.*]] = sext i32 [[TMP11]] to i64
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// CHECK8-NEXT: [[TMP13:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
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// CHECK8-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to %struct.S1**
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// CHECK8-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP14]], align 4
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// CHECK8-NEXT: [[TMP15:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
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// CHECK8-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to double**
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// CHECK8-NEXT: store double* [[A]], double** [[TMP16]], align 4
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// CHECK8-NEXT: [[TMP17:%.*]] = getelementptr inbounds [6 x i64], [6 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
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// CHECK8-NEXT: store i64 8, i64* [[TMP17]], align 4
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// CHECK8-NEXT: [[TMP18:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
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// CHECK8-NEXT: store i8* null, i8** [[TMP18]], align 4
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// CHECK8-NEXT: [[TMP19:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
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// CHECK8-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32*
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|
// CHECK8-NEXT: store i32 [[TMP6]], i32* [[TMP20]], align 4
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|
// CHECK8-NEXT: [[TMP21:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
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|
// CHECK8-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i32*
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|
// CHECK8-NEXT: store i32 [[TMP6]], i32* [[TMP22]], align 4
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|
// CHECK8-NEXT: [[TMP23:%.*]] = getelementptr inbounds [6 x i64], [6 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1
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|
// CHECK8-NEXT: store i64 4, i64* [[TMP23]], align 4
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// CHECK8-NEXT: [[TMP24:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
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// CHECK8-NEXT: store i8* null, i8** [[TMP24]], align 4
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// CHECK8-NEXT: [[TMP25:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
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// CHECK8-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i32*
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// CHECK8-NEXT: store i32 2, i32* [[TMP26]], align 4
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// CHECK8-NEXT: [[TMP27:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
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// CHECK8-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i32*
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// CHECK8-NEXT: store i32 2, i32* [[TMP28]], align 4
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// CHECK8-NEXT: [[TMP29:%.*]] = getelementptr inbounds [6 x i64], [6 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2
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// CHECK8-NEXT: store i64 4, i64* [[TMP29]], align 4
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// CHECK8-NEXT: [[TMP30:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
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// CHECK8-NEXT: store i8* null, i8** [[TMP30]], align 4
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// CHECK8-NEXT: [[TMP31:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
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// CHECK8-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i32*
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// CHECK8-NEXT: store i32 [[TMP1]], i32* [[TMP32]], align 4
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// CHECK8-NEXT: [[TMP33:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
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// CHECK8-NEXT: [[TMP34:%.*]] = bitcast i8** [[TMP33]] to i32*
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// CHECK8-NEXT: store i32 [[TMP1]], i32* [[TMP34]], align 4
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// CHECK8-NEXT: [[TMP35:%.*]] = getelementptr inbounds [6 x i64], [6 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3
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// CHECK8-NEXT: store i64 4, i64* [[TMP35]], align 4
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// CHECK8-NEXT: [[TMP36:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
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// CHECK8-NEXT: store i8* null, i8** [[TMP36]], align 4
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// CHECK8-NEXT: [[TMP37:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
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|
// CHECK8-NEXT: [[TMP38:%.*]] = bitcast i8** [[TMP37]] to i16**
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|
// CHECK8-NEXT: store i16* [[VLA]], i16** [[TMP38]], align 4
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|
// CHECK8-NEXT: [[TMP39:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
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|
// CHECK8-NEXT: [[TMP40:%.*]] = bitcast i8** [[TMP39]] to i16**
|
|
// CHECK8-NEXT: store i16* [[VLA]], i16** [[TMP40]], align 4
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// CHECK8-NEXT: [[TMP41:%.*]] = getelementptr inbounds [6 x i64], [6 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4
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// CHECK8-NEXT: store i64 [[TMP12]], i64* [[TMP41]], align 4
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// CHECK8-NEXT: [[TMP42:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4
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|
// CHECK8-NEXT: store i8* null, i8** [[TMP42]], align 4
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// CHECK8-NEXT: [[TMP43:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 5
|
|
// CHECK8-NEXT: [[TMP44:%.*]] = bitcast i8** [[TMP43]] to i32*
|
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// CHECK8-NEXT: store i32 [[TMP8]], i32* [[TMP44]], align 4
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// CHECK8-NEXT: [[TMP45:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 5
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|
// CHECK8-NEXT: [[TMP46:%.*]] = bitcast i8** [[TMP45]] to i32*
|
|
// CHECK8-NEXT: store i32 [[TMP8]], i32* [[TMP46]], align 4
|
|
// CHECK8-NEXT: [[TMP47:%.*]] = getelementptr inbounds [6 x i64], [6 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 5
|
|
// CHECK8-NEXT: store i64 1, i64* [[TMP47]], align 4
|
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// CHECK8-NEXT: [[TMP48:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 5
|
|
// CHECK8-NEXT: store i8* null, i8** [[TMP48]], align 4
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// CHECK8-NEXT: [[TMP49:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK8-NEXT: [[TMP50:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
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|
// CHECK8-NEXT: [[TMP51:%.*]] = getelementptr inbounds [6 x i64], [6 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
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|
// CHECK8-NEXT: [[TMP52:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
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// CHECK8-NEXT: [[TOBOOL4:%.*]] = trunc i8 [[TMP52]] to i1
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|
// CHECK8-NEXT: [[TMP53:%.*]] = select i1 [[TOBOOL4]], i32 0, i32 1
|
|
// CHECK8-NEXT: [[TMP54:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214.region_id, i32 6, i8** [[TMP49]], i8** [[TMP50]], i64* [[TMP51]], i64* getelementptr inbounds ([6 x i64], [6 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP53]])
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// CHECK8-NEXT: [[TMP55:%.*]] = icmp ne i32 [[TMP54]], 0
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// CHECK8-NEXT: br i1 [[TMP55]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
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// CHECK8: omp_offload.failed:
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|
// CHECK8-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214(%struct.S1* [[THIS1]], i32 [[TMP6]], i32 2, i32 [[TMP1]], i16* [[VLA]], i32 [[TMP8]]) #[[ATTR4]]
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// CHECK8-NEXT: br label [[OMP_OFFLOAD_CONT]]
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// CHECK8: omp_offload.cont:
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|
// CHECK8-NEXT: br label [[OMP_IF_END:%.*]]
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// CHECK8: omp_if.else:
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|
// CHECK8-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214(%struct.S1* [[THIS1]], i32 [[TMP6]], i32 2, i32 [[TMP1]], i16* [[VLA]], i32 [[TMP8]]) #[[ATTR4]]
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// CHECK8-NEXT: br label [[OMP_IF_END]]
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|
// CHECK8: omp_if.end:
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|
// CHECK8-NEXT: [[TMP56:%.*]] = mul nsw i32 1, [[TMP1]]
|
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// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP56]]
|
|
// CHECK8-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
|
|
// CHECK8-NEXT: [[TMP57:%.*]] = load i16, i16* [[ARRAYIDX5]], align 2
|
|
// CHECK8-NEXT: [[CONV6:%.*]] = sext i16 [[TMP57]] to i32
|
|
// CHECK8-NEXT: [[TMP58:%.*]] = load i32, i32* [[B]], align 4
|
|
// CHECK8-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], [[TMP58]]
|
|
// CHECK8-NEXT: [[TMP59:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
|
|
// CHECK8-NEXT: call void @llvm.stackrestore(i8* [[TMP59]])
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|
// CHECK8-NEXT: ret i32 [[ADD7]]
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|
//
|
|
//
|
|
// CHECK8-LABEL: define {{[^@]+}}@_ZL7fstatici
|
|
// CHECK8-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
|
|
// CHECK8-NEXT: entry:
|
|
// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK8-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK8-NEXT: [[AA:%.*]] = alloca i16, align 2
|
|
// CHECK8-NEXT: [[AAA:%.*]] = alloca i8, align 1
|
|
// CHECK8-NEXT: [[B:%.*]] = alloca [10 x i32], align 4
|
|
// CHECK8-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK8-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK8-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK8-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4
|
|
// CHECK8-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4
|
|
// CHECK8-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4
|
|
// CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK8-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK8-NEXT: store i16 0, i16* [[AA]], align 2
|
|
// CHECK8-NEXT: store i8 0, i8* [[AAA]], align 1
|
|
// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK8-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
|
|
// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
|
|
// CHECK8-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
|
|
// CHECK8-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
|
|
// CHECK8-NEXT: store i16 [[TMP2]], i16* [[CONV]], align 2
|
|
// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
|
|
// CHECK8-NEXT: [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1
|
|
// CHECK8-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
|
|
// CHECK8-NEXT: store i8 [[TMP4]], i8* [[CONV1]], align 1
|
|
// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
|
|
// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50
|
|
// CHECK8-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
|
|
// CHECK8: omp_if.then:
|
|
// CHECK8-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK8-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32*
|
|
// CHECK8-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4
|
|
// CHECK8-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK8-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32*
|
|
// CHECK8-NEXT: store i32 [[TMP1]], i32* [[TMP10]], align 4
|
|
// CHECK8-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
|
|
// CHECK8-NEXT: store i8* null, i8** [[TMP11]], align 4
|
|
// CHECK8-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
|
|
// CHECK8-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32*
|
|
// CHECK8-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4
|
|
// CHECK8-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
|
|
// CHECK8-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32*
|
|
// CHECK8-NEXT: store i32 [[TMP3]], i32* [[TMP15]], align 4
|
|
// CHECK8-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
|
|
// CHECK8-NEXT: store i8* null, i8** [[TMP16]], align 4
|
|
// CHECK8-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
|
|
// CHECK8-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32*
|
|
// CHECK8-NEXT: store i32 [[TMP5]], i32* [[TMP18]], align 4
|
|
// CHECK8-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
|
|
// CHECK8-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32*
|
|
// CHECK8-NEXT: store i32 [[TMP5]], i32* [[TMP20]], align 4
|
|
// CHECK8-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
|
|
// CHECK8-NEXT: store i8* null, i8** [[TMP21]], align 4
|
|
// CHECK8-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
|
|
// CHECK8-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]**
|
|
// CHECK8-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 4
|
|
// CHECK8-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
|
|
// CHECK8-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]**
|
|
// CHECK8-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 4
|
|
// CHECK8-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
|
|
// CHECK8-NEXT: store i8* null, i8** [[TMP26]], align 4
|
|
// CHECK8-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK8-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK8-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
|
|
// CHECK8-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0
|
|
// CHECK8-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
|
// CHECK8: omp_offload.failed:
|
|
// CHECK8-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]]
|
|
// CHECK8-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
|
// CHECK8: omp_offload.cont:
|
|
// CHECK8-NEXT: br label [[OMP_IF_END:%.*]]
|
|
// CHECK8: omp_if.else:
|
|
// CHECK8-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]]
|
|
// CHECK8-NEXT: br label [[OMP_IF_END]]
|
|
// CHECK8: omp_if.end:
|
|
// CHECK8-NEXT: [[TMP31:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK8-NEXT: ret i32 [[TMP31]]
|
|
//
|
|
//
|
|
// CHECK8-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
|
|
// CHECK8-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat {
|
|
// CHECK8-NEXT: entry:
|
|
// CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK8-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK8-NEXT: [[AA:%.*]] = alloca i16, align 2
|
|
// CHECK8-NEXT: [[B:%.*]] = alloca [10 x i32], align 4
|
|
// CHECK8-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK8-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK8-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4
|
|
// CHECK8-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4
|
|
// CHECK8-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4
|
|
// CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK8-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK8-NEXT: store i16 0, i16* [[AA]], align 2
|
|
// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK8-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
|
|
// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
|
|
// CHECK8-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
|
|
// CHECK8-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
|
|
// CHECK8-NEXT: store i16 [[TMP2]], i16* [[CONV]], align 2
|
|
// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
|
|
// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40
|
|
// CHECK8-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
|
|
// CHECK8: omp_if.then:
|
|
// CHECK8-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK8-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i32*
|
|
// CHECK8-NEXT: store i32 [[TMP1]], i32* [[TMP6]], align 4
|
|
// CHECK8-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK8-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32*
|
|
// CHECK8-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4
|
|
// CHECK8-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
|
|
// CHECK8-NEXT: store i8* null, i8** [[TMP9]], align 4
|
|
// CHECK8-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
|
|
// CHECK8-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i32*
|
|
// CHECK8-NEXT: store i32 [[TMP3]], i32* [[TMP11]], align 4
|
|
// CHECK8-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
|
|
// CHECK8-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32*
|
|
// CHECK8-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4
|
|
// CHECK8-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
|
|
// CHECK8-NEXT: store i8* null, i8** [[TMP14]], align 4
|
|
// CHECK8-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
|
|
// CHECK8-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]**
|
|
// CHECK8-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 4
|
|
// CHECK8-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
|
|
// CHECK8-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]**
|
|
// CHECK8-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 4
|
|
// CHECK8-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
|
|
// CHECK8-NEXT: store i8* null, i8** [[TMP19]], align 4
|
|
// CHECK8-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK8-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK8-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.15, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.16, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
|
|
// CHECK8-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0
|
|
// CHECK8-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
|
// CHECK8: omp_offload.failed:
|
|
// CHECK8-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]]
|
|
// CHECK8-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
|
// CHECK8: omp_offload.cont:
|
|
// CHECK8-NEXT: br label [[OMP_IF_END:%.*]]
|
|
// CHECK8: omp_if.else:
|
|
// CHECK8-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]]
|
|
// CHECK8-NEXT: br label [[OMP_IF_END]]
|
|
// CHECK8: omp_if.end:
|
|
// CHECK8-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK8-NEXT: ret i32 [[TMP24]]
|
|
//
|
|
//
|
|
// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214
|
|
// CHECK8-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] {
|
|
// CHECK8-NEXT: entry:
|
|
// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
|
|
// CHECK8-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK8-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK8-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
|
|
// CHECK8-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4
|
|
// CHECK8-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK8-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK8-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK8-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
|
|
// CHECK8-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK8-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4
|
|
// CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]])
|
|
// CHECK8-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK8-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
|
|
// CHECK8-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
|
|
// CHECK8-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
|
|
// CHECK8-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4
|
|
// CHECK8-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK8-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
|
|
// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
|
|
// CHECK8-NEXT: [[TMP4:%.*]] = load i16*, i16** [[C_ADDR]], align 4
|
|
// CHECK8-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8*
|
|
// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_ADDR]], align 4
|
|
// CHECK8-NEXT: store i32 [[TMP5]], i32* [[B_CASTED]], align 4
|
|
// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4
|
|
// CHECK8-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV]], align 4
|
|
// CHECK8-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP7]] to i1
|
|
// CHECK8-NEXT: [[CONV3:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__CASTED]] to i8*
|
|
// CHECK8-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
|
|
// CHECK8-NEXT: store i8 [[FROMBOOL]], i8* [[CONV3]], align 1
|
|
// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
|
|
// CHECK8-NEXT: [[TMP9:%.*]] = load i8, i8* [[CONV]], align 4
|
|
// CHECK8-NEXT: [[TOBOOL4:%.*]] = trunc i8 [[TMP9]] to i1
|
|
// CHECK8-NEXT: br i1 [[TOBOOL4]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
|
|
// CHECK8: omp_if.then:
|
|
// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*, i32)* @.omp_outlined..9 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP6]], i32 [[TMP2]], i32 [[TMP3]], i16* [[TMP4]], i32 [[TMP8]])
|
|
// CHECK8-NEXT: br label [[OMP_IF_END:%.*]]
|
|
// CHECK8: omp_if.else:
|
|
// CHECK8-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]])
|
|
// CHECK8-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
|
|
// CHECK8-NEXT: call void @.omp_outlined..9(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]], i32 [[TMP6]], i32 [[TMP2]], i32 [[TMP3]], i16* [[TMP4]], i32 [[TMP8]]) #[[ATTR4]]
|
|
// CHECK8-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]])
|
|
// CHECK8-NEXT: br label [[OMP_IF_END]]
|
|
// CHECK8: omp_if.end:
|
|
// CHECK8-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..9
|
|
// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] {
|
|
// CHECK8-NEXT: entry:
|
|
// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
|
|
// CHECK8-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK8-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK8-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
|
|
// CHECK8-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4
|
|
// CHECK8-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
|
|
// CHECK8-NEXT: [[TMP:%.*]] = alloca i64, align 4
|
|
// CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
|
|
// CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
|
|
// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
|
|
// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK8-NEXT: [[IT:%.*]] = alloca i64, align 8
|
|
// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK8-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK8-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
|
|
// CHECK8-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
|
|
// CHECK8-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
|
|
// CHECK8-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4
|
|
// CHECK8-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK8-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
|
|
// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
|
|
// CHECK8-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
|
|
// CHECK8-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8*
|
|
// CHECK8-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK8-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK8-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
|
|
// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK8-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV]], align 4
|
|
// CHECK8-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1
|
|
// CHECK8-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
|
|
// CHECK8: omp_if.then:
|
|
// CHECK8-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4
|
|
// CHECK8-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
|
|
// CHECK8-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK8-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP7]], 3
|
|
// CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK8: cond.true:
|
|
// CHECK8-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK8: cond.false:
|
|
// CHECK8-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK8-NEXT: br label [[COND_END]]
|
|
// CHECK8: cond.end:
|
|
// CHECK8-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ]
|
|
// CHECK8-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
|
|
// CHECK8-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK8-NEXT: store i64 [[TMP9]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK8: omp.inner.for.cond:
|
|
// CHECK8-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !39
|
|
// CHECK8-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !39
|
|
// CHECK8-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP10]], [[TMP11]]
|
|
// CHECK8-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK8: omp.inner.for.body:
|
|
// CHECK8-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !39
|
|
// CHECK8-NEXT: [[MUL:%.*]] = mul i64 [[TMP12]], 400
|
|
// CHECK8-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]
|
|
// CHECK8-NEXT: store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !39
|
|
// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[B_ADDR]], align 4, !llvm.access.group !39
|
|
// CHECK8-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP13]] to double
|
|
// CHECK8-NEXT: [[ADD:%.*]] = fadd double [[CONV4]], 1.500000e+00
|
|
// CHECK8-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
|
|
// CHECK8-NEXT: store double [[ADD]], double* [[A]], align 4, !nontemporal !40, !llvm.access.group !39
|
|
// CHECK8-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
|
|
// CHECK8-NEXT: [[TMP14:%.*]] = load double, double* [[A5]], align 4, !nontemporal !40, !llvm.access.group !39
|
|
// CHECK8-NEXT: [[INC:%.*]] = fadd double [[TMP14]], 1.000000e+00
|
|
// CHECK8-NEXT: store double [[INC]], double* [[A5]], align 4, !nontemporal !40, !llvm.access.group !39
|
|
// CHECK8-NEXT: [[CONV6:%.*]] = fptosi double [[INC]] to i16
|
|
// CHECK8-NEXT: [[TMP15:%.*]] = mul nsw i32 1, [[TMP2]]
|
|
// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP15]]
|
|
// CHECK8-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
|
|
// CHECK8-NEXT: store i16 [[CONV6]], i16* [[ARRAYIDX7]], align 2, !llvm.access.group !39
|
|
// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK8: omp.body.continue:
|
|
// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK8: omp.inner.for.inc:
|
|
// CHECK8-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !39
|
|
// CHECK8-NEXT: [[ADD8:%.*]] = add i64 [[TMP16]], 1
|
|
// CHECK8-NEXT: store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !39
|
|
// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP41:![0-9]+]]
|
|
// CHECK8: omp.inner.for.end:
|
|
// CHECK8-NEXT: br label [[OMP_IF_END:%.*]]
|
|
// CHECK8: omp_if.else:
|
|
// CHECK8-NEXT: [[TMP17:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK8-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP17]], align 4
|
|
// CHECK8-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP18]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
|
|
// CHECK8-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK8-NEXT: [[CMP9:%.*]] = icmp ugt i64 [[TMP19]], 3
|
|
// CHECK8-NEXT: br i1 [[CMP9]], label [[COND_TRUE10:%.*]], label [[COND_FALSE11:%.*]]
|
|
// CHECK8: cond.true10:
|
|
// CHECK8-NEXT: br label [[COND_END12:%.*]]
|
|
// CHECK8: cond.false11:
|
|
// CHECK8-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK8-NEXT: br label [[COND_END12]]
|
|
// CHECK8: cond.end12:
|
|
// CHECK8-NEXT: [[COND13:%.*]] = phi i64 [ 3, [[COND_TRUE10]] ], [ [[TMP20]], [[COND_FALSE11]] ]
|
|
// CHECK8-NEXT: store i64 [[COND13]], i64* [[DOTOMP_UB]], align 8
|
|
// CHECK8-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK8-NEXT: store i64 [[TMP21]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND14:%.*]]
|
|
// CHECK8: omp.inner.for.cond14:
|
|
// CHECK8-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK8-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK8-NEXT: [[CMP15:%.*]] = icmp ule i64 [[TMP22]], [[TMP23]]
|
|
// CHECK8-NEXT: br i1 [[CMP15]], label [[OMP_INNER_FOR_BODY16:%.*]], label [[OMP_INNER_FOR_END30:%.*]]
|
|
// CHECK8: omp.inner.for.body16:
|
|
// CHECK8-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK8-NEXT: [[MUL17:%.*]] = mul i64 [[TMP24]], 400
|
|
// CHECK8-NEXT: [[SUB18:%.*]] = sub i64 2000, [[MUL17]]
|
|
// CHECK8-NEXT: store i64 [[SUB18]], i64* [[IT]], align 8
|
|
// CHECK8-NEXT: [[TMP25:%.*]] = load i32, i32* [[B_ADDR]], align 4
|
|
// CHECK8-NEXT: [[CONV19:%.*]] = sitofp i32 [[TMP25]] to double
|
|
// CHECK8-NEXT: [[ADD20:%.*]] = fadd double [[CONV19]], 1.500000e+00
|
|
// CHECK8-NEXT: [[A21:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
|
|
// CHECK8-NEXT: store double [[ADD20]], double* [[A21]], align 4
|
|
// CHECK8-NEXT: [[A22:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
|
|
// CHECK8-NEXT: [[TMP26:%.*]] = load double, double* [[A22]], align 4
|
|
// CHECK8-NEXT: [[INC23:%.*]] = fadd double [[TMP26]], 1.000000e+00
|
|
// CHECK8-NEXT: store double [[INC23]], double* [[A22]], align 4
|
|
// CHECK8-NEXT: [[CONV24:%.*]] = fptosi double [[INC23]] to i16
|
|
// CHECK8-NEXT: [[TMP27:%.*]] = mul nsw i32 1, [[TMP2]]
|
|
// CHECK8-NEXT: [[ARRAYIDX25:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP27]]
|
|
// CHECK8-NEXT: [[ARRAYIDX26:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX25]], i32 1
|
|
// CHECK8-NEXT: store i16 [[CONV24]], i16* [[ARRAYIDX26]], align 2
|
|
// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE27:%.*]]
|
|
// CHECK8: omp.body.continue27:
|
|
// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC28:%.*]]
|
|
// CHECK8: omp.inner.for.inc28:
|
|
// CHECK8-NEXT: [[TMP28:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK8-NEXT: [[ADD29:%.*]] = add i64 [[TMP28]], 1
|
|
// CHECK8-NEXT: store i64 [[ADD29]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND14]], !llvm.loop [[LOOP43:![0-9]+]]
|
|
// CHECK8: omp.inner.for.end30:
|
|
// CHECK8-NEXT: br label [[OMP_IF_END]]
|
|
// CHECK8: omp_if.end:
|
|
// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK8: omp.loop.exit:
|
|
// CHECK8-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK8-NEXT: [[TMP30:%.*]] = load i32, i32* [[TMP29]], align 4
|
|
// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP30]])
|
|
// CHECK8-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK8-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0
|
|
// CHECK8-NEXT: br i1 [[TMP32]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
|
|
// CHECK8: .omp.final.then:
|
|
// CHECK8-NEXT: store i64 400, i64* [[IT]], align 8
|
|
// CHECK8-NEXT: br label [[DOTOMP_FINAL_DONE]]
|
|
// CHECK8: .omp.final.done:
|
|
// CHECK8-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195
|
|
// CHECK8-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
|
|
// CHECK8-NEXT: entry:
|
|
// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK8-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK8-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK8-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
|
|
// CHECK8-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK8-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK8-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK8-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
|
|
// CHECK8-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
|
|
// CHECK8-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
|
|
// CHECK8-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
|
|
// CHECK8-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
|
|
// CHECK8-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
|
|
// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK8-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
|
|
// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
|
|
// CHECK8-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
|
|
// CHECK8-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
|
|
// CHECK8-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2
|
|
// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
|
|
// CHECK8-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 4
|
|
// CHECK8-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
|
|
// CHECK8-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1
|
|
// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
|
|
// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]])
|
|
// CHECK8-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..11
|
|
// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] {
|
|
// CHECK8-NEXT: entry:
|
|
// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK8-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK8-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK8-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
|
|
// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK8-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
|
|
// CHECK8-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
|
|
// CHECK8-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
|
|
// CHECK8-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
|
|
// CHECK8-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
|
|
// CHECK8-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
|
|
// CHECK8-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178
|
|
// CHECK8-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
|
|
// CHECK8-NEXT: entry:
|
|
// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK8-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK8-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
|
|
// CHECK8-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK8-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK8-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
|
|
// CHECK8-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
|
|
// CHECK8-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
|
|
// CHECK8-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
|
|
// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK8-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
|
|
// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
|
|
// CHECK8-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
|
|
// CHECK8-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
|
|
// CHECK8-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2
|
|
// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
|
|
// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]])
|
|
// CHECK8-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..14
|
|
// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] {
|
|
// CHECK8-NEXT: entry:
|
|
// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK8-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK8-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
|
|
// CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
|
|
// CHECK8-NEXT: [[TMP:%.*]] = alloca i64, align 4
|
|
// CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
|
|
// CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
|
|
// CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
|
|
// CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK8-NEXT: [[I:%.*]] = alloca i64, align 8
|
|
// CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK8-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
|
|
// CHECK8-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
|
|
// CHECK8-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
|
|
// CHECK8-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
|
|
// CHECK8-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK8-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK8-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
|
|
// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK8-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
|
|
// CHECK8-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
|
|
// CHECK8-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6
|
|
// CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK8: cond.true:
|
|
// CHECK8-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK8: cond.false:
|
|
// CHECK8-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK8-NEXT: br label [[COND_END]]
|
|
// CHECK8: cond.end:
|
|
// CHECK8-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
|
|
// CHECK8-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
|
|
// CHECK8-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK8-NEXT: store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK8: omp.inner.for.cond:
|
|
// CHECK8-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !45
|
|
// CHECK8-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !45
|
|
// CHECK8-NEXT: [[CMP1:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]]
|
|
// CHECK8-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK8: omp.inner.for.body:
|
|
// CHECK8-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !45
|
|
// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3
|
|
// CHECK8-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
|
|
// CHECK8-NEXT: store i64 [[ADD]], i64* [[I]], align 8, !llvm.access.group !45
|
|
// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !45
|
|
// CHECK8-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
|
|
// CHECK8-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4, !llvm.access.group !45
|
|
// CHECK8-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !45
|
|
// CHECK8-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32
|
|
// CHECK8-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
|
|
// CHECK8-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
|
|
// CHECK8-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 4, !llvm.access.group !45
|
|
// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
|
|
// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !45
|
|
// CHECK8-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1
|
|
// CHECK8-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !45
|
|
// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK8: omp.body.continue:
|
|
// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK8: omp.inner.for.inc:
|
|
// CHECK8-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !45
|
|
// CHECK8-NEXT: [[ADD7:%.*]] = add nsw i64 [[TMP12]], 1
|
|
// CHECK8-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !45
|
|
// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP46:![0-9]+]]
|
|
// CHECK8: omp.inner.for.end:
|
|
// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK8: omp.loop.exit:
|
|
// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
|
|
// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK8-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
|
|
// CHECK8-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
|
|
// CHECK8: .omp.final.then:
|
|
// CHECK8-NEXT: store i64 11, i64* [[I]], align 8
|
|
// CHECK8-NEXT: br label [[DOTOMP_FINAL_DONE]]
|
|
// CHECK8: .omp.final.done:
|
|
// CHECK8-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK8-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
|
|
// CHECK8-SAME: () #[[ATTR7:[0-9]+]] {
|
|
// CHECK8-NEXT: entry:
|
|
// CHECK8-NEXT: call void @__tgt_register_requires(i64 1)
|
|
// CHECK8-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK9-LABEL: define {{[^@]+}}@_Z7get_valv
|
|
// CHECK9-SAME: () #[[ATTR0:[0-9]+]] {
|
|
// CHECK9-NEXT: entry:
|
|
// CHECK9-NEXT: ret i64 0
|
|
//
|
|
//
|
|
// CHECK9-LABEL: define {{[^@]+}}@_Z3fooi
|
|
// CHECK9-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
|
|
// CHECK9-NEXT: entry:
|
|
// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: [[AA:%.*]] = alloca i16, align 2
|
|
// CHECK9-NEXT: [[B:%.*]] = alloca [10 x float], align 4
|
|
// CHECK9-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8
|
|
// CHECK9-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8
|
|
// CHECK9-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8
|
|
// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: [[K:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[_TMP3:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: [[DOTOMP_LB4:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: [[DOTOMP_UB5:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: [[DOTOMP_IV6:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: [[DOTLINEAR_START:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[I7:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: [[K8:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[LIN:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: [[_TMP21:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[DOTOMP_LB22:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[DOTOMP_UB23:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[DOTOMP_IV24:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[DOTLINEAR_START25:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: [[DOTLINEAR_START26:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[IT:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[LIN28:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: [[A29:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: [[_TMP58:%.*]] = alloca i16, align 2
|
|
// CHECK9-NEXT: [[DOTOMP_LB59:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: [[DOTOMP_UB60:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: [[DOTOMP_IV61:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: [[IT62:%.*]] = alloca i16, align 2
|
|
// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: [[_TMP77:%.*]] = alloca i8, align 1
|
|
// CHECK9-NEXT: [[DOTOMP_LB78:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: [[DOTOMP_UB79:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: [[DOTOMP_IV80:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: [[IT81:%.*]] = alloca i8, align 1
|
|
// CHECK9-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK9-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK9-NEXT: store i16 0, i16* [[AA]], align 2
|
|
// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK9-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
|
|
// CHECK9-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave()
|
|
// CHECK9-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8
|
|
// CHECK9-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4
|
|
// CHECK9-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8
|
|
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK9-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64
|
|
// CHECK9-NEXT: [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]]
|
|
// CHECK9-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8
|
|
// CHECK9-NEXT: store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8
|
|
// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK9-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK9: omp.inner.for.cond:
|
|
// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
|
|
// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !2
|
|
// CHECK9-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
|
|
// CHECK9-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK9: omp.inner.for.body:
|
|
// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
|
|
// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 5
|
|
// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]]
|
|
// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !2
|
|
// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK9: omp.body.continue:
|
|
// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK9: omp.inner.for.inc:
|
|
// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
|
|
// CHECK9-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1
|
|
// CHECK9-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
|
|
// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]
|
|
// CHECK9: omp.inner.for.end:
|
|
// CHECK9-NEXT: store i32 33, i32* [[I]], align 4
|
|
// CHECK9-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv()
|
|
// CHECK9-NEXT: store i64 [[CALL]], i64* [[K]], align 8
|
|
// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB4]], align 4
|
|
// CHECK9-NEXT: store i32 8, i32* [[DOTOMP_UB5]], align 4
|
|
// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_LB4]], align 4
|
|
// CHECK9-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV6]], align 4
|
|
// CHECK9-NEXT: [[TMP12:%.*]] = load i64, i64* [[K]], align 8
|
|
// CHECK9-NEXT: store i64 [[TMP12]], i64* [[DOTLINEAR_START]], align 8
|
|
// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND9:%.*]]
|
|
// CHECK9: omp.inner.for.cond9:
|
|
// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !6
|
|
// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB5]], align 4, !llvm.access.group !6
|
|
// CHECK9-NEXT: [[CMP10:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
|
|
// CHECK9-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY11:%.*]], label [[OMP_INNER_FOR_END19:%.*]]
|
|
// CHECK9: omp.inner.for.body11:
|
|
// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !6
|
|
// CHECK9-NEXT: [[MUL12:%.*]] = mul nsw i32 [[TMP15]], 1
|
|
// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL12]]
|
|
// CHECK9-NEXT: store i32 [[SUB]], i32* [[I7]], align 4, !llvm.access.group !6
|
|
// CHECK9-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8, !llvm.access.group !6
|
|
// CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !6
|
|
// CHECK9-NEXT: [[MUL13:%.*]] = mul nsw i32 [[TMP17]], 3
|
|
// CHECK9-NEXT: [[CONV:%.*]] = sext i32 [[MUL13]] to i64
|
|
// CHECK9-NEXT: [[ADD14:%.*]] = add nsw i64 [[TMP16]], [[CONV]]
|
|
// CHECK9-NEXT: store i64 [[ADD14]], i64* [[K8]], align 8, !llvm.access.group !6
|
|
// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !6
|
|
// CHECK9-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP18]], 1
|
|
// CHECK9-NEXT: store i32 [[ADD15]], i32* [[A]], align 4, !llvm.access.group !6
|
|
// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE16:%.*]]
|
|
// CHECK9: omp.body.continue16:
|
|
// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC17:%.*]]
|
|
// CHECK9: omp.inner.for.inc17:
|
|
// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !6
|
|
// CHECK9-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP19]], 1
|
|
// CHECK9-NEXT: store i32 [[ADD18]], i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !6
|
|
// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND9]], !llvm.loop [[LOOP7:![0-9]+]]
|
|
// CHECK9: omp.inner.for.end19:
|
|
// CHECK9-NEXT: store i32 1, i32* [[I7]], align 4
|
|
// CHECK9-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8
|
|
// CHECK9-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP20]], 27
|
|
// CHECK9-NEXT: store i64 [[ADD20]], i64* [[K]], align 8
|
|
// CHECK9-NEXT: store i32 12, i32* [[LIN]], align 4
|
|
// CHECK9-NEXT: store i64 0, i64* [[DOTOMP_LB22]], align 8
|
|
// CHECK9-NEXT: store i64 3, i64* [[DOTOMP_UB23]], align 8
|
|
// CHECK9-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_LB22]], align 8
|
|
// CHECK9-NEXT: store i64 [[TMP21]], i64* [[DOTOMP_IV24]], align 8
|
|
// CHECK9-NEXT: [[TMP22:%.*]] = load i32, i32* [[LIN]], align 4
|
|
// CHECK9-NEXT: store i32 [[TMP22]], i32* [[DOTLINEAR_START25]], align 4
|
|
// CHECK9-NEXT: [[TMP23:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK9-NEXT: store i32 [[TMP23]], i32* [[DOTLINEAR_START26]], align 4
|
|
// CHECK9-NEXT: [[CALL27:%.*]] = call i64 @_Z7get_valv()
|
|
// CHECK9-NEXT: store i64 [[CALL27]], i64* [[DOTLINEAR_STEP]], align 8
|
|
// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND30:%.*]]
|
|
// CHECK9: omp.inner.for.cond30:
|
|
// CHECK9-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !9
|
|
// CHECK9-NEXT: [[TMP25:%.*]] = load i64, i64* [[DOTOMP_UB23]], align 8, !llvm.access.group !9
|
|
// CHECK9-NEXT: [[CMP31:%.*]] = icmp ule i64 [[TMP24]], [[TMP25]]
|
|
// CHECK9-NEXT: br i1 [[CMP31]], label [[OMP_INNER_FOR_BODY32:%.*]], label [[OMP_INNER_FOR_END49:%.*]]
|
|
// CHECK9: omp.inner.for.body32:
|
|
// CHECK9-NEXT: [[TMP26:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !9
|
|
// CHECK9-NEXT: [[MUL33:%.*]] = mul i64 [[TMP26]], 400
|
|
// CHECK9-NEXT: [[SUB34:%.*]] = sub i64 2000, [[MUL33]]
|
|
// CHECK9-NEXT: store i64 [[SUB34]], i64* [[IT]], align 8, !llvm.access.group !9
|
|
// CHECK9-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTLINEAR_START25]], align 4, !llvm.access.group !9
|
|
// CHECK9-NEXT: [[CONV35:%.*]] = sext i32 [[TMP27]] to i64
|
|
// CHECK9-NEXT: [[TMP28:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !9
|
|
// CHECK9-NEXT: [[TMP29:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !9
|
|
// CHECK9-NEXT: [[MUL36:%.*]] = mul i64 [[TMP28]], [[TMP29]]
|
|
// CHECK9-NEXT: [[ADD37:%.*]] = add i64 [[CONV35]], [[MUL36]]
|
|
// CHECK9-NEXT: [[CONV38:%.*]] = trunc i64 [[ADD37]] to i32
|
|
// CHECK9-NEXT: store i32 [[CONV38]], i32* [[LIN28]], align 4, !llvm.access.group !9
|
|
// CHECK9-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTLINEAR_START26]], align 4, !llvm.access.group !9
|
|
// CHECK9-NEXT: [[CONV39:%.*]] = sext i32 [[TMP30]] to i64
|
|
// CHECK9-NEXT: [[TMP31:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !9
|
|
// CHECK9-NEXT: [[TMP32:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !9
|
|
// CHECK9-NEXT: [[MUL40:%.*]] = mul i64 [[TMP31]], [[TMP32]]
|
|
// CHECK9-NEXT: [[ADD41:%.*]] = add i64 [[CONV39]], [[MUL40]]
|
|
// CHECK9-NEXT: [[CONV42:%.*]] = trunc i64 [[ADD41]] to i32
|
|
// CHECK9-NEXT: store i32 [[CONV42]], i32* [[A29]], align 4, !llvm.access.group !9
|
|
// CHECK9-NEXT: [[TMP33:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !9
|
|
// CHECK9-NEXT: [[CONV43:%.*]] = sext i16 [[TMP33]] to i32
|
|
// CHECK9-NEXT: [[ADD44:%.*]] = add nsw i32 [[CONV43]], 1
|
|
// CHECK9-NEXT: [[CONV45:%.*]] = trunc i32 [[ADD44]] to i16
|
|
// CHECK9-NEXT: store i16 [[CONV45]], i16* [[AA]], align 2, !llvm.access.group !9
|
|
// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE46:%.*]]
|
|
// CHECK9: omp.body.continue46:
|
|
// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC47:%.*]]
|
|
// CHECK9: omp.inner.for.inc47:
|
|
// CHECK9-NEXT: [[TMP34:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !9
|
|
// CHECK9-NEXT: [[ADD48:%.*]] = add i64 [[TMP34]], 1
|
|
// CHECK9-NEXT: store i64 [[ADD48]], i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !9
|
|
// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND30]], !llvm.loop [[LOOP10:![0-9]+]]
|
|
// CHECK9: omp.inner.for.end49:
|
|
// CHECK9-NEXT: store i64 400, i64* [[IT]], align 8
|
|
// CHECK9-NEXT: [[TMP35:%.*]] = load i32, i32* [[DOTLINEAR_START25]], align 4
|
|
// CHECK9-NEXT: [[CONV50:%.*]] = sext i32 [[TMP35]] to i64
|
|
// CHECK9-NEXT: [[TMP36:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
|
|
// CHECK9-NEXT: [[MUL51:%.*]] = mul i64 4, [[TMP36]]
|
|
// CHECK9-NEXT: [[ADD52:%.*]] = add i64 [[CONV50]], [[MUL51]]
|
|
// CHECK9-NEXT: [[CONV53:%.*]] = trunc i64 [[ADD52]] to i32
|
|
// CHECK9-NEXT: store i32 [[CONV53]], i32* [[LIN]], align 4
|
|
// CHECK9-NEXT: [[TMP37:%.*]] = load i32, i32* [[DOTLINEAR_START26]], align 4
|
|
// CHECK9-NEXT: [[CONV54:%.*]] = sext i32 [[TMP37]] to i64
|
|
// CHECK9-NEXT: [[TMP38:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
|
|
// CHECK9-NEXT: [[MUL55:%.*]] = mul i64 4, [[TMP38]]
|
|
// CHECK9-NEXT: [[ADD56:%.*]] = add i64 [[CONV54]], [[MUL55]]
|
|
// CHECK9-NEXT: [[CONV57:%.*]] = trunc i64 [[ADD56]] to i32
|
|
// CHECK9-NEXT: store i32 [[CONV57]], i32* [[A]], align 4
|
|
// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB59]], align 4
|
|
// CHECK9-NEXT: store i32 3, i32* [[DOTOMP_UB60]], align 4
|
|
// CHECK9-NEXT: [[TMP39:%.*]] = load i32, i32* [[DOTOMP_LB59]], align 4
|
|
// CHECK9-NEXT: store i32 [[TMP39]], i32* [[DOTOMP_IV61]], align 4
|
|
// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND63:%.*]]
|
|
// CHECK9: omp.inner.for.cond63:
|
|
// CHECK9-NEXT: [[TMP40:%.*]] = load i32, i32* [[DOTOMP_IV61]], align 4, !llvm.access.group !12
|
|
// CHECK9-NEXT: [[TMP41:%.*]] = load i32, i32* [[DOTOMP_UB60]], align 4, !llvm.access.group !12
|
|
// CHECK9-NEXT: [[CMP64:%.*]] = icmp sle i32 [[TMP40]], [[TMP41]]
|
|
// CHECK9-NEXT: br i1 [[CMP64]], label [[OMP_INNER_FOR_BODY65:%.*]], label [[OMP_INNER_FOR_END76:%.*]]
|
|
// CHECK9: omp.inner.for.body65:
|
|
// CHECK9-NEXT: [[TMP42:%.*]] = load i32, i32* [[DOTOMP_IV61]], align 4, !llvm.access.group !12
|
|
// CHECK9-NEXT: [[MUL66:%.*]] = mul nsw i32 [[TMP42]], 4
|
|
// CHECK9-NEXT: [[ADD67:%.*]] = add nsw i32 6, [[MUL66]]
|
|
// CHECK9-NEXT: [[CONV68:%.*]] = trunc i32 [[ADD67]] to i16
|
|
// CHECK9-NEXT: store i16 [[CONV68]], i16* [[IT62]], align 2, !llvm.access.group !12
|
|
// CHECK9-NEXT: [[TMP43:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !12
|
|
// CHECK9-NEXT: [[ADD69:%.*]] = add nsw i32 [[TMP43]], 1
|
|
// CHECK9-NEXT: store i32 [[ADD69]], i32* [[A]], align 4, !llvm.access.group !12
|
|
// CHECK9-NEXT: [[TMP44:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !12
|
|
// CHECK9-NEXT: [[CONV70:%.*]] = sext i16 [[TMP44]] to i32
|
|
// CHECK9-NEXT: [[ADD71:%.*]] = add nsw i32 [[CONV70]], 1
|
|
// CHECK9-NEXT: [[CONV72:%.*]] = trunc i32 [[ADD71]] to i16
|
|
// CHECK9-NEXT: store i16 [[CONV72]], i16* [[AA]], align 2, !llvm.access.group !12
|
|
// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE73:%.*]]
|
|
// CHECK9: omp.body.continue73:
|
|
// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC74:%.*]]
|
|
// CHECK9: omp.inner.for.inc74:
|
|
// CHECK9-NEXT: [[TMP45:%.*]] = load i32, i32* [[DOTOMP_IV61]], align 4, !llvm.access.group !12
|
|
// CHECK9-NEXT: [[ADD75:%.*]] = add nsw i32 [[TMP45]], 1
|
|
// CHECK9-NEXT: store i32 [[ADD75]], i32* [[DOTOMP_IV61]], align 4, !llvm.access.group !12
|
|
// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND63]], !llvm.loop [[LOOP13:![0-9]+]]
|
|
// CHECK9: omp.inner.for.end76:
|
|
// CHECK9-NEXT: store i16 22, i16* [[IT62]], align 2
|
|
// CHECK9-NEXT: [[TMP46:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK9-NEXT: store i32 [[TMP46]], i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB78]], align 4
|
|
// CHECK9-NEXT: store i32 25, i32* [[DOTOMP_UB79]], align 4
|
|
// CHECK9-NEXT: [[TMP47:%.*]] = load i32, i32* [[DOTOMP_LB78]], align 4
|
|
// CHECK9-NEXT: store i32 [[TMP47]], i32* [[DOTOMP_IV80]], align 4
|
|
// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND82:%.*]]
|
|
// CHECK9: omp.inner.for.cond82:
|
|
// CHECK9-NEXT: [[TMP48:%.*]] = load i32, i32* [[DOTOMP_IV80]], align 4, !llvm.access.group !15
|
|
// CHECK9-NEXT: [[TMP49:%.*]] = load i32, i32* [[DOTOMP_UB79]], align 4, !llvm.access.group !15
|
|
// CHECK9-NEXT: [[CMP83:%.*]] = icmp sle i32 [[TMP48]], [[TMP49]]
|
|
// CHECK9-NEXT: br i1 [[CMP83]], label [[OMP_INNER_FOR_BODY84:%.*]], label [[OMP_INNER_FOR_END109:%.*]]
|
|
// CHECK9: omp.inner.for.body84:
|
|
// CHECK9-NEXT: [[TMP50:%.*]] = load i32, i32* [[DOTOMP_IV80]], align 4, !llvm.access.group !15
|
|
// CHECK9-NEXT: [[MUL85:%.*]] = mul nsw i32 [[TMP50]], 1
|
|
// CHECK9-NEXT: [[SUB86:%.*]] = sub nsw i32 122, [[MUL85]]
|
|
// CHECK9-NEXT: [[CONV87:%.*]] = trunc i32 [[SUB86]] to i8
|
|
// CHECK9-NEXT: store i8 [[CONV87]], i8* [[IT81]], align 1, !llvm.access.group !15
|
|
// CHECK9-NEXT: [[TMP51:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !15
|
|
// CHECK9-NEXT: [[ADD88:%.*]] = add nsw i32 [[TMP51]], 1
|
|
// CHECK9-NEXT: store i32 [[ADD88]], i32* [[A]], align 4, !llvm.access.group !15
|
|
// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 2
|
|
// CHECK9-NEXT: [[TMP52:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !15
|
|
// CHECK9-NEXT: [[CONV89:%.*]] = fpext float [[TMP52]] to double
|
|
// CHECK9-NEXT: [[ADD90:%.*]] = fadd double [[CONV89]], 1.000000e+00
|
|
// CHECK9-NEXT: [[CONV91:%.*]] = fptrunc double [[ADD90]] to float
|
|
// CHECK9-NEXT: store float [[CONV91]], float* [[ARRAYIDX]], align 4, !llvm.access.group !15
|
|
// CHECK9-NEXT: [[ARRAYIDX92:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 3
|
|
// CHECK9-NEXT: [[TMP53:%.*]] = load float, float* [[ARRAYIDX92]], align 4, !llvm.access.group !15
|
|
// CHECK9-NEXT: [[CONV93:%.*]] = fpext float [[TMP53]] to double
|
|
// CHECK9-NEXT: [[ADD94:%.*]] = fadd double [[CONV93]], 1.000000e+00
|
|
// CHECK9-NEXT: [[CONV95:%.*]] = fptrunc double [[ADD94]] to float
|
|
// CHECK9-NEXT: store float [[CONV95]], float* [[ARRAYIDX92]], align 4, !llvm.access.group !15
|
|
// CHECK9-NEXT: [[ARRAYIDX96:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i64 0, i64 1
|
|
// CHECK9-NEXT: [[ARRAYIDX97:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX96]], i64 0, i64 2
|
|
// CHECK9-NEXT: [[TMP54:%.*]] = load double, double* [[ARRAYIDX97]], align 8, !llvm.access.group !15
|
|
// CHECK9-NEXT: [[ADD98:%.*]] = fadd double [[TMP54]], 1.000000e+00
|
|
// CHECK9-NEXT: store double [[ADD98]], double* [[ARRAYIDX97]], align 8, !llvm.access.group !15
|
|
// CHECK9-NEXT: [[TMP55:%.*]] = mul nsw i64 1, [[TMP4]]
|
|
// CHECK9-NEXT: [[ARRAYIDX99:%.*]] = getelementptr inbounds double, double* [[VLA1]], i64 [[TMP55]]
|
|
// CHECK9-NEXT: [[ARRAYIDX100:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX99]], i64 3
|
|
// CHECK9-NEXT: [[TMP56:%.*]] = load double, double* [[ARRAYIDX100]], align 8, !llvm.access.group !15
|
|
// CHECK9-NEXT: [[ADD101:%.*]] = fadd double [[TMP56]], 1.000000e+00
|
|
// CHECK9-NEXT: store double [[ADD101]], double* [[ARRAYIDX100]], align 8, !llvm.access.group !15
|
|
// CHECK9-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0
|
|
// CHECK9-NEXT: [[TMP57:%.*]] = load i64, i64* [[X]], align 8, !llvm.access.group !15
|
|
// CHECK9-NEXT: [[ADD102:%.*]] = add nsw i64 [[TMP57]], 1
|
|
// CHECK9-NEXT: store i64 [[ADD102]], i64* [[X]], align 8, !llvm.access.group !15
|
|
// CHECK9-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1
|
|
// CHECK9-NEXT: [[TMP58:%.*]] = load i8, i8* [[Y]], align 8, !llvm.access.group !15
|
|
// CHECK9-NEXT: [[CONV103:%.*]] = sext i8 [[TMP58]] to i32
|
|
// CHECK9-NEXT: [[ADD104:%.*]] = add nsw i32 [[CONV103]], 1
|
|
// CHECK9-NEXT: [[CONV105:%.*]] = trunc i32 [[ADD104]] to i8
|
|
// CHECK9-NEXT: store i8 [[CONV105]], i8* [[Y]], align 8, !llvm.access.group !15
|
|
// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE106:%.*]]
|
|
// CHECK9: omp.body.continue106:
|
|
// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC107:%.*]]
|
|
// CHECK9: omp.inner.for.inc107:
|
|
// CHECK9-NEXT: [[TMP59:%.*]] = load i32, i32* [[DOTOMP_IV80]], align 4, !llvm.access.group !15
|
|
// CHECK9-NEXT: [[ADD108:%.*]] = add nsw i32 [[TMP59]], 1
|
|
// CHECK9-NEXT: store i32 [[ADD108]], i32* [[DOTOMP_IV80]], align 4, !llvm.access.group !15
|
|
// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND82]], !llvm.loop [[LOOP16:![0-9]+]]
|
|
// CHECK9: omp.inner.for.end109:
|
|
// CHECK9-NEXT: store i8 96, i8* [[IT81]], align 1
|
|
// CHECK9-NEXT: [[TMP60:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK9-NEXT: [[TMP61:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
|
|
// CHECK9-NEXT: call void @llvm.stackrestore(i8* [[TMP61]])
|
|
// CHECK9-NEXT: ret i32 [[TMP60]]
|
|
//
|
|
//
|
|
// CHECK9-LABEL: define {{[^@]+}}@_Z3bari
|
|
// CHECK9-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
|
|
// CHECK9-NEXT: entry:
|
|
// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8
|
|
// CHECK9-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK9-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK9-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]])
|
|
// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
|
|
// CHECK9-NEXT: store i32 [[ADD]], i32* [[A]], align 4
|
|
// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK9-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]])
|
|
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK9-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
|
|
// CHECK9-NEXT: store i32 [[ADD2]], i32* [[A]], align 4
|
|
// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK9-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]])
|
|
// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
|
|
// CHECK9-NEXT: store i32 [[ADD4]], i32* [[A]], align 4
|
|
// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK9-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]])
|
|
// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK9-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
|
|
// CHECK9-NEXT: store i32 [[ADD6]], i32* [[A]], align 4
|
|
// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK9-NEXT: ret i32 [[TMP8]]
|
|
//
|
|
//
|
|
// CHECK9-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
|
|
// CHECK9-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 {
|
|
// CHECK9-NEXT: entry:
|
|
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
|
|
// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: [[B:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8
|
|
// CHECK9-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[TMP:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[IT:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK9-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
|
|
// CHECK9-NEXT: store i32 [[ADD]], i32* [[B]], align 4
|
|
// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK9-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
|
|
// CHECK9-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave()
|
|
// CHECK9-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8
|
|
// CHECK9-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]]
|
|
// CHECK9-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2
|
|
// CHECK9-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8
|
|
// CHECK9-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK9-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK9-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK9-NEXT: store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK9: omp.inner.for.cond:
|
|
// CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18
|
|
// CHECK9-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !18
|
|
// CHECK9-NEXT: [[CMP:%.*]] = icmp ule i64 [[TMP6]], [[TMP7]]
|
|
// CHECK9-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK9: omp.inner.for.body:
|
|
// CHECK9-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18
|
|
// CHECK9-NEXT: [[MUL:%.*]] = mul i64 [[TMP8]], 400
|
|
// CHECK9-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]
|
|
// CHECK9-NEXT: store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !18
|
|
// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[B]], align 4, !llvm.access.group !18
|
|
// CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP9]] to double
|
|
// CHECK9-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00
|
|
// CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
|
|
// CHECK9-NEXT: store double [[ADD2]], double* [[A]], align 8, !llvm.access.group !18
|
|
// CHECK9-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
|
|
// CHECK9-NEXT: [[TMP10:%.*]] = load double, double* [[A3]], align 8, !llvm.access.group !18
|
|
// CHECK9-NEXT: [[INC:%.*]] = fadd double [[TMP10]], 1.000000e+00
|
|
// CHECK9-NEXT: store double [[INC]], double* [[A3]], align 8, !llvm.access.group !18
|
|
// CHECK9-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16
|
|
// CHECK9-NEXT: [[TMP11:%.*]] = mul nsw i64 1, [[TMP2]]
|
|
// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP11]]
|
|
// CHECK9-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
|
|
// CHECK9-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2, !llvm.access.group !18
|
|
// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK9: omp.body.continue:
|
|
// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK9: omp.inner.for.inc:
|
|
// CHECK9-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18
|
|
// CHECK9-NEXT: [[ADD6:%.*]] = add i64 [[TMP12]], 1
|
|
// CHECK9-NEXT: store i64 [[ADD6]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18
|
|
// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]
|
|
// CHECK9: omp.inner.for.end:
|
|
// CHECK9-NEXT: store i64 400, i64* [[IT]], align 8
|
|
// CHECK9-NEXT: [[TMP13:%.*]] = mul nsw i64 1, [[TMP2]]
|
|
// CHECK9-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP13]]
|
|
// CHECK9-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX7]], i64 1
|
|
// CHECK9-NEXT: [[TMP14:%.*]] = load i16, i16* [[ARRAYIDX8]], align 2
|
|
// CHECK9-NEXT: [[CONV9:%.*]] = sext i16 [[TMP14]] to i32
|
|
// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[B]], align 4
|
|
// CHECK9-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[TMP15]]
|
|
// CHECK9-NEXT: [[TMP16:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
|
|
// CHECK9-NEXT: call void @llvm.stackrestore(i8* [[TMP16]])
|
|
// CHECK9-NEXT: ret i32 [[ADD10]]
|
|
//
|
|
//
|
|
// CHECK9-LABEL: define {{[^@]+}}@_ZL7fstatici
|
|
// CHECK9-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
|
|
// CHECK9-NEXT: entry:
|
|
// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: [[AA:%.*]] = alloca i16, align 2
|
|
// CHECK9-NEXT: [[AAA:%.*]] = alloca i8, align 1
|
|
// CHECK9-NEXT: [[B:%.*]] = alloca [10 x i32], align 4
|
|
// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK9-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK9-NEXT: store i16 0, i16* [[AA]], align 2
|
|
// CHECK9-NEXT: store i8 0, i8* [[AAA]], align 1
|
|
// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK9-NEXT: store i32 429496720, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK9-NEXT: ret i32 [[TMP0]]
|
|
//
|
|
//
|
|
// CHECK9-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
|
|
// CHECK9-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat {
|
|
// CHECK9-NEXT: entry:
|
|
// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: [[AA:%.*]] = alloca i16, align 2
|
|
// CHECK9-NEXT: [[B:%.*]] = alloca [10 x i32], align 4
|
|
// CHECK9-NEXT: [[TMP:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[I:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK9-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK9-NEXT: store i16 0, i16* [[AA]], align 2
|
|
// CHECK9-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK9-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK9-NEXT: store i64 [[TMP0]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK9: omp.inner.for.cond:
|
|
// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !21
|
|
// CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !21
|
|
// CHECK9-NEXT: [[CMP:%.*]] = icmp sle i64 [[TMP1]], [[TMP2]]
|
|
// CHECK9-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK9: omp.inner.for.body:
|
|
// CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !21
|
|
// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP3]], 3
|
|
// CHECK9-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
|
|
// CHECK9-NEXT: store i64 [[ADD]], i64* [[I]], align 8, !llvm.access.group !21
|
|
// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !21
|
|
// CHECK9-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1
|
|
// CHECK9-NEXT: store i32 [[ADD1]], i32* [[A]], align 4, !llvm.access.group !21
|
|
// CHECK9-NEXT: [[TMP5:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !21
|
|
// CHECK9-NEXT: [[CONV:%.*]] = sext i16 [[TMP5]] to i32
|
|
// CHECK9-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 1
|
|
// CHECK9-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
|
|
// CHECK9-NEXT: store i16 [[CONV3]], i16* [[AA]], align 2, !llvm.access.group !21
|
|
// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2
|
|
// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !21
|
|
// CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP6]], 1
|
|
// CHECK9-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !21
|
|
// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK9: omp.body.continue:
|
|
// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK9: omp.inner.for.inc:
|
|
// CHECK9-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !21
|
|
// CHECK9-NEXT: [[ADD5:%.*]] = add nsw i64 [[TMP7]], 1
|
|
// CHECK9-NEXT: store i64 [[ADD5]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !21
|
|
// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]]
|
|
// CHECK9: omp.inner.for.end:
|
|
// CHECK9-NEXT: store i64 11, i64* [[I]], align 8
|
|
// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK9-NEXT: ret i32 [[TMP8]]
|
|
//
|
|
//
|
|
// CHECK10-LABEL: define {{[^@]+}}@_Z7get_valv
|
|
// CHECK10-SAME: () #[[ATTR0:[0-9]+]] {
|
|
// CHECK10-NEXT: entry:
|
|
// CHECK10-NEXT: ret i64 0
|
|
//
|
|
//
|
|
// CHECK10-LABEL: define {{[^@]+}}@_Z3fooi
|
|
// CHECK10-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
|
|
// CHECK10-NEXT: entry:
|
|
// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK10-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK10-NEXT: [[AA:%.*]] = alloca i16, align 2
|
|
// CHECK10-NEXT: [[B:%.*]] = alloca [10 x float], align 4
|
|
// CHECK10-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8
|
|
// CHECK10-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8
|
|
// CHECK10-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8
|
|
// CHECK10-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8
|
|
// CHECK10-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8
|
|
// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4
|
|
// CHECK10-NEXT: [[K:%.*]] = alloca i64, align 8
|
|
// CHECK10-NEXT: [[_TMP3:%.*]] = alloca i32, align 4
|
|
// CHECK10-NEXT: [[DOTOMP_LB4:%.*]] = alloca i32, align 4
|
|
// CHECK10-NEXT: [[DOTOMP_UB5:%.*]] = alloca i32, align 4
|
|
// CHECK10-NEXT: [[DOTOMP_IV6:%.*]] = alloca i32, align 4
|
|
// CHECK10-NEXT: [[DOTLINEAR_START:%.*]] = alloca i64, align 8
|
|
// CHECK10-NEXT: [[I7:%.*]] = alloca i32, align 4
|
|
// CHECK10-NEXT: [[K8:%.*]] = alloca i64, align 8
|
|
// CHECK10-NEXT: [[LIN:%.*]] = alloca i32, align 4
|
|
// CHECK10-NEXT: [[_TMP21:%.*]] = alloca i64, align 8
|
|
// CHECK10-NEXT: [[DOTOMP_LB22:%.*]] = alloca i64, align 8
|
|
// CHECK10-NEXT: [[DOTOMP_UB23:%.*]] = alloca i64, align 8
|
|
// CHECK10-NEXT: [[DOTOMP_IV24:%.*]] = alloca i64, align 8
|
|
// CHECK10-NEXT: [[DOTLINEAR_START25:%.*]] = alloca i32, align 4
|
|
// CHECK10-NEXT: [[DOTLINEAR_START26:%.*]] = alloca i32, align 4
|
|
// CHECK10-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8
|
|
// CHECK10-NEXT: [[IT:%.*]] = alloca i64, align 8
|
|
// CHECK10-NEXT: [[LIN28:%.*]] = alloca i32, align 4
|
|
// CHECK10-NEXT: [[A29:%.*]] = alloca i32, align 4
|
|
// CHECK10-NEXT: [[_TMP58:%.*]] = alloca i16, align 2
|
|
// CHECK10-NEXT: [[DOTOMP_LB59:%.*]] = alloca i32, align 4
|
|
// CHECK10-NEXT: [[DOTOMP_UB60:%.*]] = alloca i32, align 4
|
|
// CHECK10-NEXT: [[DOTOMP_IV61:%.*]] = alloca i32, align 4
|
|
// CHECK10-NEXT: [[IT62:%.*]] = alloca i16, align 2
|
|
// CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
|
// CHECK10-NEXT: [[_TMP77:%.*]] = alloca i8, align 1
|
|
// CHECK10-NEXT: [[DOTOMP_LB78:%.*]] = alloca i32, align 4
|
|
// CHECK10-NEXT: [[DOTOMP_UB79:%.*]] = alloca i32, align 4
|
|
// CHECK10-NEXT: [[DOTOMP_IV80:%.*]] = alloca i32, align 4
|
|
// CHECK10-NEXT: [[IT81:%.*]] = alloca i8, align 1
|
|
// CHECK10-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK10-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK10-NEXT: store i16 0, i16* [[AA]], align 2
|
|
// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK10-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
|
|
// CHECK10-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave()
|
|
// CHECK10-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8
|
|
// CHECK10-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4
|
|
// CHECK10-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8
|
|
// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK10-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64
|
|
// CHECK10-NEXT: [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]]
|
|
// CHECK10-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8
|
|
// CHECK10-NEXT: store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8
|
|
// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK10-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK10: omp.inner.for.cond:
|
|
// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
|
|
// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !2
|
|
// CHECK10-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
|
|
// CHECK10-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK10: omp.inner.for.body:
|
|
// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
|
|
// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 5
|
|
// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]]
|
|
// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !2
|
|
// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK10: omp.body.continue:
|
|
// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK10: omp.inner.for.inc:
|
|
// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
|
|
// CHECK10-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1
|
|
// CHECK10-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
|
|
// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]
|
|
// CHECK10: omp.inner.for.end:
|
|
// CHECK10-NEXT: store i32 33, i32* [[I]], align 4
|
|
// CHECK10-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv()
|
|
// CHECK10-NEXT: store i64 [[CALL]], i64* [[K]], align 8
|
|
// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB4]], align 4
|
|
// CHECK10-NEXT: store i32 8, i32* [[DOTOMP_UB5]], align 4
|
|
// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_LB4]], align 4
|
|
// CHECK10-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV6]], align 4
|
|
// CHECK10-NEXT: [[TMP12:%.*]] = load i64, i64* [[K]], align 8
|
|
// CHECK10-NEXT: store i64 [[TMP12]], i64* [[DOTLINEAR_START]], align 8
|
|
// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND9:%.*]]
|
|
// CHECK10: omp.inner.for.cond9:
|
|
// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !6
|
|
// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB5]], align 4, !llvm.access.group !6
|
|
// CHECK10-NEXT: [[CMP10:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
|
|
// CHECK10-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY11:%.*]], label [[OMP_INNER_FOR_END19:%.*]]
|
|
// CHECK10: omp.inner.for.body11:
|
|
// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !6
|
|
// CHECK10-NEXT: [[MUL12:%.*]] = mul nsw i32 [[TMP15]], 1
|
|
// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL12]]
|
|
// CHECK10-NEXT: store i32 [[SUB]], i32* [[I7]], align 4, !llvm.access.group !6
|
|
// CHECK10-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8, !llvm.access.group !6
|
|
// CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !6
|
|
// CHECK10-NEXT: [[MUL13:%.*]] = mul nsw i32 [[TMP17]], 3
|
|
// CHECK10-NEXT: [[CONV:%.*]] = sext i32 [[MUL13]] to i64
|
|
// CHECK10-NEXT: [[ADD14:%.*]] = add nsw i64 [[TMP16]], [[CONV]]
|
|
// CHECK10-NEXT: store i64 [[ADD14]], i64* [[K8]], align 8, !llvm.access.group !6
|
|
// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !6
|
|
// CHECK10-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP18]], 1
|
|
// CHECK10-NEXT: store i32 [[ADD15]], i32* [[A]], align 4, !llvm.access.group !6
|
|
// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE16:%.*]]
|
|
// CHECK10: omp.body.continue16:
|
|
// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC17:%.*]]
|
|
// CHECK10: omp.inner.for.inc17:
|
|
// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !6
|
|
// CHECK10-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP19]], 1
|
|
// CHECK10-NEXT: store i32 [[ADD18]], i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !6
|
|
// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND9]], !llvm.loop [[LOOP7:![0-9]+]]
|
|
// CHECK10: omp.inner.for.end19:
|
|
// CHECK10-NEXT: store i32 1, i32* [[I7]], align 4
|
|
// CHECK10-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8
|
|
// CHECK10-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP20]], 27
|
|
// CHECK10-NEXT: store i64 [[ADD20]], i64* [[K]], align 8
|
|
// CHECK10-NEXT: store i32 12, i32* [[LIN]], align 4
|
|
// CHECK10-NEXT: store i64 0, i64* [[DOTOMP_LB22]], align 8
|
|
// CHECK10-NEXT: store i64 3, i64* [[DOTOMP_UB23]], align 8
|
|
// CHECK10-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_LB22]], align 8
|
|
// CHECK10-NEXT: store i64 [[TMP21]], i64* [[DOTOMP_IV24]], align 8
|
|
// CHECK10-NEXT: [[TMP22:%.*]] = load i32, i32* [[LIN]], align 4
|
|
// CHECK10-NEXT: store i32 [[TMP22]], i32* [[DOTLINEAR_START25]], align 4
|
|
// CHECK10-NEXT: [[TMP23:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK10-NEXT: store i32 [[TMP23]], i32* [[DOTLINEAR_START26]], align 4
|
|
// CHECK10-NEXT: [[CALL27:%.*]] = call i64 @_Z7get_valv()
|
|
// CHECK10-NEXT: store i64 [[CALL27]], i64* [[DOTLINEAR_STEP]], align 8
|
|
// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND30:%.*]]
|
|
// CHECK10: omp.inner.for.cond30:
|
|
// CHECK10-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !9
|
|
// CHECK10-NEXT: [[TMP25:%.*]] = load i64, i64* [[DOTOMP_UB23]], align 8, !llvm.access.group !9
|
|
// CHECK10-NEXT: [[CMP31:%.*]] = icmp ule i64 [[TMP24]], [[TMP25]]
|
|
// CHECK10-NEXT: br i1 [[CMP31]], label [[OMP_INNER_FOR_BODY32:%.*]], label [[OMP_INNER_FOR_END49:%.*]]
|
|
// CHECK10: omp.inner.for.body32:
|
|
// CHECK10-NEXT: [[TMP26:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !9
|
|
// CHECK10-NEXT: [[MUL33:%.*]] = mul i64 [[TMP26]], 400
|
|
// CHECK10-NEXT: [[SUB34:%.*]] = sub i64 2000, [[MUL33]]
|
|
// CHECK10-NEXT: store i64 [[SUB34]], i64* [[IT]], align 8, !llvm.access.group !9
|
|
// CHECK10-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTLINEAR_START25]], align 4, !llvm.access.group !9
|
|
// CHECK10-NEXT: [[CONV35:%.*]] = sext i32 [[TMP27]] to i64
|
|
// CHECK10-NEXT: [[TMP28:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !9
|
|
// CHECK10-NEXT: [[TMP29:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !9
|
|
// CHECK10-NEXT: [[MUL36:%.*]] = mul i64 [[TMP28]], [[TMP29]]
|
|
// CHECK10-NEXT: [[ADD37:%.*]] = add i64 [[CONV35]], [[MUL36]]
|
|
// CHECK10-NEXT: [[CONV38:%.*]] = trunc i64 [[ADD37]] to i32
|
|
// CHECK10-NEXT: store i32 [[CONV38]], i32* [[LIN28]], align 4, !llvm.access.group !9
|
|
// CHECK10-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTLINEAR_START26]], align 4, !llvm.access.group !9
|
|
// CHECK10-NEXT: [[CONV39:%.*]] = sext i32 [[TMP30]] to i64
|
|
// CHECK10-NEXT: [[TMP31:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !9
|
|
// CHECK10-NEXT: [[TMP32:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !9
|
|
// CHECK10-NEXT: [[MUL40:%.*]] = mul i64 [[TMP31]], [[TMP32]]
|
|
// CHECK10-NEXT: [[ADD41:%.*]] = add i64 [[CONV39]], [[MUL40]]
|
|
// CHECK10-NEXT: [[CONV42:%.*]] = trunc i64 [[ADD41]] to i32
|
|
// CHECK10-NEXT: store i32 [[CONV42]], i32* [[A29]], align 4, !llvm.access.group !9
|
|
// CHECK10-NEXT: [[TMP33:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !9
|
|
// CHECK10-NEXT: [[CONV43:%.*]] = sext i16 [[TMP33]] to i32
|
|
// CHECK10-NEXT: [[ADD44:%.*]] = add nsw i32 [[CONV43]], 1
|
|
// CHECK10-NEXT: [[CONV45:%.*]] = trunc i32 [[ADD44]] to i16
|
|
// CHECK10-NEXT: store i16 [[CONV45]], i16* [[AA]], align 2, !llvm.access.group !9
|
|
// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE46:%.*]]
|
|
// CHECK10: omp.body.continue46:
|
|
// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC47:%.*]]
|
|
// CHECK10: omp.inner.for.inc47:
|
|
// CHECK10-NEXT: [[TMP34:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !9
|
|
// CHECK10-NEXT: [[ADD48:%.*]] = add i64 [[TMP34]], 1
|
|
// CHECK10-NEXT: store i64 [[ADD48]], i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !9
|
|
// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND30]], !llvm.loop [[LOOP10:![0-9]+]]
|
|
// CHECK10: omp.inner.for.end49:
|
|
// CHECK10-NEXT: store i64 400, i64* [[IT]], align 8
|
|
// CHECK10-NEXT: [[TMP35:%.*]] = load i32, i32* [[DOTLINEAR_START25]], align 4
|
|
// CHECK10-NEXT: [[CONV50:%.*]] = sext i32 [[TMP35]] to i64
|
|
// CHECK10-NEXT: [[TMP36:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
|
|
// CHECK10-NEXT: [[MUL51:%.*]] = mul i64 4, [[TMP36]]
|
|
// CHECK10-NEXT: [[ADD52:%.*]] = add i64 [[CONV50]], [[MUL51]]
|
|
// CHECK10-NEXT: [[CONV53:%.*]] = trunc i64 [[ADD52]] to i32
|
|
// CHECK10-NEXT: store i32 [[CONV53]], i32* [[LIN]], align 4
|
|
// CHECK10-NEXT: [[TMP37:%.*]] = load i32, i32* [[DOTLINEAR_START26]], align 4
|
|
// CHECK10-NEXT: [[CONV54:%.*]] = sext i32 [[TMP37]] to i64
|
|
// CHECK10-NEXT: [[TMP38:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
|
|
// CHECK10-NEXT: [[MUL55:%.*]] = mul i64 4, [[TMP38]]
|
|
// CHECK10-NEXT: [[ADD56:%.*]] = add i64 [[CONV54]], [[MUL55]]
|
|
// CHECK10-NEXT: [[CONV57:%.*]] = trunc i64 [[ADD56]] to i32
|
|
// CHECK10-NEXT: store i32 [[CONV57]], i32* [[A]], align 4
|
|
// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB59]], align 4
|
|
// CHECK10-NEXT: store i32 3, i32* [[DOTOMP_UB60]], align 4
|
|
// CHECK10-NEXT: [[TMP39:%.*]] = load i32, i32* [[DOTOMP_LB59]], align 4
|
|
// CHECK10-NEXT: store i32 [[TMP39]], i32* [[DOTOMP_IV61]], align 4
|
|
// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND63:%.*]]
|
|
// CHECK10: omp.inner.for.cond63:
|
|
// CHECK10-NEXT: [[TMP40:%.*]] = load i32, i32* [[DOTOMP_IV61]], align 4, !llvm.access.group !12
|
|
// CHECK10-NEXT: [[TMP41:%.*]] = load i32, i32* [[DOTOMP_UB60]], align 4, !llvm.access.group !12
|
|
// CHECK10-NEXT: [[CMP64:%.*]] = icmp sle i32 [[TMP40]], [[TMP41]]
|
|
// CHECK10-NEXT: br i1 [[CMP64]], label [[OMP_INNER_FOR_BODY65:%.*]], label [[OMP_INNER_FOR_END76:%.*]]
|
|
// CHECK10: omp.inner.for.body65:
|
|
// CHECK10-NEXT: [[TMP42:%.*]] = load i32, i32* [[DOTOMP_IV61]], align 4, !llvm.access.group !12
|
|
// CHECK10-NEXT: [[MUL66:%.*]] = mul nsw i32 [[TMP42]], 4
|
|
// CHECK10-NEXT: [[ADD67:%.*]] = add nsw i32 6, [[MUL66]]
|
|
// CHECK10-NEXT: [[CONV68:%.*]] = trunc i32 [[ADD67]] to i16
|
|
// CHECK10-NEXT: store i16 [[CONV68]], i16* [[IT62]], align 2, !llvm.access.group !12
|
|
// CHECK10-NEXT: [[TMP43:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !12
|
|
// CHECK10-NEXT: [[ADD69:%.*]] = add nsw i32 [[TMP43]], 1
|
|
// CHECK10-NEXT: store i32 [[ADD69]], i32* [[A]], align 4, !llvm.access.group !12
|
|
// CHECK10-NEXT: [[TMP44:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !12
|
|
// CHECK10-NEXT: [[CONV70:%.*]] = sext i16 [[TMP44]] to i32
|
|
// CHECK10-NEXT: [[ADD71:%.*]] = add nsw i32 [[CONV70]], 1
|
|
// CHECK10-NEXT: [[CONV72:%.*]] = trunc i32 [[ADD71]] to i16
|
|
// CHECK10-NEXT: store i16 [[CONV72]], i16* [[AA]], align 2, !llvm.access.group !12
|
|
// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE73:%.*]]
|
|
// CHECK10: omp.body.continue73:
|
|
// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC74:%.*]]
|
|
// CHECK10: omp.inner.for.inc74:
|
|
// CHECK10-NEXT: [[TMP45:%.*]] = load i32, i32* [[DOTOMP_IV61]], align 4, !llvm.access.group !12
|
|
// CHECK10-NEXT: [[ADD75:%.*]] = add nsw i32 [[TMP45]], 1
|
|
// CHECK10-NEXT: store i32 [[ADD75]], i32* [[DOTOMP_IV61]], align 4, !llvm.access.group !12
|
|
// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND63]], !llvm.loop [[LOOP13:![0-9]+]]
|
|
// CHECK10: omp.inner.for.end76:
|
|
// CHECK10-NEXT: store i16 22, i16* [[IT62]], align 2
|
|
// CHECK10-NEXT: [[TMP46:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK10-NEXT: store i32 [[TMP46]], i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB78]], align 4
|
|
// CHECK10-NEXT: store i32 25, i32* [[DOTOMP_UB79]], align 4
|
|
// CHECK10-NEXT: [[TMP47:%.*]] = load i32, i32* [[DOTOMP_LB78]], align 4
|
|
// CHECK10-NEXT: store i32 [[TMP47]], i32* [[DOTOMP_IV80]], align 4
|
|
// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND82:%.*]]
|
|
// CHECK10: omp.inner.for.cond82:
|
|
// CHECK10-NEXT: [[TMP48:%.*]] = load i32, i32* [[DOTOMP_IV80]], align 4, !llvm.access.group !15
|
|
// CHECK10-NEXT: [[TMP49:%.*]] = load i32, i32* [[DOTOMP_UB79]], align 4, !llvm.access.group !15
|
|
// CHECK10-NEXT: [[CMP83:%.*]] = icmp sle i32 [[TMP48]], [[TMP49]]
|
|
// CHECK10-NEXT: br i1 [[CMP83]], label [[OMP_INNER_FOR_BODY84:%.*]], label [[OMP_INNER_FOR_END109:%.*]]
|
|
// CHECK10: omp.inner.for.body84:
|
|
// CHECK10-NEXT: [[TMP50:%.*]] = load i32, i32* [[DOTOMP_IV80]], align 4, !llvm.access.group !15
|
|
// CHECK10-NEXT: [[MUL85:%.*]] = mul nsw i32 [[TMP50]], 1
|
|
// CHECK10-NEXT: [[SUB86:%.*]] = sub nsw i32 122, [[MUL85]]
|
|
// CHECK10-NEXT: [[CONV87:%.*]] = trunc i32 [[SUB86]] to i8
|
|
// CHECK10-NEXT: store i8 [[CONV87]], i8* [[IT81]], align 1, !llvm.access.group !15
|
|
// CHECK10-NEXT: [[TMP51:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !15
|
|
// CHECK10-NEXT: [[ADD88:%.*]] = add nsw i32 [[TMP51]], 1
|
|
// CHECK10-NEXT: store i32 [[ADD88]], i32* [[A]], align 4, !llvm.access.group !15
|
|
// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 2
|
|
// CHECK10-NEXT: [[TMP52:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !15
|
|
// CHECK10-NEXT: [[CONV89:%.*]] = fpext float [[TMP52]] to double
|
|
// CHECK10-NEXT: [[ADD90:%.*]] = fadd double [[CONV89]], 1.000000e+00
|
|
// CHECK10-NEXT: [[CONV91:%.*]] = fptrunc double [[ADD90]] to float
|
|
// CHECK10-NEXT: store float [[CONV91]], float* [[ARRAYIDX]], align 4, !llvm.access.group !15
|
|
// CHECK10-NEXT: [[ARRAYIDX92:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 3
|
|
// CHECK10-NEXT: [[TMP53:%.*]] = load float, float* [[ARRAYIDX92]], align 4, !llvm.access.group !15
|
|
// CHECK10-NEXT: [[CONV93:%.*]] = fpext float [[TMP53]] to double
|
|
// CHECK10-NEXT: [[ADD94:%.*]] = fadd double [[CONV93]], 1.000000e+00
|
|
// CHECK10-NEXT: [[CONV95:%.*]] = fptrunc double [[ADD94]] to float
|
|
// CHECK10-NEXT: store float [[CONV95]], float* [[ARRAYIDX92]], align 4, !llvm.access.group !15
|
|
// CHECK10-NEXT: [[ARRAYIDX96:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i64 0, i64 1
|
|
// CHECK10-NEXT: [[ARRAYIDX97:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX96]], i64 0, i64 2
|
|
// CHECK10-NEXT: [[TMP54:%.*]] = load double, double* [[ARRAYIDX97]], align 8, !llvm.access.group !15
|
|
// CHECK10-NEXT: [[ADD98:%.*]] = fadd double [[TMP54]], 1.000000e+00
|
|
// CHECK10-NEXT: store double [[ADD98]], double* [[ARRAYIDX97]], align 8, !llvm.access.group !15
|
|
// CHECK10-NEXT: [[TMP55:%.*]] = mul nsw i64 1, [[TMP4]]
|
|
// CHECK10-NEXT: [[ARRAYIDX99:%.*]] = getelementptr inbounds double, double* [[VLA1]], i64 [[TMP55]]
|
|
// CHECK10-NEXT: [[ARRAYIDX100:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX99]], i64 3
|
|
// CHECK10-NEXT: [[TMP56:%.*]] = load double, double* [[ARRAYIDX100]], align 8, !llvm.access.group !15
|
|
// CHECK10-NEXT: [[ADD101:%.*]] = fadd double [[TMP56]], 1.000000e+00
|
|
// CHECK10-NEXT: store double [[ADD101]], double* [[ARRAYIDX100]], align 8, !llvm.access.group !15
|
|
// CHECK10-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0
|
|
// CHECK10-NEXT: [[TMP57:%.*]] = load i64, i64* [[X]], align 8, !llvm.access.group !15
|
|
// CHECK10-NEXT: [[ADD102:%.*]] = add nsw i64 [[TMP57]], 1
|
|
// CHECK10-NEXT: store i64 [[ADD102]], i64* [[X]], align 8, !llvm.access.group !15
|
|
// CHECK10-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1
|
|
// CHECK10-NEXT: [[TMP58:%.*]] = load i8, i8* [[Y]], align 8, !llvm.access.group !15
|
|
// CHECK10-NEXT: [[CONV103:%.*]] = sext i8 [[TMP58]] to i32
|
|
// CHECK10-NEXT: [[ADD104:%.*]] = add nsw i32 [[CONV103]], 1
|
|
// CHECK10-NEXT: [[CONV105:%.*]] = trunc i32 [[ADD104]] to i8
|
|
// CHECK10-NEXT: store i8 [[CONV105]], i8* [[Y]], align 8, !llvm.access.group !15
|
|
// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE106:%.*]]
|
|
// CHECK10: omp.body.continue106:
|
|
// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC107:%.*]]
|
|
// CHECK10: omp.inner.for.inc107:
|
|
// CHECK10-NEXT: [[TMP59:%.*]] = load i32, i32* [[DOTOMP_IV80]], align 4, !llvm.access.group !15
|
|
// CHECK10-NEXT: [[ADD108:%.*]] = add nsw i32 [[TMP59]], 1
|
|
// CHECK10-NEXT: store i32 [[ADD108]], i32* [[DOTOMP_IV80]], align 4, !llvm.access.group !15
|
|
// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND82]], !llvm.loop [[LOOP16:![0-9]+]]
|
|
// CHECK10: omp.inner.for.end109:
|
|
// CHECK10-NEXT: store i8 96, i8* [[IT81]], align 1
|
|
// CHECK10-NEXT: [[TMP60:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK10-NEXT: [[TMP61:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
|
|
// CHECK10-NEXT: call void @llvm.stackrestore(i8* [[TMP61]])
|
|
// CHECK10-NEXT: ret i32 [[TMP60]]
|
|
//
|
|
//
|
|
// CHECK10-LABEL: define {{[^@]+}}@_Z3bari
|
|
// CHECK10-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
|
|
// CHECK10-NEXT: entry:
|
|
// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK10-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK10-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8
|
|
// CHECK10-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK10-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK10-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]])
|
|
// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
|
|
// CHECK10-NEXT: store i32 [[ADD]], i32* [[A]], align 4
|
|
// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK10-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]])
|
|
// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK10-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
|
|
// CHECK10-NEXT: store i32 [[ADD2]], i32* [[A]], align 4
|
|
// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK10-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]])
|
|
// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK10-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
|
|
// CHECK10-NEXT: store i32 [[ADD4]], i32* [[A]], align 4
|
|
// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK10-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]])
|
|
// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK10-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
|
|
// CHECK10-NEXT: store i32 [[ADD6]], i32* [[A]], align 4
|
|
// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK10-NEXT: ret i32 [[TMP8]]
|
|
//
|
|
//
|
|
// CHECK10-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
|
|
// CHECK10-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 {
|
|
// CHECK10-NEXT: entry:
|
|
// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
|
|
// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK10-NEXT: [[B:%.*]] = alloca i32, align 4
|
|
// CHECK10-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8
|
|
// CHECK10-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8
|
|
// CHECK10-NEXT: [[TMP:%.*]] = alloca i64, align 8
|
|
// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
|
|
// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
|
|
// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
|
|
// CHECK10-NEXT: [[IT:%.*]] = alloca i64, align 8
|
|
// CHECK10-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK10-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
|
|
// CHECK10-NEXT: store i32 [[ADD]], i32* [[B]], align 4
|
|
// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK10-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
|
|
// CHECK10-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave()
|
|
// CHECK10-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8
|
|
// CHECK10-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]]
|
|
// CHECK10-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2
|
|
// CHECK10-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8
|
|
// CHECK10-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK10-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK10-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK10-NEXT: store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK10: omp.inner.for.cond:
|
|
// CHECK10-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18
|
|
// CHECK10-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !18
|
|
// CHECK10-NEXT: [[CMP:%.*]] = icmp ule i64 [[TMP6]], [[TMP7]]
|
|
// CHECK10-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK10: omp.inner.for.body:
|
|
// CHECK10-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18
|
|
// CHECK10-NEXT: [[MUL:%.*]] = mul i64 [[TMP8]], 400
|
|
// CHECK10-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]
|
|
// CHECK10-NEXT: store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !18
|
|
// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[B]], align 4, !llvm.access.group !18
|
|
// CHECK10-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP9]] to double
|
|
// CHECK10-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00
|
|
// CHECK10-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
|
|
// CHECK10-NEXT: store double [[ADD2]], double* [[A]], align 8, !llvm.access.group !18
|
|
// CHECK10-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
|
|
// CHECK10-NEXT: [[TMP10:%.*]] = load double, double* [[A3]], align 8, !llvm.access.group !18
|
|
// CHECK10-NEXT: [[INC:%.*]] = fadd double [[TMP10]], 1.000000e+00
|
|
// CHECK10-NEXT: store double [[INC]], double* [[A3]], align 8, !llvm.access.group !18
|
|
// CHECK10-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16
|
|
// CHECK10-NEXT: [[TMP11:%.*]] = mul nsw i64 1, [[TMP2]]
|
|
// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP11]]
|
|
// CHECK10-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
|
|
// CHECK10-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2, !llvm.access.group !18
|
|
// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK10: omp.body.continue:
|
|
// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK10: omp.inner.for.inc:
|
|
// CHECK10-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18
|
|
// CHECK10-NEXT: [[ADD6:%.*]] = add i64 [[TMP12]], 1
|
|
// CHECK10-NEXT: store i64 [[ADD6]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18
|
|
// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]
|
|
// CHECK10: omp.inner.for.end:
|
|
// CHECK10-NEXT: store i64 400, i64* [[IT]], align 8
|
|
// CHECK10-NEXT: [[TMP13:%.*]] = mul nsw i64 1, [[TMP2]]
|
|
// CHECK10-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP13]]
|
|
// CHECK10-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX7]], i64 1
|
|
// CHECK10-NEXT: [[TMP14:%.*]] = load i16, i16* [[ARRAYIDX8]], align 2
|
|
// CHECK10-NEXT: [[CONV9:%.*]] = sext i16 [[TMP14]] to i32
|
|
// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[B]], align 4
|
|
// CHECK10-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[TMP15]]
|
|
// CHECK10-NEXT: [[TMP16:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
|
|
// CHECK10-NEXT: call void @llvm.stackrestore(i8* [[TMP16]])
|
|
// CHECK10-NEXT: ret i32 [[ADD10]]
|
|
//
|
|
//
|
|
// CHECK10-LABEL: define {{[^@]+}}@_ZL7fstatici
|
|
// CHECK10-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
|
|
// CHECK10-NEXT: entry:
|
|
// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK10-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK10-NEXT: [[AA:%.*]] = alloca i16, align 2
|
|
// CHECK10-NEXT: [[AAA:%.*]] = alloca i8, align 1
|
|
// CHECK10-NEXT: [[B:%.*]] = alloca [10 x i32], align 4
|
|
// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK10-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK10-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK10-NEXT: store i16 0, i16* [[AA]], align 2
|
|
// CHECK10-NEXT: store i8 0, i8* [[AAA]], align 1
|
|
// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK10-NEXT: store i32 429496720, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK10-NEXT: ret i32 [[TMP0]]
|
|
//
|
|
//
|
|
// CHECK10-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
|
|
// CHECK10-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat {
|
|
// CHECK10-NEXT: entry:
|
|
// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK10-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK10-NEXT: [[AA:%.*]] = alloca i16, align 2
|
|
// CHECK10-NEXT: [[B:%.*]] = alloca [10 x i32], align 4
|
|
// CHECK10-NEXT: [[TMP:%.*]] = alloca i64, align 8
|
|
// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
|
|
// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
|
|
// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
|
|
// CHECK10-NEXT: [[I:%.*]] = alloca i64, align 8
|
|
// CHECK10-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK10-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK10-NEXT: store i16 0, i16* [[AA]], align 2
|
|
// CHECK10-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK10-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK10-NEXT: store i64 [[TMP0]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK10: omp.inner.for.cond:
|
|
// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !21
|
|
// CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !21
|
|
// CHECK10-NEXT: [[CMP:%.*]] = icmp sle i64 [[TMP1]], [[TMP2]]
|
|
// CHECK10-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK10: omp.inner.for.body:
|
|
// CHECK10-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !21
|
|
// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP3]], 3
|
|
// CHECK10-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
|
|
// CHECK10-NEXT: store i64 [[ADD]], i64* [[I]], align 8, !llvm.access.group !21
|
|
// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !21
|
|
// CHECK10-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1
|
|
// CHECK10-NEXT: store i32 [[ADD1]], i32* [[A]], align 4, !llvm.access.group !21
|
|
// CHECK10-NEXT: [[TMP5:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !21
|
|
// CHECK10-NEXT: [[CONV:%.*]] = sext i16 [[TMP5]] to i32
|
|
// CHECK10-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 1
|
|
// CHECK10-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
|
|
// CHECK10-NEXT: store i16 [[CONV3]], i16* [[AA]], align 2, !llvm.access.group !21
|
|
// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2
|
|
// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !21
|
|
// CHECK10-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP6]], 1
|
|
// CHECK10-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !21
|
|
// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK10: omp.body.continue:
|
|
// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK10: omp.inner.for.inc:
|
|
// CHECK10-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !21
|
|
// CHECK10-NEXT: [[ADD5:%.*]] = add nsw i64 [[TMP7]], 1
|
|
// CHECK10-NEXT: store i64 [[ADD5]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !21
|
|
// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]]
|
|
// CHECK10: omp.inner.for.end:
|
|
// CHECK10-NEXT: store i64 11, i64* [[I]], align 8
|
|
// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK10-NEXT: ret i32 [[TMP8]]
|
|
//
|
|
//
|
|
// CHECK11-LABEL: define {{[^@]+}}@_Z7get_valv
|
|
// CHECK11-SAME: () #[[ATTR0:[0-9]+]] {
|
|
// CHECK11-NEXT: entry:
|
|
// CHECK11-NEXT: ret i64 0
|
|
//
|
|
//
|
|
// CHECK11-LABEL: define {{[^@]+}}@_Z3fooi
|
|
// CHECK11-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
|
|
// CHECK11-NEXT: entry:
|
|
// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[AA:%.*]] = alloca i16, align 2
|
|
// CHECK11-NEXT: [[B:%.*]] = alloca [10 x float], align 4
|
|
// CHECK11-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4
|
|
// CHECK11-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8
|
|
// CHECK11-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4
|
|
// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[K:%.*]] = alloca i64, align 8
|
|
// CHECK11-NEXT: [[_TMP3:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[DOTOMP_LB4:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[DOTOMP_UB5:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[DOTOMP_IV6:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[DOTLINEAR_START:%.*]] = alloca i64, align 8
|
|
// CHECK11-NEXT: [[I7:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[K8:%.*]] = alloca i64, align 8
|
|
// CHECK11-NEXT: [[LIN:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[_TMP21:%.*]] = alloca i64, align 4
|
|
// CHECK11-NEXT: [[DOTOMP_LB22:%.*]] = alloca i64, align 8
|
|
// CHECK11-NEXT: [[DOTOMP_UB23:%.*]] = alloca i64, align 8
|
|
// CHECK11-NEXT: [[DOTOMP_IV24:%.*]] = alloca i64, align 8
|
|
// CHECK11-NEXT: [[DOTLINEAR_START25:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[DOTLINEAR_START26:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8
|
|
// CHECK11-NEXT: [[IT:%.*]] = alloca i64, align 8
|
|
// CHECK11-NEXT: [[LIN28:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[A29:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[_TMP58:%.*]] = alloca i16, align 2
|
|
// CHECK11-NEXT: [[DOTOMP_LB59:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[DOTOMP_UB60:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[DOTOMP_IV61:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[IT62:%.*]] = alloca i16, align 2
|
|
// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[_TMP77:%.*]] = alloca i8, align 1
|
|
// CHECK11-NEXT: [[DOTOMP_LB78:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[DOTOMP_UB79:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[DOTOMP_IV80:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[IT81:%.*]] = alloca i8, align 1
|
|
// CHECK11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK11-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK11-NEXT: store i16 0, i16* [[AA]], align 2
|
|
// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK11-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave()
|
|
// CHECK11-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4
|
|
// CHECK11-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4
|
|
// CHECK11-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4
|
|
// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK11-NEXT: [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]]
|
|
// CHECK11-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8
|
|
// CHECK11-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4
|
|
// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK11-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK11-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK11: omp.inner.for.cond:
|
|
// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
|
|
// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !3
|
|
// CHECK11-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
|
|
// CHECK11-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK11: omp.inner.for.body:
|
|
// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
|
|
// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5
|
|
// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]]
|
|
// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !3
|
|
// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK11: omp.body.continue:
|
|
// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK11: omp.inner.for.inc:
|
|
// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
|
|
// CHECK11-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
|
|
// CHECK11-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
|
|
// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]
|
|
// CHECK11: omp.inner.for.end:
|
|
// CHECK11-NEXT: store i32 33, i32* [[I]], align 4
|
|
// CHECK11-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv()
|
|
// CHECK11-NEXT: store i64 [[CALL]], i64* [[K]], align 8
|
|
// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB4]], align 4
|
|
// CHECK11-NEXT: store i32 8, i32* [[DOTOMP_UB5]], align 4
|
|
// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_LB4]], align 4
|
|
// CHECK11-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV6]], align 4
|
|
// CHECK11-NEXT: [[TMP10:%.*]] = load i64, i64* [[K]], align 8
|
|
// CHECK11-NEXT: store i64 [[TMP10]], i64* [[DOTLINEAR_START]], align 8
|
|
// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND9:%.*]]
|
|
// CHECK11: omp.inner.for.cond9:
|
|
// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !7
|
|
// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB5]], align 4, !llvm.access.group !7
|
|
// CHECK11-NEXT: [[CMP10:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]]
|
|
// CHECK11-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY11:%.*]], label [[OMP_INNER_FOR_END19:%.*]]
|
|
// CHECK11: omp.inner.for.body11:
|
|
// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !7
|
|
// CHECK11-NEXT: [[MUL12:%.*]] = mul nsw i32 [[TMP13]], 1
|
|
// CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL12]]
|
|
// CHECK11-NEXT: store i32 [[SUB]], i32* [[I7]], align 4, !llvm.access.group !7
|
|
// CHECK11-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8, !llvm.access.group !7
|
|
// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !7
|
|
// CHECK11-NEXT: [[MUL13:%.*]] = mul nsw i32 [[TMP15]], 3
|
|
// CHECK11-NEXT: [[CONV:%.*]] = sext i32 [[MUL13]] to i64
|
|
// CHECK11-NEXT: [[ADD14:%.*]] = add nsw i64 [[TMP14]], [[CONV]]
|
|
// CHECK11-NEXT: store i64 [[ADD14]], i64* [[K8]], align 8, !llvm.access.group !7
|
|
// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !7
|
|
// CHECK11-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP16]], 1
|
|
// CHECK11-NEXT: store i32 [[ADD15]], i32* [[A]], align 4, !llvm.access.group !7
|
|
// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE16:%.*]]
|
|
// CHECK11: omp.body.continue16:
|
|
// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC17:%.*]]
|
|
// CHECK11: omp.inner.for.inc17:
|
|
// CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !7
|
|
// CHECK11-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP17]], 1
|
|
// CHECK11-NEXT: store i32 [[ADD18]], i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !7
|
|
// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND9]], !llvm.loop [[LOOP8:![0-9]+]]
|
|
// CHECK11: omp.inner.for.end19:
|
|
// CHECK11-NEXT: store i32 1, i32* [[I7]], align 4
|
|
// CHECK11-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8
|
|
// CHECK11-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP18]], 27
|
|
// CHECK11-NEXT: store i64 [[ADD20]], i64* [[K]], align 8
|
|
// CHECK11-NEXT: store i32 12, i32* [[LIN]], align 4
|
|
// CHECK11-NEXT: store i64 0, i64* [[DOTOMP_LB22]], align 8
|
|
// CHECK11-NEXT: store i64 3, i64* [[DOTOMP_UB23]], align 8
|
|
// CHECK11-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_LB22]], align 8
|
|
// CHECK11-NEXT: store i64 [[TMP19]], i64* [[DOTOMP_IV24]], align 8
|
|
// CHECK11-NEXT: [[TMP20:%.*]] = load i32, i32* [[LIN]], align 4
|
|
// CHECK11-NEXT: store i32 [[TMP20]], i32* [[DOTLINEAR_START25]], align 4
|
|
// CHECK11-NEXT: [[TMP21:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK11-NEXT: store i32 [[TMP21]], i32* [[DOTLINEAR_START26]], align 4
|
|
// CHECK11-NEXT: [[CALL27:%.*]] = call i64 @_Z7get_valv()
|
|
// CHECK11-NEXT: store i64 [[CALL27]], i64* [[DOTLINEAR_STEP]], align 8
|
|
// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND30:%.*]]
|
|
// CHECK11: omp.inner.for.cond30:
|
|
// CHECK11-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !10
|
|
// CHECK11-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_UB23]], align 8, !llvm.access.group !10
|
|
// CHECK11-NEXT: [[CMP31:%.*]] = icmp ule i64 [[TMP22]], [[TMP23]]
|
|
// CHECK11-NEXT: br i1 [[CMP31]], label [[OMP_INNER_FOR_BODY32:%.*]], label [[OMP_INNER_FOR_END49:%.*]]
|
|
// CHECK11: omp.inner.for.body32:
|
|
// CHECK11-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !10
|
|
// CHECK11-NEXT: [[MUL33:%.*]] = mul i64 [[TMP24]], 400
|
|
// CHECK11-NEXT: [[SUB34:%.*]] = sub i64 2000, [[MUL33]]
|
|
// CHECK11-NEXT: store i64 [[SUB34]], i64* [[IT]], align 8, !llvm.access.group !10
|
|
// CHECK11-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTLINEAR_START25]], align 4, !llvm.access.group !10
|
|
// CHECK11-NEXT: [[CONV35:%.*]] = sext i32 [[TMP25]] to i64
|
|
// CHECK11-NEXT: [[TMP26:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !10
|
|
// CHECK11-NEXT: [[TMP27:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !10
|
|
// CHECK11-NEXT: [[MUL36:%.*]] = mul i64 [[TMP26]], [[TMP27]]
|
|
// CHECK11-NEXT: [[ADD37:%.*]] = add i64 [[CONV35]], [[MUL36]]
|
|
// CHECK11-NEXT: [[CONV38:%.*]] = trunc i64 [[ADD37]] to i32
|
|
// CHECK11-NEXT: store i32 [[CONV38]], i32* [[LIN28]], align 4, !llvm.access.group !10
|
|
// CHECK11-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTLINEAR_START26]], align 4, !llvm.access.group !10
|
|
// CHECK11-NEXT: [[CONV39:%.*]] = sext i32 [[TMP28]] to i64
|
|
// CHECK11-NEXT: [[TMP29:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !10
|
|
// CHECK11-NEXT: [[TMP30:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !10
|
|
// CHECK11-NEXT: [[MUL40:%.*]] = mul i64 [[TMP29]], [[TMP30]]
|
|
// CHECK11-NEXT: [[ADD41:%.*]] = add i64 [[CONV39]], [[MUL40]]
|
|
// CHECK11-NEXT: [[CONV42:%.*]] = trunc i64 [[ADD41]] to i32
|
|
// CHECK11-NEXT: store i32 [[CONV42]], i32* [[A29]], align 4, !llvm.access.group !10
|
|
// CHECK11-NEXT: [[TMP31:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !10
|
|
// CHECK11-NEXT: [[CONV43:%.*]] = sext i16 [[TMP31]] to i32
|
|
// CHECK11-NEXT: [[ADD44:%.*]] = add nsw i32 [[CONV43]], 1
|
|
// CHECK11-NEXT: [[CONV45:%.*]] = trunc i32 [[ADD44]] to i16
|
|
// CHECK11-NEXT: store i16 [[CONV45]], i16* [[AA]], align 2, !llvm.access.group !10
|
|
// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE46:%.*]]
|
|
// CHECK11: omp.body.continue46:
|
|
// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC47:%.*]]
|
|
// CHECK11: omp.inner.for.inc47:
|
|
// CHECK11-NEXT: [[TMP32:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !10
|
|
// CHECK11-NEXT: [[ADD48:%.*]] = add i64 [[TMP32]], 1
|
|
// CHECK11-NEXT: store i64 [[ADD48]], i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !10
|
|
// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND30]], !llvm.loop [[LOOP11:![0-9]+]]
|
|
// CHECK11: omp.inner.for.end49:
|
|
// CHECK11-NEXT: store i64 400, i64* [[IT]], align 8
|
|
// CHECK11-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTLINEAR_START25]], align 4
|
|
// CHECK11-NEXT: [[CONV50:%.*]] = sext i32 [[TMP33]] to i64
|
|
// CHECK11-NEXT: [[TMP34:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
|
|
// CHECK11-NEXT: [[MUL51:%.*]] = mul i64 4, [[TMP34]]
|
|
// CHECK11-NEXT: [[ADD52:%.*]] = add i64 [[CONV50]], [[MUL51]]
|
|
// CHECK11-NEXT: [[CONV53:%.*]] = trunc i64 [[ADD52]] to i32
|
|
// CHECK11-NEXT: store i32 [[CONV53]], i32* [[LIN]], align 4
|
|
// CHECK11-NEXT: [[TMP35:%.*]] = load i32, i32* [[DOTLINEAR_START26]], align 4
|
|
// CHECK11-NEXT: [[CONV54:%.*]] = sext i32 [[TMP35]] to i64
|
|
// CHECK11-NEXT: [[TMP36:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
|
|
// CHECK11-NEXT: [[MUL55:%.*]] = mul i64 4, [[TMP36]]
|
|
// CHECK11-NEXT: [[ADD56:%.*]] = add i64 [[CONV54]], [[MUL55]]
|
|
// CHECK11-NEXT: [[CONV57:%.*]] = trunc i64 [[ADD56]] to i32
|
|
// CHECK11-NEXT: store i32 [[CONV57]], i32* [[A]], align 4
|
|
// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB59]], align 4
|
|
// CHECK11-NEXT: store i32 3, i32* [[DOTOMP_UB60]], align 4
|
|
// CHECK11-NEXT: [[TMP37:%.*]] = load i32, i32* [[DOTOMP_LB59]], align 4
|
|
// CHECK11-NEXT: store i32 [[TMP37]], i32* [[DOTOMP_IV61]], align 4
|
|
// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND63:%.*]]
|
|
// CHECK11: omp.inner.for.cond63:
|
|
// CHECK11-NEXT: [[TMP38:%.*]] = load i32, i32* [[DOTOMP_IV61]], align 4, !llvm.access.group !13
|
|
// CHECK11-NEXT: [[TMP39:%.*]] = load i32, i32* [[DOTOMP_UB60]], align 4, !llvm.access.group !13
|
|
// CHECK11-NEXT: [[CMP64:%.*]] = icmp sle i32 [[TMP38]], [[TMP39]]
|
|
// CHECK11-NEXT: br i1 [[CMP64]], label [[OMP_INNER_FOR_BODY65:%.*]], label [[OMP_INNER_FOR_END76:%.*]]
|
|
// CHECK11: omp.inner.for.body65:
|
|
// CHECK11-NEXT: [[TMP40:%.*]] = load i32, i32* [[DOTOMP_IV61]], align 4, !llvm.access.group !13
|
|
// CHECK11-NEXT: [[MUL66:%.*]] = mul nsw i32 [[TMP40]], 4
|
|
// CHECK11-NEXT: [[ADD67:%.*]] = add nsw i32 6, [[MUL66]]
|
|
// CHECK11-NEXT: [[CONV68:%.*]] = trunc i32 [[ADD67]] to i16
|
|
// CHECK11-NEXT: store i16 [[CONV68]], i16* [[IT62]], align 2, !llvm.access.group !13
|
|
// CHECK11-NEXT: [[TMP41:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !13
|
|
// CHECK11-NEXT: [[ADD69:%.*]] = add nsw i32 [[TMP41]], 1
|
|
// CHECK11-NEXT: store i32 [[ADD69]], i32* [[A]], align 4, !llvm.access.group !13
|
|
// CHECK11-NEXT: [[TMP42:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !13
|
|
// CHECK11-NEXT: [[CONV70:%.*]] = sext i16 [[TMP42]] to i32
|
|
// CHECK11-NEXT: [[ADD71:%.*]] = add nsw i32 [[CONV70]], 1
|
|
// CHECK11-NEXT: [[CONV72:%.*]] = trunc i32 [[ADD71]] to i16
|
|
// CHECK11-NEXT: store i16 [[CONV72]], i16* [[AA]], align 2, !llvm.access.group !13
|
|
// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE73:%.*]]
|
|
// CHECK11: omp.body.continue73:
|
|
// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC74:%.*]]
|
|
// CHECK11: omp.inner.for.inc74:
|
|
// CHECK11-NEXT: [[TMP43:%.*]] = load i32, i32* [[DOTOMP_IV61]], align 4, !llvm.access.group !13
|
|
// CHECK11-NEXT: [[ADD75:%.*]] = add nsw i32 [[TMP43]], 1
|
|
// CHECK11-NEXT: store i32 [[ADD75]], i32* [[DOTOMP_IV61]], align 4, !llvm.access.group !13
|
|
// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND63]], !llvm.loop [[LOOP14:![0-9]+]]
|
|
// CHECK11: omp.inner.for.end76:
|
|
// CHECK11-NEXT: store i16 22, i16* [[IT62]], align 2
|
|
// CHECK11-NEXT: [[TMP44:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK11-NEXT: store i32 [[TMP44]], i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB78]], align 4
|
|
// CHECK11-NEXT: store i32 25, i32* [[DOTOMP_UB79]], align 4
|
|
// CHECK11-NEXT: [[TMP45:%.*]] = load i32, i32* [[DOTOMP_LB78]], align 4
|
|
// CHECK11-NEXT: store i32 [[TMP45]], i32* [[DOTOMP_IV80]], align 4
|
|
// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND82:%.*]]
|
|
// CHECK11: omp.inner.for.cond82:
|
|
// CHECK11-NEXT: [[TMP46:%.*]] = load i32, i32* [[DOTOMP_IV80]], align 4, !llvm.access.group !16
|
|
// CHECK11-NEXT: [[TMP47:%.*]] = load i32, i32* [[DOTOMP_UB79]], align 4, !llvm.access.group !16
|
|
// CHECK11-NEXT: [[CMP83:%.*]] = icmp sle i32 [[TMP46]], [[TMP47]]
|
|
// CHECK11-NEXT: br i1 [[CMP83]], label [[OMP_INNER_FOR_BODY84:%.*]], label [[OMP_INNER_FOR_END109:%.*]]
|
|
// CHECK11: omp.inner.for.body84:
|
|
// CHECK11-NEXT: [[TMP48:%.*]] = load i32, i32* [[DOTOMP_IV80]], align 4, !llvm.access.group !16
|
|
// CHECK11-NEXT: [[MUL85:%.*]] = mul nsw i32 [[TMP48]], 1
|
|
// CHECK11-NEXT: [[SUB86:%.*]] = sub nsw i32 122, [[MUL85]]
|
|
// CHECK11-NEXT: [[CONV87:%.*]] = trunc i32 [[SUB86]] to i8
|
|
// CHECK11-NEXT: store i8 [[CONV87]], i8* [[IT81]], align 1, !llvm.access.group !16
|
|
// CHECK11-NEXT: [[TMP49:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !16
|
|
// CHECK11-NEXT: [[ADD88:%.*]] = add nsw i32 [[TMP49]], 1
|
|
// CHECK11-NEXT: store i32 [[ADD88]], i32* [[A]], align 4, !llvm.access.group !16
|
|
// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 2
|
|
// CHECK11-NEXT: [[TMP50:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !16
|
|
// CHECK11-NEXT: [[CONV89:%.*]] = fpext float [[TMP50]] to double
|
|
// CHECK11-NEXT: [[ADD90:%.*]] = fadd double [[CONV89]], 1.000000e+00
|
|
// CHECK11-NEXT: [[CONV91:%.*]] = fptrunc double [[ADD90]] to float
|
|
// CHECK11-NEXT: store float [[CONV91]], float* [[ARRAYIDX]], align 4, !llvm.access.group !16
|
|
// CHECK11-NEXT: [[ARRAYIDX92:%.*]] = getelementptr inbounds float, float* [[VLA]], i32 3
|
|
// CHECK11-NEXT: [[TMP51:%.*]] = load float, float* [[ARRAYIDX92]], align 4, !llvm.access.group !16
|
|
// CHECK11-NEXT: [[CONV93:%.*]] = fpext float [[TMP51]] to double
|
|
// CHECK11-NEXT: [[ADD94:%.*]] = fadd double [[CONV93]], 1.000000e+00
|
|
// CHECK11-NEXT: [[CONV95:%.*]] = fptrunc double [[ADD94]] to float
|
|
// CHECK11-NEXT: store float [[CONV95]], float* [[ARRAYIDX92]], align 4, !llvm.access.group !16
|
|
// CHECK11-NEXT: [[ARRAYIDX96:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i32 0, i32 1
|
|
// CHECK11-NEXT: [[ARRAYIDX97:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX96]], i32 0, i32 2
|
|
// CHECK11-NEXT: [[TMP52:%.*]] = load double, double* [[ARRAYIDX97]], align 8, !llvm.access.group !16
|
|
// CHECK11-NEXT: [[ADD98:%.*]] = fadd double [[TMP52]], 1.000000e+00
|
|
// CHECK11-NEXT: store double [[ADD98]], double* [[ARRAYIDX97]], align 8, !llvm.access.group !16
|
|
// CHECK11-NEXT: [[TMP53:%.*]] = mul nsw i32 1, [[TMP2]]
|
|
// CHECK11-NEXT: [[ARRAYIDX99:%.*]] = getelementptr inbounds double, double* [[VLA1]], i32 [[TMP53]]
|
|
// CHECK11-NEXT: [[ARRAYIDX100:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX99]], i32 3
|
|
// CHECK11-NEXT: [[TMP54:%.*]] = load double, double* [[ARRAYIDX100]], align 8, !llvm.access.group !16
|
|
// CHECK11-NEXT: [[ADD101:%.*]] = fadd double [[TMP54]], 1.000000e+00
|
|
// CHECK11-NEXT: store double [[ADD101]], double* [[ARRAYIDX100]], align 8, !llvm.access.group !16
|
|
// CHECK11-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0
|
|
// CHECK11-NEXT: [[TMP55:%.*]] = load i64, i64* [[X]], align 4, !llvm.access.group !16
|
|
// CHECK11-NEXT: [[ADD102:%.*]] = add nsw i64 [[TMP55]], 1
|
|
// CHECK11-NEXT: store i64 [[ADD102]], i64* [[X]], align 4, !llvm.access.group !16
|
|
// CHECK11-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1
|
|
// CHECK11-NEXT: [[TMP56:%.*]] = load i8, i8* [[Y]], align 4, !llvm.access.group !16
|
|
// CHECK11-NEXT: [[CONV103:%.*]] = sext i8 [[TMP56]] to i32
|
|
// CHECK11-NEXT: [[ADD104:%.*]] = add nsw i32 [[CONV103]], 1
|
|
// CHECK11-NEXT: [[CONV105:%.*]] = trunc i32 [[ADD104]] to i8
|
|
// CHECK11-NEXT: store i8 [[CONV105]], i8* [[Y]], align 4, !llvm.access.group !16
|
|
// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE106:%.*]]
|
|
// CHECK11: omp.body.continue106:
|
|
// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC107:%.*]]
|
|
// CHECK11: omp.inner.for.inc107:
|
|
// CHECK11-NEXT: [[TMP57:%.*]] = load i32, i32* [[DOTOMP_IV80]], align 4, !llvm.access.group !16
|
|
// CHECK11-NEXT: [[ADD108:%.*]] = add nsw i32 [[TMP57]], 1
|
|
// CHECK11-NEXT: store i32 [[ADD108]], i32* [[DOTOMP_IV80]], align 4, !llvm.access.group !16
|
|
// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND82]], !llvm.loop [[LOOP17:![0-9]+]]
|
|
// CHECK11: omp.inner.for.end109:
|
|
// CHECK11-NEXT: store i8 96, i8* [[IT81]], align 1
|
|
// CHECK11-NEXT: [[TMP58:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK11-NEXT: [[TMP59:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
|
|
// CHECK11-NEXT: call void @llvm.stackrestore(i8* [[TMP59]])
|
|
// CHECK11-NEXT: ret i32 [[TMP58]]
|
|
//
|
|
//
|
|
// CHECK11-LABEL: define {{[^@]+}}@_Z3bari
|
|
// CHECK11-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
|
|
// CHECK11-NEXT: entry:
|
|
// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4
|
|
// CHECK11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK11-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK11-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]])
|
|
// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
|
|
// CHECK11-NEXT: store i32 [[ADD]], i32* [[A]], align 4
|
|
// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK11-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]])
|
|
// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK11-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
|
|
// CHECK11-NEXT: store i32 [[ADD2]], i32* [[A]], align 4
|
|
// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK11-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]])
|
|
// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK11-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
|
|
// CHECK11-NEXT: store i32 [[ADD4]], i32* [[A]], align 4
|
|
// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK11-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]])
|
|
// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK11-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
|
|
// CHECK11-NEXT: store i32 [[ADD6]], i32* [[A]], align 4
|
|
// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK11-NEXT: ret i32 [[TMP8]]
|
|
//
|
|
//
|
|
// CHECK11-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
|
|
// CHECK11-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 {
|
|
// CHECK11-NEXT: entry:
|
|
// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
|
|
// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[B:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4
|
|
// CHECK11-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[TMP:%.*]] = alloca i64, align 4
|
|
// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
|
|
// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
|
|
// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
|
|
// CHECK11-NEXT: [[IT:%.*]] = alloca i64, align 8
|
|
// CHECK11-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
|
|
// CHECK11-NEXT: store i32 [[ADD]], i32* [[B]], align 4
|
|
// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK11-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave()
|
|
// CHECK11-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4
|
|
// CHECK11-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]]
|
|
// CHECK11-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2
|
|
// CHECK11-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4
|
|
// CHECK11-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK11-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK11-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK11-NEXT: store i64 [[TMP4]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK11: omp.inner.for.cond:
|
|
// CHECK11-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !19
|
|
// CHECK11-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !19
|
|
// CHECK11-NEXT: [[CMP:%.*]] = icmp ule i64 [[TMP5]], [[TMP6]]
|
|
// CHECK11-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK11: omp.inner.for.body:
|
|
// CHECK11-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !19
|
|
// CHECK11-NEXT: [[MUL:%.*]] = mul i64 [[TMP7]], 400
|
|
// CHECK11-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]
|
|
// CHECK11-NEXT: store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !19
|
|
// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[B]], align 4, !llvm.access.group !19
|
|
// CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP8]] to double
|
|
// CHECK11-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00
|
|
// CHECK11-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
|
|
// CHECK11-NEXT: store double [[ADD2]], double* [[A]], align 4, !llvm.access.group !19
|
|
// CHECK11-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
|
|
// CHECK11-NEXT: [[TMP9:%.*]] = load double, double* [[A3]], align 4, !llvm.access.group !19
|
|
// CHECK11-NEXT: [[INC:%.*]] = fadd double [[TMP9]], 1.000000e+00
|
|
// CHECK11-NEXT: store double [[INC]], double* [[A3]], align 4, !llvm.access.group !19
|
|
// CHECK11-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16
|
|
// CHECK11-NEXT: [[TMP10:%.*]] = mul nsw i32 1, [[TMP1]]
|
|
// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP10]]
|
|
// CHECK11-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
|
|
// CHECK11-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2, !llvm.access.group !19
|
|
// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK11: omp.body.continue:
|
|
// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK11: omp.inner.for.inc:
|
|
// CHECK11-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !19
|
|
// CHECK11-NEXT: [[ADD6:%.*]] = add i64 [[TMP11]], 1
|
|
// CHECK11-NEXT: store i64 [[ADD6]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !19
|
|
// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]]
|
|
// CHECK11: omp.inner.for.end:
|
|
// CHECK11-NEXT: store i64 400, i64* [[IT]], align 8
|
|
// CHECK11-NEXT: [[TMP12:%.*]] = mul nsw i32 1, [[TMP1]]
|
|
// CHECK11-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP12]]
|
|
// CHECK11-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX7]], i32 1
|
|
// CHECK11-NEXT: [[TMP13:%.*]] = load i16, i16* [[ARRAYIDX8]], align 2
|
|
// CHECK11-NEXT: [[CONV9:%.*]] = sext i16 [[TMP13]] to i32
|
|
// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[B]], align 4
|
|
// CHECK11-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[TMP14]]
|
|
// CHECK11-NEXT: [[TMP15:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
|
|
// CHECK11-NEXT: call void @llvm.stackrestore(i8* [[TMP15]])
|
|
// CHECK11-NEXT: ret i32 [[ADD10]]
|
|
//
|
|
//
|
|
// CHECK11-LABEL: define {{[^@]+}}@_ZL7fstatici
|
|
// CHECK11-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
|
|
// CHECK11-NEXT: entry:
|
|
// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[AA:%.*]] = alloca i16, align 2
|
|
// CHECK11-NEXT: [[AAA:%.*]] = alloca i8, align 1
|
|
// CHECK11-NEXT: [[B:%.*]] = alloca [10 x i32], align 4
|
|
// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK11-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK11-NEXT: store i16 0, i16* [[AA]], align 2
|
|
// CHECK11-NEXT: store i8 0, i8* [[AAA]], align 1
|
|
// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK11-NEXT: store i32 429496720, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK11-NEXT: ret i32 [[TMP0]]
|
|
//
|
|
//
|
|
// CHECK11-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
|
|
// CHECK11-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat {
|
|
// CHECK11-NEXT: entry:
|
|
// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[AA:%.*]] = alloca i16, align 2
|
|
// CHECK11-NEXT: [[B:%.*]] = alloca [10 x i32], align 4
|
|
// CHECK11-NEXT: [[TMP:%.*]] = alloca i64, align 4
|
|
// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
|
|
// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
|
|
// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
|
|
// CHECK11-NEXT: [[I:%.*]] = alloca i64, align 8
|
|
// CHECK11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK11-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK11-NEXT: store i16 0, i16* [[AA]], align 2
|
|
// CHECK11-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK11-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK11-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK11-NEXT: store i64 [[TMP0]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK11: omp.inner.for.cond:
|
|
// CHECK11-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !22
|
|
// CHECK11-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !22
|
|
// CHECK11-NEXT: [[CMP:%.*]] = icmp sle i64 [[TMP1]], [[TMP2]]
|
|
// CHECK11-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK11: omp.inner.for.body:
|
|
// CHECK11-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !22
|
|
// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP3]], 3
|
|
// CHECK11-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
|
|
// CHECK11-NEXT: store i64 [[ADD]], i64* [[I]], align 8, !llvm.access.group !22
|
|
// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !22
|
|
// CHECK11-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1
|
|
// CHECK11-NEXT: store i32 [[ADD1]], i32* [[A]], align 4, !llvm.access.group !22
|
|
// CHECK11-NEXT: [[TMP5:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !22
|
|
// CHECK11-NEXT: [[CONV:%.*]] = sext i16 [[TMP5]] to i32
|
|
// CHECK11-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 1
|
|
// CHECK11-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
|
|
// CHECK11-NEXT: store i16 [[CONV3]], i16* [[AA]], align 2, !llvm.access.group !22
|
|
// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2
|
|
// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !22
|
|
// CHECK11-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP6]], 1
|
|
// CHECK11-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !22
|
|
// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK11: omp.body.continue:
|
|
// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK11: omp.inner.for.inc:
|
|
// CHECK11-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !22
|
|
// CHECK11-NEXT: [[ADD5:%.*]] = add nsw i64 [[TMP7]], 1
|
|
// CHECK11-NEXT: store i64 [[ADD5]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !22
|
|
// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]]
|
|
// CHECK11: omp.inner.for.end:
|
|
// CHECK11-NEXT: store i64 11, i64* [[I]], align 8
|
|
// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK11-NEXT: ret i32 [[TMP8]]
|
|
//
|
|
//
|
|
// CHECK12-LABEL: define {{[^@]+}}@_Z7get_valv
|
|
// CHECK12-SAME: () #[[ATTR0:[0-9]+]] {
|
|
// CHECK12-NEXT: entry:
|
|
// CHECK12-NEXT: ret i64 0
|
|
//
|
|
//
|
|
// CHECK12-LABEL: define {{[^@]+}}@_Z3fooi
|
|
// CHECK12-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
|
|
// CHECK12-NEXT: entry:
|
|
// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[AA:%.*]] = alloca i16, align 2
|
|
// CHECK12-NEXT: [[B:%.*]] = alloca [10 x float], align 4
|
|
// CHECK12-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4
|
|
// CHECK12-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8
|
|
// CHECK12-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4
|
|
// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[K:%.*]] = alloca i64, align 8
|
|
// CHECK12-NEXT: [[_TMP3:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[DOTOMP_LB4:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[DOTOMP_UB5:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[DOTOMP_IV6:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[DOTLINEAR_START:%.*]] = alloca i64, align 8
|
|
// CHECK12-NEXT: [[I7:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[K8:%.*]] = alloca i64, align 8
|
|
// CHECK12-NEXT: [[LIN:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[_TMP21:%.*]] = alloca i64, align 4
|
|
// CHECK12-NEXT: [[DOTOMP_LB22:%.*]] = alloca i64, align 8
|
|
// CHECK12-NEXT: [[DOTOMP_UB23:%.*]] = alloca i64, align 8
|
|
// CHECK12-NEXT: [[DOTOMP_IV24:%.*]] = alloca i64, align 8
|
|
// CHECK12-NEXT: [[DOTLINEAR_START25:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[DOTLINEAR_START26:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8
|
|
// CHECK12-NEXT: [[IT:%.*]] = alloca i64, align 8
|
|
// CHECK12-NEXT: [[LIN28:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[A29:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[_TMP58:%.*]] = alloca i16, align 2
|
|
// CHECK12-NEXT: [[DOTOMP_LB59:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[DOTOMP_UB60:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[DOTOMP_IV61:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[IT62:%.*]] = alloca i16, align 2
|
|
// CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[_TMP77:%.*]] = alloca i8, align 1
|
|
// CHECK12-NEXT: [[DOTOMP_LB78:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[DOTOMP_UB79:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[DOTOMP_IV80:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[IT81:%.*]] = alloca i8, align 1
|
|
// CHECK12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK12-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK12-NEXT: store i16 0, i16* [[AA]], align 2
|
|
// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK12-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave()
|
|
// CHECK12-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4
|
|
// CHECK12-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4
|
|
// CHECK12-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4
|
|
// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK12-NEXT: [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]]
|
|
// CHECK12-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8
|
|
// CHECK12-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4
|
|
// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK12-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK12-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK12: omp.inner.for.cond:
|
|
// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
|
|
// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !3
|
|
// CHECK12-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
|
|
// CHECK12-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK12: omp.inner.for.body:
|
|
// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
|
|
// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5
|
|
// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]]
|
|
// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !3
|
|
// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK12: omp.body.continue:
|
|
// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK12: omp.inner.for.inc:
|
|
// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
|
|
// CHECK12-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
|
|
// CHECK12-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
|
|
// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]
|
|
// CHECK12: omp.inner.for.end:
|
|
// CHECK12-NEXT: store i32 33, i32* [[I]], align 4
|
|
// CHECK12-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv()
|
|
// CHECK12-NEXT: store i64 [[CALL]], i64* [[K]], align 8
|
|
// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_LB4]], align 4
|
|
// CHECK12-NEXT: store i32 8, i32* [[DOTOMP_UB5]], align 4
|
|
// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_LB4]], align 4
|
|
// CHECK12-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV6]], align 4
|
|
// CHECK12-NEXT: [[TMP10:%.*]] = load i64, i64* [[K]], align 8
|
|
// CHECK12-NEXT: store i64 [[TMP10]], i64* [[DOTLINEAR_START]], align 8
|
|
// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND9:%.*]]
|
|
// CHECK12: omp.inner.for.cond9:
|
|
// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !7
|
|
// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB5]], align 4, !llvm.access.group !7
|
|
// CHECK12-NEXT: [[CMP10:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]]
|
|
// CHECK12-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY11:%.*]], label [[OMP_INNER_FOR_END19:%.*]]
|
|
// CHECK12: omp.inner.for.body11:
|
|
// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !7
|
|
// CHECK12-NEXT: [[MUL12:%.*]] = mul nsw i32 [[TMP13]], 1
|
|
// CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL12]]
|
|
// CHECK12-NEXT: store i32 [[SUB]], i32* [[I7]], align 4, !llvm.access.group !7
|
|
// CHECK12-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8, !llvm.access.group !7
|
|
// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !7
|
|
// CHECK12-NEXT: [[MUL13:%.*]] = mul nsw i32 [[TMP15]], 3
|
|
// CHECK12-NEXT: [[CONV:%.*]] = sext i32 [[MUL13]] to i64
|
|
// CHECK12-NEXT: [[ADD14:%.*]] = add nsw i64 [[TMP14]], [[CONV]]
|
|
// CHECK12-NEXT: store i64 [[ADD14]], i64* [[K8]], align 8, !llvm.access.group !7
|
|
// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !7
|
|
// CHECK12-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP16]], 1
|
|
// CHECK12-NEXT: store i32 [[ADD15]], i32* [[A]], align 4, !llvm.access.group !7
|
|
// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE16:%.*]]
|
|
// CHECK12: omp.body.continue16:
|
|
// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC17:%.*]]
|
|
// CHECK12: omp.inner.for.inc17:
|
|
// CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !7
|
|
// CHECK12-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP17]], 1
|
|
// CHECK12-NEXT: store i32 [[ADD18]], i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !7
|
|
// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND9]], !llvm.loop [[LOOP8:![0-9]+]]
|
|
// CHECK12: omp.inner.for.end19:
|
|
// CHECK12-NEXT: store i32 1, i32* [[I7]], align 4
|
|
// CHECK12-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8
|
|
// CHECK12-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP18]], 27
|
|
// CHECK12-NEXT: store i64 [[ADD20]], i64* [[K]], align 8
|
|
// CHECK12-NEXT: store i32 12, i32* [[LIN]], align 4
|
|
// CHECK12-NEXT: store i64 0, i64* [[DOTOMP_LB22]], align 8
|
|
// CHECK12-NEXT: store i64 3, i64* [[DOTOMP_UB23]], align 8
|
|
// CHECK12-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_LB22]], align 8
|
|
// CHECK12-NEXT: store i64 [[TMP19]], i64* [[DOTOMP_IV24]], align 8
|
|
// CHECK12-NEXT: [[TMP20:%.*]] = load i32, i32* [[LIN]], align 4
|
|
// CHECK12-NEXT: store i32 [[TMP20]], i32* [[DOTLINEAR_START25]], align 4
|
|
// CHECK12-NEXT: [[TMP21:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK12-NEXT: store i32 [[TMP21]], i32* [[DOTLINEAR_START26]], align 4
|
|
// CHECK12-NEXT: [[CALL27:%.*]] = call i64 @_Z7get_valv()
|
|
// CHECK12-NEXT: store i64 [[CALL27]], i64* [[DOTLINEAR_STEP]], align 8
|
|
// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND30:%.*]]
|
|
// CHECK12: omp.inner.for.cond30:
|
|
// CHECK12-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !10
|
|
// CHECK12-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_UB23]], align 8, !llvm.access.group !10
|
|
// CHECK12-NEXT: [[CMP31:%.*]] = icmp ule i64 [[TMP22]], [[TMP23]]
|
|
// CHECK12-NEXT: br i1 [[CMP31]], label [[OMP_INNER_FOR_BODY32:%.*]], label [[OMP_INNER_FOR_END49:%.*]]
|
|
// CHECK12: omp.inner.for.body32:
|
|
// CHECK12-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !10
|
|
// CHECK12-NEXT: [[MUL33:%.*]] = mul i64 [[TMP24]], 400
|
|
// CHECK12-NEXT: [[SUB34:%.*]] = sub i64 2000, [[MUL33]]
|
|
// CHECK12-NEXT: store i64 [[SUB34]], i64* [[IT]], align 8, !llvm.access.group !10
|
|
// CHECK12-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTLINEAR_START25]], align 4, !llvm.access.group !10
|
|
// CHECK12-NEXT: [[CONV35:%.*]] = sext i32 [[TMP25]] to i64
|
|
// CHECK12-NEXT: [[TMP26:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !10
|
|
// CHECK12-NEXT: [[TMP27:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !10
|
|
// CHECK12-NEXT: [[MUL36:%.*]] = mul i64 [[TMP26]], [[TMP27]]
|
|
// CHECK12-NEXT: [[ADD37:%.*]] = add i64 [[CONV35]], [[MUL36]]
|
|
// CHECK12-NEXT: [[CONV38:%.*]] = trunc i64 [[ADD37]] to i32
|
|
// CHECK12-NEXT: store i32 [[CONV38]], i32* [[LIN28]], align 4, !llvm.access.group !10
|
|
// CHECK12-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTLINEAR_START26]], align 4, !llvm.access.group !10
|
|
// CHECK12-NEXT: [[CONV39:%.*]] = sext i32 [[TMP28]] to i64
|
|
// CHECK12-NEXT: [[TMP29:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !10
|
|
// CHECK12-NEXT: [[TMP30:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !10
|
|
// CHECK12-NEXT: [[MUL40:%.*]] = mul i64 [[TMP29]], [[TMP30]]
|
|
// CHECK12-NEXT: [[ADD41:%.*]] = add i64 [[CONV39]], [[MUL40]]
|
|
// CHECK12-NEXT: [[CONV42:%.*]] = trunc i64 [[ADD41]] to i32
|
|
// CHECK12-NEXT: store i32 [[CONV42]], i32* [[A29]], align 4, !llvm.access.group !10
|
|
// CHECK12-NEXT: [[TMP31:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !10
|
|
// CHECK12-NEXT: [[CONV43:%.*]] = sext i16 [[TMP31]] to i32
|
|
// CHECK12-NEXT: [[ADD44:%.*]] = add nsw i32 [[CONV43]], 1
|
|
// CHECK12-NEXT: [[CONV45:%.*]] = trunc i32 [[ADD44]] to i16
|
|
// CHECK12-NEXT: store i16 [[CONV45]], i16* [[AA]], align 2, !llvm.access.group !10
|
|
// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE46:%.*]]
|
|
// CHECK12: omp.body.continue46:
|
|
// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC47:%.*]]
|
|
// CHECK12: omp.inner.for.inc47:
|
|
// CHECK12-NEXT: [[TMP32:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !10
|
|
// CHECK12-NEXT: [[ADD48:%.*]] = add i64 [[TMP32]], 1
|
|
// CHECK12-NEXT: store i64 [[ADD48]], i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !10
|
|
// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND30]], !llvm.loop [[LOOP11:![0-9]+]]
|
|
// CHECK12: omp.inner.for.end49:
|
|
// CHECK12-NEXT: store i64 400, i64* [[IT]], align 8
|
|
// CHECK12-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTLINEAR_START25]], align 4
|
|
// CHECK12-NEXT: [[CONV50:%.*]] = sext i32 [[TMP33]] to i64
|
|
// CHECK12-NEXT: [[TMP34:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
|
|
// CHECK12-NEXT: [[MUL51:%.*]] = mul i64 4, [[TMP34]]
|
|
// CHECK12-NEXT: [[ADD52:%.*]] = add i64 [[CONV50]], [[MUL51]]
|
|
// CHECK12-NEXT: [[CONV53:%.*]] = trunc i64 [[ADD52]] to i32
|
|
// CHECK12-NEXT: store i32 [[CONV53]], i32* [[LIN]], align 4
|
|
// CHECK12-NEXT: [[TMP35:%.*]] = load i32, i32* [[DOTLINEAR_START26]], align 4
|
|
// CHECK12-NEXT: [[CONV54:%.*]] = sext i32 [[TMP35]] to i64
|
|
// CHECK12-NEXT: [[TMP36:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
|
|
// CHECK12-NEXT: [[MUL55:%.*]] = mul i64 4, [[TMP36]]
|
|
// CHECK12-NEXT: [[ADD56:%.*]] = add i64 [[CONV54]], [[MUL55]]
|
|
// CHECK12-NEXT: [[CONV57:%.*]] = trunc i64 [[ADD56]] to i32
|
|
// CHECK12-NEXT: store i32 [[CONV57]], i32* [[A]], align 4
|
|
// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_LB59]], align 4
|
|
// CHECK12-NEXT: store i32 3, i32* [[DOTOMP_UB60]], align 4
|
|
// CHECK12-NEXT: [[TMP37:%.*]] = load i32, i32* [[DOTOMP_LB59]], align 4
|
|
// CHECK12-NEXT: store i32 [[TMP37]], i32* [[DOTOMP_IV61]], align 4
|
|
// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND63:%.*]]
|
|
// CHECK12: omp.inner.for.cond63:
|
|
// CHECK12-NEXT: [[TMP38:%.*]] = load i32, i32* [[DOTOMP_IV61]], align 4, !llvm.access.group !13
|
|
// CHECK12-NEXT: [[TMP39:%.*]] = load i32, i32* [[DOTOMP_UB60]], align 4, !llvm.access.group !13
|
|
// CHECK12-NEXT: [[CMP64:%.*]] = icmp sle i32 [[TMP38]], [[TMP39]]
|
|
// CHECK12-NEXT: br i1 [[CMP64]], label [[OMP_INNER_FOR_BODY65:%.*]], label [[OMP_INNER_FOR_END76:%.*]]
|
|
// CHECK12: omp.inner.for.body65:
|
|
// CHECK12-NEXT: [[TMP40:%.*]] = load i32, i32* [[DOTOMP_IV61]], align 4, !llvm.access.group !13
|
|
// CHECK12-NEXT: [[MUL66:%.*]] = mul nsw i32 [[TMP40]], 4
|
|
// CHECK12-NEXT: [[ADD67:%.*]] = add nsw i32 6, [[MUL66]]
|
|
// CHECK12-NEXT: [[CONV68:%.*]] = trunc i32 [[ADD67]] to i16
|
|
// CHECK12-NEXT: store i16 [[CONV68]], i16* [[IT62]], align 2, !llvm.access.group !13
|
|
// CHECK12-NEXT: [[TMP41:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !13
|
|
// CHECK12-NEXT: [[ADD69:%.*]] = add nsw i32 [[TMP41]], 1
|
|
// CHECK12-NEXT: store i32 [[ADD69]], i32* [[A]], align 4, !llvm.access.group !13
|
|
// CHECK12-NEXT: [[TMP42:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !13
|
|
// CHECK12-NEXT: [[CONV70:%.*]] = sext i16 [[TMP42]] to i32
|
|
// CHECK12-NEXT: [[ADD71:%.*]] = add nsw i32 [[CONV70]], 1
|
|
// CHECK12-NEXT: [[CONV72:%.*]] = trunc i32 [[ADD71]] to i16
|
|
// CHECK12-NEXT: store i16 [[CONV72]], i16* [[AA]], align 2, !llvm.access.group !13
|
|
// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE73:%.*]]
|
|
// CHECK12: omp.body.continue73:
|
|
// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC74:%.*]]
|
|
// CHECK12: omp.inner.for.inc74:
|
|
// CHECK12-NEXT: [[TMP43:%.*]] = load i32, i32* [[DOTOMP_IV61]], align 4, !llvm.access.group !13
|
|
// CHECK12-NEXT: [[ADD75:%.*]] = add nsw i32 [[TMP43]], 1
|
|
// CHECK12-NEXT: store i32 [[ADD75]], i32* [[DOTOMP_IV61]], align 4, !llvm.access.group !13
|
|
// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND63]], !llvm.loop [[LOOP14:![0-9]+]]
|
|
// CHECK12: omp.inner.for.end76:
|
|
// CHECK12-NEXT: store i16 22, i16* [[IT62]], align 2
|
|
// CHECK12-NEXT: [[TMP44:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK12-NEXT: store i32 [[TMP44]], i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_LB78]], align 4
|
|
// CHECK12-NEXT: store i32 25, i32* [[DOTOMP_UB79]], align 4
|
|
// CHECK12-NEXT: [[TMP45:%.*]] = load i32, i32* [[DOTOMP_LB78]], align 4
|
|
// CHECK12-NEXT: store i32 [[TMP45]], i32* [[DOTOMP_IV80]], align 4
|
|
// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND82:%.*]]
|
|
// CHECK12: omp.inner.for.cond82:
|
|
// CHECK12-NEXT: [[TMP46:%.*]] = load i32, i32* [[DOTOMP_IV80]], align 4, !llvm.access.group !16
|
|
// CHECK12-NEXT: [[TMP47:%.*]] = load i32, i32* [[DOTOMP_UB79]], align 4, !llvm.access.group !16
|
|
// CHECK12-NEXT: [[CMP83:%.*]] = icmp sle i32 [[TMP46]], [[TMP47]]
|
|
// CHECK12-NEXT: br i1 [[CMP83]], label [[OMP_INNER_FOR_BODY84:%.*]], label [[OMP_INNER_FOR_END109:%.*]]
|
|
// CHECK12: omp.inner.for.body84:
|
|
// CHECK12-NEXT: [[TMP48:%.*]] = load i32, i32* [[DOTOMP_IV80]], align 4, !llvm.access.group !16
|
|
// CHECK12-NEXT: [[MUL85:%.*]] = mul nsw i32 [[TMP48]], 1
|
|
// CHECK12-NEXT: [[SUB86:%.*]] = sub nsw i32 122, [[MUL85]]
|
|
// CHECK12-NEXT: [[CONV87:%.*]] = trunc i32 [[SUB86]] to i8
|
|
// CHECK12-NEXT: store i8 [[CONV87]], i8* [[IT81]], align 1, !llvm.access.group !16
|
|
// CHECK12-NEXT: [[TMP49:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !16
|
|
// CHECK12-NEXT: [[ADD88:%.*]] = add nsw i32 [[TMP49]], 1
|
|
// CHECK12-NEXT: store i32 [[ADD88]], i32* [[A]], align 4, !llvm.access.group !16
|
|
// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 2
|
|
// CHECK12-NEXT: [[TMP50:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !16
|
|
// CHECK12-NEXT: [[CONV89:%.*]] = fpext float [[TMP50]] to double
|
|
// CHECK12-NEXT: [[ADD90:%.*]] = fadd double [[CONV89]], 1.000000e+00
|
|
// CHECK12-NEXT: [[CONV91:%.*]] = fptrunc double [[ADD90]] to float
|
|
// CHECK12-NEXT: store float [[CONV91]], float* [[ARRAYIDX]], align 4, !llvm.access.group !16
|
|
// CHECK12-NEXT: [[ARRAYIDX92:%.*]] = getelementptr inbounds float, float* [[VLA]], i32 3
|
|
// CHECK12-NEXT: [[TMP51:%.*]] = load float, float* [[ARRAYIDX92]], align 4, !llvm.access.group !16
|
|
// CHECK12-NEXT: [[CONV93:%.*]] = fpext float [[TMP51]] to double
|
|
// CHECK12-NEXT: [[ADD94:%.*]] = fadd double [[CONV93]], 1.000000e+00
|
|
// CHECK12-NEXT: [[CONV95:%.*]] = fptrunc double [[ADD94]] to float
|
|
// CHECK12-NEXT: store float [[CONV95]], float* [[ARRAYIDX92]], align 4, !llvm.access.group !16
|
|
// CHECK12-NEXT: [[ARRAYIDX96:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i32 0, i32 1
|
|
// CHECK12-NEXT: [[ARRAYIDX97:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX96]], i32 0, i32 2
|
|
// CHECK12-NEXT: [[TMP52:%.*]] = load double, double* [[ARRAYIDX97]], align 8, !llvm.access.group !16
|
|
// CHECK12-NEXT: [[ADD98:%.*]] = fadd double [[TMP52]], 1.000000e+00
|
|
// CHECK12-NEXT: store double [[ADD98]], double* [[ARRAYIDX97]], align 8, !llvm.access.group !16
|
|
// CHECK12-NEXT: [[TMP53:%.*]] = mul nsw i32 1, [[TMP2]]
|
|
// CHECK12-NEXT: [[ARRAYIDX99:%.*]] = getelementptr inbounds double, double* [[VLA1]], i32 [[TMP53]]
|
|
// CHECK12-NEXT: [[ARRAYIDX100:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX99]], i32 3
|
|
// CHECK12-NEXT: [[TMP54:%.*]] = load double, double* [[ARRAYIDX100]], align 8, !llvm.access.group !16
|
|
// CHECK12-NEXT: [[ADD101:%.*]] = fadd double [[TMP54]], 1.000000e+00
|
|
// CHECK12-NEXT: store double [[ADD101]], double* [[ARRAYIDX100]], align 8, !llvm.access.group !16
|
|
// CHECK12-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0
|
|
// CHECK12-NEXT: [[TMP55:%.*]] = load i64, i64* [[X]], align 4, !llvm.access.group !16
|
|
// CHECK12-NEXT: [[ADD102:%.*]] = add nsw i64 [[TMP55]], 1
|
|
// CHECK12-NEXT: store i64 [[ADD102]], i64* [[X]], align 4, !llvm.access.group !16
|
|
// CHECK12-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1
|
|
// CHECK12-NEXT: [[TMP56:%.*]] = load i8, i8* [[Y]], align 4, !llvm.access.group !16
|
|
// CHECK12-NEXT: [[CONV103:%.*]] = sext i8 [[TMP56]] to i32
|
|
// CHECK12-NEXT: [[ADD104:%.*]] = add nsw i32 [[CONV103]], 1
|
|
// CHECK12-NEXT: [[CONV105:%.*]] = trunc i32 [[ADD104]] to i8
|
|
// CHECK12-NEXT: store i8 [[CONV105]], i8* [[Y]], align 4, !llvm.access.group !16
|
|
// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE106:%.*]]
|
|
// CHECK12: omp.body.continue106:
|
|
// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC107:%.*]]
|
|
// CHECK12: omp.inner.for.inc107:
|
|
// CHECK12-NEXT: [[TMP57:%.*]] = load i32, i32* [[DOTOMP_IV80]], align 4, !llvm.access.group !16
|
|
// CHECK12-NEXT: [[ADD108:%.*]] = add nsw i32 [[TMP57]], 1
|
|
// CHECK12-NEXT: store i32 [[ADD108]], i32* [[DOTOMP_IV80]], align 4, !llvm.access.group !16
|
|
// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND82]], !llvm.loop [[LOOP17:![0-9]+]]
|
|
// CHECK12: omp.inner.for.end109:
|
|
// CHECK12-NEXT: store i8 96, i8* [[IT81]], align 1
|
|
// CHECK12-NEXT: [[TMP58:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK12-NEXT: [[TMP59:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
|
|
// CHECK12-NEXT: call void @llvm.stackrestore(i8* [[TMP59]])
|
|
// CHECK12-NEXT: ret i32 [[TMP58]]
|
|
//
|
|
//
|
|
// CHECK12-LABEL: define {{[^@]+}}@_Z3bari
|
|
// CHECK12-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
|
|
// CHECK12-NEXT: entry:
|
|
// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4
|
|
// CHECK12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK12-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK12-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]])
|
|
// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
|
|
// CHECK12-NEXT: store i32 [[ADD]], i32* [[A]], align 4
|
|
// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK12-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]])
|
|
// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK12-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
|
|
// CHECK12-NEXT: store i32 [[ADD2]], i32* [[A]], align 4
|
|
// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK12-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]])
|
|
// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK12-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
|
|
// CHECK12-NEXT: store i32 [[ADD4]], i32* [[A]], align 4
|
|
// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK12-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]])
|
|
// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK12-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
|
|
// CHECK12-NEXT: store i32 [[ADD6]], i32* [[A]], align 4
|
|
// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK12-NEXT: ret i32 [[TMP8]]
|
|
//
|
|
//
|
|
// CHECK12-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
|
|
// CHECK12-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 {
|
|
// CHECK12-NEXT: entry:
|
|
// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
|
|
// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[B:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4
|
|
// CHECK12-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[TMP:%.*]] = alloca i64, align 4
|
|
// CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
|
|
// CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
|
|
// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
|
|
// CHECK12-NEXT: [[IT:%.*]] = alloca i64, align 8
|
|
// CHECK12-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
|
|
// CHECK12-NEXT: store i32 [[ADD]], i32* [[B]], align 4
|
|
// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK12-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave()
|
|
// CHECK12-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4
|
|
// CHECK12-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]]
|
|
// CHECK12-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2
|
|
// CHECK12-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4
|
|
// CHECK12-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK12-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK12-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK12-NEXT: store i64 [[TMP4]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK12: omp.inner.for.cond:
|
|
// CHECK12-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !19
|
|
// CHECK12-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !19
|
|
// CHECK12-NEXT: [[CMP:%.*]] = icmp ule i64 [[TMP5]], [[TMP6]]
|
|
// CHECK12-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK12: omp.inner.for.body:
|
|
// CHECK12-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !19
|
|
// CHECK12-NEXT: [[MUL:%.*]] = mul i64 [[TMP7]], 400
|
|
// CHECK12-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]
|
|
// CHECK12-NEXT: store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !19
|
|
// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[B]], align 4, !llvm.access.group !19
|
|
// CHECK12-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP8]] to double
|
|
// CHECK12-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00
|
|
// CHECK12-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
|
|
// CHECK12-NEXT: store double [[ADD2]], double* [[A]], align 4, !llvm.access.group !19
|
|
// CHECK12-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
|
|
// CHECK12-NEXT: [[TMP9:%.*]] = load double, double* [[A3]], align 4, !llvm.access.group !19
|
|
// CHECK12-NEXT: [[INC:%.*]] = fadd double [[TMP9]], 1.000000e+00
|
|
// CHECK12-NEXT: store double [[INC]], double* [[A3]], align 4, !llvm.access.group !19
|
|
// CHECK12-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16
|
|
// CHECK12-NEXT: [[TMP10:%.*]] = mul nsw i32 1, [[TMP1]]
|
|
// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP10]]
|
|
// CHECK12-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
|
|
// CHECK12-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2, !llvm.access.group !19
|
|
// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK12: omp.body.continue:
|
|
// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK12: omp.inner.for.inc:
|
|
// CHECK12-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !19
|
|
// CHECK12-NEXT: [[ADD6:%.*]] = add i64 [[TMP11]], 1
|
|
// CHECK12-NEXT: store i64 [[ADD6]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !19
|
|
// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]]
|
|
// CHECK12: omp.inner.for.end:
|
|
// CHECK12-NEXT: store i64 400, i64* [[IT]], align 8
|
|
// CHECK12-NEXT: [[TMP12:%.*]] = mul nsw i32 1, [[TMP1]]
|
|
// CHECK12-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP12]]
|
|
// CHECK12-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX7]], i32 1
|
|
// CHECK12-NEXT: [[TMP13:%.*]] = load i16, i16* [[ARRAYIDX8]], align 2
|
|
// CHECK12-NEXT: [[CONV9:%.*]] = sext i16 [[TMP13]] to i32
|
|
// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[B]], align 4
|
|
// CHECK12-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[TMP14]]
|
|
// CHECK12-NEXT: [[TMP15:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
|
|
// CHECK12-NEXT: call void @llvm.stackrestore(i8* [[TMP15]])
|
|
// CHECK12-NEXT: ret i32 [[ADD10]]
|
|
//
|
|
//
|
|
// CHECK12-LABEL: define {{[^@]+}}@_ZL7fstatici
|
|
// CHECK12-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
|
|
// CHECK12-NEXT: entry:
|
|
// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[AA:%.*]] = alloca i16, align 2
|
|
// CHECK12-NEXT: [[AAA:%.*]] = alloca i8, align 1
|
|
// CHECK12-NEXT: [[B:%.*]] = alloca [10 x i32], align 4
|
|
// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK12-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK12-NEXT: store i16 0, i16* [[AA]], align 2
|
|
// CHECK12-NEXT: store i8 0, i8* [[AAA]], align 1
|
|
// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK12-NEXT: store i32 429496720, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK12-NEXT: ret i32 [[TMP0]]
|
|
//
|
|
//
|
|
// CHECK12-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
|
|
// CHECK12-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat {
|
|
// CHECK12-NEXT: entry:
|
|
// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[AA:%.*]] = alloca i16, align 2
|
|
// CHECK12-NEXT: [[B:%.*]] = alloca [10 x i32], align 4
|
|
// CHECK12-NEXT: [[TMP:%.*]] = alloca i64, align 4
|
|
// CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
|
|
// CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
|
|
// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
|
|
// CHECK12-NEXT: [[I:%.*]] = alloca i64, align 8
|
|
// CHECK12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK12-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK12-NEXT: store i16 0, i16* [[AA]], align 2
|
|
// CHECK12-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK12-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK12-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK12-NEXT: store i64 [[TMP0]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK12: omp.inner.for.cond:
|
|
// CHECK12-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !22
|
|
// CHECK12-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !22
|
|
// CHECK12-NEXT: [[CMP:%.*]] = icmp sle i64 [[TMP1]], [[TMP2]]
|
|
// CHECK12-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK12: omp.inner.for.body:
|
|
// CHECK12-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !22
|
|
// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP3]], 3
|
|
// CHECK12-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
|
|
// CHECK12-NEXT: store i64 [[ADD]], i64* [[I]], align 8, !llvm.access.group !22
|
|
// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !22
|
|
// CHECK12-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1
|
|
// CHECK12-NEXT: store i32 [[ADD1]], i32* [[A]], align 4, !llvm.access.group !22
|
|
// CHECK12-NEXT: [[TMP5:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !22
|
|
// CHECK12-NEXT: [[CONV:%.*]] = sext i16 [[TMP5]] to i32
|
|
// CHECK12-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 1
|
|
// CHECK12-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
|
|
// CHECK12-NEXT: store i16 [[CONV3]], i16* [[AA]], align 2, !llvm.access.group !22
|
|
// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2
|
|
// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !22
|
|
// CHECK12-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP6]], 1
|
|
// CHECK12-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !22
|
|
// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK12: omp.body.continue:
|
|
// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK12: omp.inner.for.inc:
|
|
// CHECK12-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !22
|
|
// CHECK12-NEXT: [[ADD5:%.*]] = add nsw i64 [[TMP7]], 1
|
|
// CHECK12-NEXT: store i64 [[ADD5]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !22
|
|
// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]]
|
|
// CHECK12: omp.inner.for.end:
|
|
// CHECK12-NEXT: store i64 11, i64* [[I]], align 8
|
|
// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK12-NEXT: ret i32 [[TMP8]]
|
|
//
|
|
//
|
|
// CHECK13-LABEL: define {{[^@]+}}@_Z7get_valv
|
|
// CHECK13-SAME: () #[[ATTR0:[0-9]+]] {
|
|
// CHECK13-NEXT: entry:
|
|
// CHECK13-NEXT: ret i64 0
|
|
//
|
|
//
|
|
// CHECK13-LABEL: define {{[^@]+}}@_Z3fooi
|
|
// CHECK13-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
|
|
// CHECK13-NEXT: entry:
|
|
// CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK13-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK13-NEXT: [[AA:%.*]] = alloca i16, align 2
|
|
// CHECK13-NEXT: [[B:%.*]] = alloca [10 x float], align 4
|
|
// CHECK13-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8
|
|
// CHECK13-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8
|
|
// CHECK13-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8
|
|
// CHECK13-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8
|
|
// CHECK13-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8
|
|
// CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4
|
|
// CHECK13-NEXT: [[K:%.*]] = alloca i64, align 8
|
|
// CHECK13-NEXT: [[_TMP3:%.*]] = alloca i32, align 4
|
|
// CHECK13-NEXT: [[DOTOMP_LB4:%.*]] = alloca i32, align 4
|
|
// CHECK13-NEXT: [[DOTOMP_UB5:%.*]] = alloca i32, align 4
|
|
// CHECK13-NEXT: [[DOTOMP_IV6:%.*]] = alloca i32, align 4
|
|
// CHECK13-NEXT: [[DOTLINEAR_START:%.*]] = alloca i64, align 8
|
|
// CHECK13-NEXT: [[I7:%.*]] = alloca i32, align 4
|
|
// CHECK13-NEXT: [[K8:%.*]] = alloca i64, align 8
|
|
// CHECK13-NEXT: [[LIN:%.*]] = alloca i32, align 4
|
|
// CHECK13-NEXT: [[_TMP21:%.*]] = alloca i64, align 8
|
|
// CHECK13-NEXT: [[DOTOMP_LB22:%.*]] = alloca i64, align 8
|
|
// CHECK13-NEXT: [[DOTOMP_UB23:%.*]] = alloca i64, align 8
|
|
// CHECK13-NEXT: [[DOTOMP_IV24:%.*]] = alloca i64, align 8
|
|
// CHECK13-NEXT: [[DOTLINEAR_START25:%.*]] = alloca i32, align 4
|
|
// CHECK13-NEXT: [[DOTLINEAR_START26:%.*]] = alloca i32, align 4
|
|
// CHECK13-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8
|
|
// CHECK13-NEXT: [[IT:%.*]] = alloca i64, align 8
|
|
// CHECK13-NEXT: [[LIN28:%.*]] = alloca i32, align 4
|
|
// CHECK13-NEXT: [[A29:%.*]] = alloca i32, align 4
|
|
// CHECK13-NEXT: [[_TMP58:%.*]] = alloca i16, align 2
|
|
// CHECK13-NEXT: [[DOTOMP_LB59:%.*]] = alloca i32, align 4
|
|
// CHECK13-NEXT: [[DOTOMP_UB60:%.*]] = alloca i32, align 4
|
|
// CHECK13-NEXT: [[DOTOMP_IV61:%.*]] = alloca i32, align 4
|
|
// CHECK13-NEXT: [[IT62:%.*]] = alloca i16, align 2
|
|
// CHECK13-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
|
// CHECK13-NEXT: [[_TMP77:%.*]] = alloca i8, align 1
|
|
// CHECK13-NEXT: [[DOTOMP_LB78:%.*]] = alloca i32, align 4
|
|
// CHECK13-NEXT: [[DOTOMP_UB79:%.*]] = alloca i32, align 4
|
|
// CHECK13-NEXT: [[DOTOMP_IV80:%.*]] = alloca i32, align 4
|
|
// CHECK13-NEXT: [[IT81:%.*]] = alloca i8, align 1
|
|
// CHECK13-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK13-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK13-NEXT: store i16 0, i16* [[AA]], align 2
|
|
// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK13-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
|
|
// CHECK13-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave()
|
|
// CHECK13-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8
|
|
// CHECK13-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4
|
|
// CHECK13-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8
|
|
// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK13-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64
|
|
// CHECK13-NEXT: [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]]
|
|
// CHECK13-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8
|
|
// CHECK13-NEXT: store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8
|
|
// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK13-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK13-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK13: omp.inner.for.cond:
|
|
// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
|
|
// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !2
|
|
// CHECK13-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
|
|
// CHECK13-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK13: omp.inner.for.body:
|
|
// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
|
|
// CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 5
|
|
// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]]
|
|
// CHECK13-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !2
|
|
// CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK13: omp.body.continue:
|
|
// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK13: omp.inner.for.inc:
|
|
// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
|
|
// CHECK13-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1
|
|
// CHECK13-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
|
|
// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]
|
|
// CHECK13: omp.inner.for.end:
|
|
// CHECK13-NEXT: store i32 33, i32* [[I]], align 4
|
|
// CHECK13-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv()
|
|
// CHECK13-NEXT: store i64 [[CALL]], i64* [[K]], align 8
|
|
// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_LB4]], align 4
|
|
// CHECK13-NEXT: store i32 8, i32* [[DOTOMP_UB5]], align 4
|
|
// CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_LB4]], align 4
|
|
// CHECK13-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV6]], align 4
|
|
// CHECK13-NEXT: [[TMP12:%.*]] = load i64, i64* [[K]], align 8
|
|
// CHECK13-NEXT: store i64 [[TMP12]], i64* [[DOTLINEAR_START]], align 8
|
|
// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND9:%.*]]
|
|
// CHECK13: omp.inner.for.cond9:
|
|
// CHECK13-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !6
|
|
// CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB5]], align 4, !llvm.access.group !6
|
|
// CHECK13-NEXT: [[CMP10:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
|
|
// CHECK13-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY11:%.*]], label [[OMP_INNER_FOR_END19:%.*]]
|
|
// CHECK13: omp.inner.for.body11:
|
|
// CHECK13-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !6
|
|
// CHECK13-NEXT: [[MUL12:%.*]] = mul nsw i32 [[TMP15]], 1
|
|
// CHECK13-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL12]]
|
|
// CHECK13-NEXT: store i32 [[SUB]], i32* [[I7]], align 4, !llvm.access.group !6
|
|
// CHECK13-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8, !llvm.access.group !6
|
|
// CHECK13-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !6
|
|
// CHECK13-NEXT: [[MUL13:%.*]] = mul nsw i32 [[TMP17]], 3
|
|
// CHECK13-NEXT: [[CONV:%.*]] = sext i32 [[MUL13]] to i64
|
|
// CHECK13-NEXT: [[ADD14:%.*]] = add nsw i64 [[TMP16]], [[CONV]]
|
|
// CHECK13-NEXT: store i64 [[ADD14]], i64* [[K8]], align 8, !llvm.access.group !6
|
|
// CHECK13-NEXT: [[TMP18:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !6
|
|
// CHECK13-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP18]], 1
|
|
// CHECK13-NEXT: store i32 [[ADD15]], i32* [[A]], align 4, !llvm.access.group !6
|
|
// CHECK13-NEXT: br label [[OMP_BODY_CONTINUE16:%.*]]
|
|
// CHECK13: omp.body.continue16:
|
|
// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC17:%.*]]
|
|
// CHECK13: omp.inner.for.inc17:
|
|
// CHECK13-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !6
|
|
// CHECK13-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP19]], 1
|
|
// CHECK13-NEXT: store i32 [[ADD18]], i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !6
|
|
// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND9]], !llvm.loop [[LOOP7:![0-9]+]]
|
|
// CHECK13: omp.inner.for.end19:
|
|
// CHECK13-NEXT: store i32 1, i32* [[I7]], align 4
|
|
// CHECK13-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8
|
|
// CHECK13-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP20]], 27
|
|
// CHECK13-NEXT: store i64 [[ADD20]], i64* [[K]], align 8
|
|
// CHECK13-NEXT: store i32 12, i32* [[LIN]], align 4
|
|
// CHECK13-NEXT: store i64 0, i64* [[DOTOMP_LB22]], align 8
|
|
// CHECK13-NEXT: store i64 3, i64* [[DOTOMP_UB23]], align 8
|
|
// CHECK13-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_LB22]], align 8
|
|
// CHECK13-NEXT: store i64 [[TMP21]], i64* [[DOTOMP_IV24]], align 8
|
|
// CHECK13-NEXT: [[TMP22:%.*]] = load i32, i32* [[LIN]], align 4
|
|
// CHECK13-NEXT: store i32 [[TMP22]], i32* [[DOTLINEAR_START25]], align 4
|
|
// CHECK13-NEXT: [[TMP23:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK13-NEXT: store i32 [[TMP23]], i32* [[DOTLINEAR_START26]], align 4
|
|
// CHECK13-NEXT: [[CALL27:%.*]] = call i64 @_Z7get_valv()
|
|
// CHECK13-NEXT: store i64 [[CALL27]], i64* [[DOTLINEAR_STEP]], align 8
|
|
// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND30:%.*]]
|
|
// CHECK13: omp.inner.for.cond30:
|
|
// CHECK13-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !9
|
|
// CHECK13-NEXT: [[TMP25:%.*]] = load i64, i64* [[DOTOMP_UB23]], align 8, !llvm.access.group !9
|
|
// CHECK13-NEXT: [[CMP31:%.*]] = icmp ule i64 [[TMP24]], [[TMP25]]
|
|
// CHECK13-NEXT: br i1 [[CMP31]], label [[OMP_INNER_FOR_BODY32:%.*]], label [[OMP_INNER_FOR_END49:%.*]]
|
|
// CHECK13: omp.inner.for.body32:
|
|
// CHECK13-NEXT: [[TMP26:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !9
|
|
// CHECK13-NEXT: [[MUL33:%.*]] = mul i64 [[TMP26]], 400
|
|
// CHECK13-NEXT: [[SUB34:%.*]] = sub i64 2000, [[MUL33]]
|
|
// CHECK13-NEXT: store i64 [[SUB34]], i64* [[IT]], align 8, !llvm.access.group !9
|
|
// CHECK13-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTLINEAR_START25]], align 4, !llvm.access.group !9
|
|
// CHECK13-NEXT: [[CONV35:%.*]] = sext i32 [[TMP27]] to i64
|
|
// CHECK13-NEXT: [[TMP28:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !9
|
|
// CHECK13-NEXT: [[TMP29:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !9
|
|
// CHECK13-NEXT: [[MUL36:%.*]] = mul i64 [[TMP28]], [[TMP29]]
|
|
// CHECK13-NEXT: [[ADD37:%.*]] = add i64 [[CONV35]], [[MUL36]]
|
|
// CHECK13-NEXT: [[CONV38:%.*]] = trunc i64 [[ADD37]] to i32
|
|
// CHECK13-NEXT: store i32 [[CONV38]], i32* [[LIN28]], align 4, !llvm.access.group !9
|
|
// CHECK13-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTLINEAR_START26]], align 4, !llvm.access.group !9
|
|
// CHECK13-NEXT: [[CONV39:%.*]] = sext i32 [[TMP30]] to i64
|
|
// CHECK13-NEXT: [[TMP31:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !9
|
|
// CHECK13-NEXT: [[TMP32:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !9
|
|
// CHECK13-NEXT: [[MUL40:%.*]] = mul i64 [[TMP31]], [[TMP32]]
|
|
// CHECK13-NEXT: [[ADD41:%.*]] = add i64 [[CONV39]], [[MUL40]]
|
|
// CHECK13-NEXT: [[CONV42:%.*]] = trunc i64 [[ADD41]] to i32
|
|
// CHECK13-NEXT: store i32 [[CONV42]], i32* [[A29]], align 4, !llvm.access.group !9
|
|
// CHECK13-NEXT: [[TMP33:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !9
|
|
// CHECK13-NEXT: [[CONV43:%.*]] = sext i16 [[TMP33]] to i32
|
|
// CHECK13-NEXT: [[ADD44:%.*]] = add nsw i32 [[CONV43]], 1
|
|
// CHECK13-NEXT: [[CONV45:%.*]] = trunc i32 [[ADD44]] to i16
|
|
// CHECK13-NEXT: store i16 [[CONV45]], i16* [[AA]], align 2, !llvm.access.group !9
|
|
// CHECK13-NEXT: br label [[OMP_BODY_CONTINUE46:%.*]]
|
|
// CHECK13: omp.body.continue46:
|
|
// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC47:%.*]]
|
|
// CHECK13: omp.inner.for.inc47:
|
|
// CHECK13-NEXT: [[TMP34:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !9
|
|
// CHECK13-NEXT: [[ADD48:%.*]] = add i64 [[TMP34]], 1
|
|
// CHECK13-NEXT: store i64 [[ADD48]], i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !9
|
|
// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND30]], !llvm.loop [[LOOP10:![0-9]+]]
|
|
// CHECK13: omp.inner.for.end49:
|
|
// CHECK13-NEXT: store i64 400, i64* [[IT]], align 8
|
|
// CHECK13-NEXT: [[TMP35:%.*]] = load i32, i32* [[DOTLINEAR_START25]], align 4
|
|
// CHECK13-NEXT: [[CONV50:%.*]] = sext i32 [[TMP35]] to i64
|
|
// CHECK13-NEXT: [[TMP36:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
|
|
// CHECK13-NEXT: [[MUL51:%.*]] = mul i64 4, [[TMP36]]
|
|
// CHECK13-NEXT: [[ADD52:%.*]] = add i64 [[CONV50]], [[MUL51]]
|
|
// CHECK13-NEXT: [[CONV53:%.*]] = trunc i64 [[ADD52]] to i32
|
|
// CHECK13-NEXT: store i32 [[CONV53]], i32* [[LIN]], align 4
|
|
// CHECK13-NEXT: [[TMP37:%.*]] = load i32, i32* [[DOTLINEAR_START26]], align 4
|
|
// CHECK13-NEXT: [[CONV54:%.*]] = sext i32 [[TMP37]] to i64
|
|
// CHECK13-NEXT: [[TMP38:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
|
|
// CHECK13-NEXT: [[MUL55:%.*]] = mul i64 4, [[TMP38]]
|
|
// CHECK13-NEXT: [[ADD56:%.*]] = add i64 [[CONV54]], [[MUL55]]
|
|
// CHECK13-NEXT: [[CONV57:%.*]] = trunc i64 [[ADD56]] to i32
|
|
// CHECK13-NEXT: store i32 [[CONV57]], i32* [[A]], align 4
|
|
// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_LB59]], align 4
|
|
// CHECK13-NEXT: store i32 3, i32* [[DOTOMP_UB60]], align 4
|
|
// CHECK13-NEXT: [[TMP39:%.*]] = load i32, i32* [[DOTOMP_LB59]], align 4
|
|
// CHECK13-NEXT: store i32 [[TMP39]], i32* [[DOTOMP_IV61]], align 4
|
|
// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND63:%.*]]
|
|
// CHECK13: omp.inner.for.cond63:
|
|
// CHECK13-NEXT: [[TMP40:%.*]] = load i32, i32* [[DOTOMP_IV61]], align 4, !llvm.access.group !12
|
|
// CHECK13-NEXT: [[TMP41:%.*]] = load i32, i32* [[DOTOMP_UB60]], align 4, !llvm.access.group !12
|
|
// CHECK13-NEXT: [[CMP64:%.*]] = icmp sle i32 [[TMP40]], [[TMP41]]
|
|
// CHECK13-NEXT: br i1 [[CMP64]], label [[OMP_INNER_FOR_BODY65:%.*]], label [[OMP_INNER_FOR_END76:%.*]]
|
|
// CHECK13: omp.inner.for.body65:
|
|
// CHECK13-NEXT: [[TMP42:%.*]] = load i32, i32* [[DOTOMP_IV61]], align 4, !llvm.access.group !12
|
|
// CHECK13-NEXT: [[MUL66:%.*]] = mul nsw i32 [[TMP42]], 4
|
|
// CHECK13-NEXT: [[ADD67:%.*]] = add nsw i32 6, [[MUL66]]
|
|
// CHECK13-NEXT: [[CONV68:%.*]] = trunc i32 [[ADD67]] to i16
|
|
// CHECK13-NEXT: store i16 [[CONV68]], i16* [[IT62]], align 2, !llvm.access.group !12
|
|
// CHECK13-NEXT: [[TMP43:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !12
|
|
// CHECK13-NEXT: [[ADD69:%.*]] = add nsw i32 [[TMP43]], 1
|
|
// CHECK13-NEXT: store i32 [[ADD69]], i32* [[A]], align 4, !llvm.access.group !12
|
|
// CHECK13-NEXT: [[TMP44:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !12
|
|
// CHECK13-NEXT: [[CONV70:%.*]] = sext i16 [[TMP44]] to i32
|
|
// CHECK13-NEXT: [[ADD71:%.*]] = add nsw i32 [[CONV70]], 1
|
|
// CHECK13-NEXT: [[CONV72:%.*]] = trunc i32 [[ADD71]] to i16
|
|
// CHECK13-NEXT: store i16 [[CONV72]], i16* [[AA]], align 2, !llvm.access.group !12
|
|
// CHECK13-NEXT: br label [[OMP_BODY_CONTINUE73:%.*]]
|
|
// CHECK13: omp.body.continue73:
|
|
// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC74:%.*]]
|
|
// CHECK13: omp.inner.for.inc74:
|
|
// CHECK13-NEXT: [[TMP45:%.*]] = load i32, i32* [[DOTOMP_IV61]], align 4, !llvm.access.group !12
|
|
// CHECK13-NEXT: [[ADD75:%.*]] = add nsw i32 [[TMP45]], 1
|
|
// CHECK13-NEXT: store i32 [[ADD75]], i32* [[DOTOMP_IV61]], align 4, !llvm.access.group !12
|
|
// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND63]], !llvm.loop [[LOOP13:![0-9]+]]
|
|
// CHECK13: omp.inner.for.end76:
|
|
// CHECK13-NEXT: store i16 22, i16* [[IT62]], align 2
|
|
// CHECK13-NEXT: [[TMP46:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK13-NEXT: store i32 [[TMP46]], i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_LB78]], align 4
|
|
// CHECK13-NEXT: store i32 25, i32* [[DOTOMP_UB79]], align 4
|
|
// CHECK13-NEXT: [[TMP47:%.*]] = load i32, i32* [[DOTOMP_LB78]], align 4
|
|
// CHECK13-NEXT: store i32 [[TMP47]], i32* [[DOTOMP_IV80]], align 4
|
|
// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND82:%.*]]
|
|
// CHECK13: omp.inner.for.cond82:
|
|
// CHECK13-NEXT: [[TMP48:%.*]] = load i32, i32* [[DOTOMP_IV80]], align 4, !llvm.access.group !15
|
|
// CHECK13-NEXT: [[TMP49:%.*]] = load i32, i32* [[DOTOMP_UB79]], align 4, !llvm.access.group !15
|
|
// CHECK13-NEXT: [[CMP83:%.*]] = icmp sle i32 [[TMP48]], [[TMP49]]
|
|
// CHECK13-NEXT: br i1 [[CMP83]], label [[OMP_INNER_FOR_BODY84:%.*]], label [[OMP_INNER_FOR_END109:%.*]]
|
|
// CHECK13: omp.inner.for.body84:
|
|
// CHECK13-NEXT: [[TMP50:%.*]] = load i32, i32* [[DOTOMP_IV80]], align 4, !llvm.access.group !15
|
|
// CHECK13-NEXT: [[MUL85:%.*]] = mul nsw i32 [[TMP50]], 1
|
|
// CHECK13-NEXT: [[SUB86:%.*]] = sub nsw i32 122, [[MUL85]]
|
|
// CHECK13-NEXT: [[CONV87:%.*]] = trunc i32 [[SUB86]] to i8
|
|
// CHECK13-NEXT: store i8 [[CONV87]], i8* [[IT81]], align 1, !llvm.access.group !15
|
|
// CHECK13-NEXT: [[TMP51:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !15
|
|
// CHECK13-NEXT: [[ADD88:%.*]] = add nsw i32 [[TMP51]], 1
|
|
// CHECK13-NEXT: store i32 [[ADD88]], i32* [[A]], align 4, !llvm.access.group !15
|
|
// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 2
|
|
// CHECK13-NEXT: [[TMP52:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !15
|
|
// CHECK13-NEXT: [[CONV89:%.*]] = fpext float [[TMP52]] to double
|
|
// CHECK13-NEXT: [[ADD90:%.*]] = fadd double [[CONV89]], 1.000000e+00
|
|
// CHECK13-NEXT: [[CONV91:%.*]] = fptrunc double [[ADD90]] to float
|
|
// CHECK13-NEXT: store float [[CONV91]], float* [[ARRAYIDX]], align 4, !llvm.access.group !15
|
|
// CHECK13-NEXT: [[ARRAYIDX92:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 3
|
|
// CHECK13-NEXT: [[TMP53:%.*]] = load float, float* [[ARRAYIDX92]], align 4, !llvm.access.group !15
|
|
// CHECK13-NEXT: [[CONV93:%.*]] = fpext float [[TMP53]] to double
|
|
// CHECK13-NEXT: [[ADD94:%.*]] = fadd double [[CONV93]], 1.000000e+00
|
|
// CHECK13-NEXT: [[CONV95:%.*]] = fptrunc double [[ADD94]] to float
|
|
// CHECK13-NEXT: store float [[CONV95]], float* [[ARRAYIDX92]], align 4, !llvm.access.group !15
|
|
// CHECK13-NEXT: [[ARRAYIDX96:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i64 0, i64 1
|
|
// CHECK13-NEXT: [[ARRAYIDX97:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX96]], i64 0, i64 2
|
|
// CHECK13-NEXT: [[TMP54:%.*]] = load double, double* [[ARRAYIDX97]], align 8, !llvm.access.group !15
|
|
// CHECK13-NEXT: [[ADD98:%.*]] = fadd double [[TMP54]], 1.000000e+00
|
|
// CHECK13-NEXT: store double [[ADD98]], double* [[ARRAYIDX97]], align 8, !llvm.access.group !15
|
|
// CHECK13-NEXT: [[TMP55:%.*]] = mul nsw i64 1, [[TMP4]]
|
|
// CHECK13-NEXT: [[ARRAYIDX99:%.*]] = getelementptr inbounds double, double* [[VLA1]], i64 [[TMP55]]
|
|
// CHECK13-NEXT: [[ARRAYIDX100:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX99]], i64 3
|
|
// CHECK13-NEXT: [[TMP56:%.*]] = load double, double* [[ARRAYIDX100]], align 8, !llvm.access.group !15
|
|
// CHECK13-NEXT: [[ADD101:%.*]] = fadd double [[TMP56]], 1.000000e+00
|
|
// CHECK13-NEXT: store double [[ADD101]], double* [[ARRAYIDX100]], align 8, !llvm.access.group !15
|
|
// CHECK13-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0
|
|
// CHECK13-NEXT: [[TMP57:%.*]] = load i64, i64* [[X]], align 8, !llvm.access.group !15
|
|
// CHECK13-NEXT: [[ADD102:%.*]] = add nsw i64 [[TMP57]], 1
|
|
// CHECK13-NEXT: store i64 [[ADD102]], i64* [[X]], align 8, !llvm.access.group !15
|
|
// CHECK13-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1
|
|
// CHECK13-NEXT: [[TMP58:%.*]] = load i8, i8* [[Y]], align 8, !llvm.access.group !15
|
|
// CHECK13-NEXT: [[CONV103:%.*]] = sext i8 [[TMP58]] to i32
|
|
// CHECK13-NEXT: [[ADD104:%.*]] = add nsw i32 [[CONV103]], 1
|
|
// CHECK13-NEXT: [[CONV105:%.*]] = trunc i32 [[ADD104]] to i8
|
|
// CHECK13-NEXT: store i8 [[CONV105]], i8* [[Y]], align 8, !llvm.access.group !15
|
|
// CHECK13-NEXT: br label [[OMP_BODY_CONTINUE106:%.*]]
|
|
// CHECK13: omp.body.continue106:
|
|
// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC107:%.*]]
|
|
// CHECK13: omp.inner.for.inc107:
|
|
// CHECK13-NEXT: [[TMP59:%.*]] = load i32, i32* [[DOTOMP_IV80]], align 4, !llvm.access.group !15
|
|
// CHECK13-NEXT: [[ADD108:%.*]] = add nsw i32 [[TMP59]], 1
|
|
// CHECK13-NEXT: store i32 [[ADD108]], i32* [[DOTOMP_IV80]], align 4, !llvm.access.group !15
|
|
// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND82]], !llvm.loop [[LOOP16:![0-9]+]]
|
|
// CHECK13: omp.inner.for.end109:
|
|
// CHECK13-NEXT: store i8 96, i8* [[IT81]], align 1
|
|
// CHECK13-NEXT: [[TMP60:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK13-NEXT: [[TMP61:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
|
|
// CHECK13-NEXT: call void @llvm.stackrestore(i8* [[TMP61]])
|
|
// CHECK13-NEXT: ret i32 [[TMP60]]
|
|
//
|
|
//
|
|
// CHECK13-LABEL: define {{[^@]+}}@_Z3bari
|
|
// CHECK13-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
|
|
// CHECK13-NEXT: entry:
|
|
// CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK13-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK13-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8
|
|
// CHECK13-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK13-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK13-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]])
|
|
// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
|
|
// CHECK13-NEXT: store i32 [[ADD]], i32* [[A]], align 4
|
|
// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK13-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]])
|
|
// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK13-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
|
|
// CHECK13-NEXT: store i32 [[ADD2]], i32* [[A]], align 4
|
|
// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK13-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]])
|
|
// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK13-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
|
|
// CHECK13-NEXT: store i32 [[ADD4]], i32* [[A]], align 4
|
|
// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK13-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]])
|
|
// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK13-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
|
|
// CHECK13-NEXT: store i32 [[ADD6]], i32* [[A]], align 4
|
|
// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK13-NEXT: ret i32 [[TMP8]]
|
|
//
|
|
//
|
|
// CHECK13-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
|
|
// CHECK13-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 {
|
|
// CHECK13-NEXT: entry:
|
|
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
|
|
// CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK13-NEXT: [[B:%.*]] = alloca i32, align 4
|
|
// CHECK13-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8
|
|
// CHECK13-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8
|
|
// CHECK13-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
|
|
// CHECK13-NEXT: [[TMP:%.*]] = alloca i64, align 8
|
|
// CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
|
|
// CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
|
|
// CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
|
|
// CHECK13-NEXT: [[IT:%.*]] = alloca i64, align 8
|
|
// CHECK13-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK13-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
|
|
// CHECK13-NEXT: store i32 [[ADD]], i32* [[B]], align 4
|
|
// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK13-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
|
|
// CHECK13-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave()
|
|
// CHECK13-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8
|
|
// CHECK13-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]]
|
|
// CHECK13-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2
|
|
// CHECK13-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8
|
|
// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK13-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 60
|
|
// CHECK13-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8
|
|
// CHECK13-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
|
|
// CHECK13-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK13-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK13-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK13-NEXT: store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK13-NEXT: [[TMP7:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
|
|
// CHECK13-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP7]] to i1
|
|
// CHECK13-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
|
|
// CHECK13: omp_if.then:
|
|
// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK13: omp.inner.for.cond:
|
|
// CHECK13-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18
|
|
// CHECK13-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !18
|
|
// CHECK13-NEXT: [[CMP2:%.*]] = icmp ule i64 [[TMP8]], [[TMP9]]
|
|
// CHECK13-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK13: omp.inner.for.body:
|
|
// CHECK13-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18
|
|
// CHECK13-NEXT: [[MUL:%.*]] = mul i64 [[TMP10]], 400
|
|
// CHECK13-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]
|
|
// CHECK13-NEXT: store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !18
|
|
// CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[B]], align 4, !llvm.access.group !18
|
|
// CHECK13-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP11]] to double
|
|
// CHECK13-NEXT: [[ADD3:%.*]] = fadd double [[CONV]], 1.500000e+00
|
|
// CHECK13-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
|
|
// CHECK13-NEXT: store double [[ADD3]], double* [[A]], align 8, !nontemporal !19, !llvm.access.group !18
|
|
// CHECK13-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
|
|
// CHECK13-NEXT: [[TMP12:%.*]] = load double, double* [[A4]], align 8, !nontemporal !19, !llvm.access.group !18
|
|
// CHECK13-NEXT: [[INC:%.*]] = fadd double [[TMP12]], 1.000000e+00
|
|
// CHECK13-NEXT: store double [[INC]], double* [[A4]], align 8, !nontemporal !19, !llvm.access.group !18
|
|
// CHECK13-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16
|
|
// CHECK13-NEXT: [[TMP13:%.*]] = mul nsw i64 1, [[TMP2]]
|
|
// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP13]]
|
|
// CHECK13-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
|
|
// CHECK13-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2, !llvm.access.group !18
|
|
// CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK13: omp.body.continue:
|
|
// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK13: omp.inner.for.inc:
|
|
// CHECK13-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18
|
|
// CHECK13-NEXT: [[ADD7:%.*]] = add i64 [[TMP14]], 1
|
|
// CHECK13-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18
|
|
// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]]
|
|
// CHECK13: omp.inner.for.end:
|
|
// CHECK13-NEXT: br label [[OMP_IF_END:%.*]]
|
|
// CHECK13: omp_if.else:
|
|
// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND8:%.*]]
|
|
// CHECK13: omp.inner.for.cond8:
|
|
// CHECK13-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK13-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK13-NEXT: [[CMP9:%.*]] = icmp ule i64 [[TMP15]], [[TMP16]]
|
|
// CHECK13-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY10:%.*]], label [[OMP_INNER_FOR_END24:%.*]]
|
|
// CHECK13: omp.inner.for.body10:
|
|
// CHECK13-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK13-NEXT: [[MUL11:%.*]] = mul i64 [[TMP17]], 400
|
|
// CHECK13-NEXT: [[SUB12:%.*]] = sub i64 2000, [[MUL11]]
|
|
// CHECK13-NEXT: store i64 [[SUB12]], i64* [[IT]], align 8
|
|
// CHECK13-NEXT: [[TMP18:%.*]] = load i32, i32* [[B]], align 4
|
|
// CHECK13-NEXT: [[CONV13:%.*]] = sitofp i32 [[TMP18]] to double
|
|
// CHECK13-NEXT: [[ADD14:%.*]] = fadd double [[CONV13]], 1.500000e+00
|
|
// CHECK13-NEXT: [[A15:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
|
|
// CHECK13-NEXT: store double [[ADD14]], double* [[A15]], align 8
|
|
// CHECK13-NEXT: [[A16:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
|
|
// CHECK13-NEXT: [[TMP19:%.*]] = load double, double* [[A16]], align 8
|
|
// CHECK13-NEXT: [[INC17:%.*]] = fadd double [[TMP19]], 1.000000e+00
|
|
// CHECK13-NEXT: store double [[INC17]], double* [[A16]], align 8
|
|
// CHECK13-NEXT: [[CONV18:%.*]] = fptosi double [[INC17]] to i16
|
|
// CHECK13-NEXT: [[TMP20:%.*]] = mul nsw i64 1, [[TMP2]]
|
|
// CHECK13-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP20]]
|
|
// CHECK13-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX19]], i64 1
|
|
// CHECK13-NEXT: store i16 [[CONV18]], i16* [[ARRAYIDX20]], align 2
|
|
// CHECK13-NEXT: br label [[OMP_BODY_CONTINUE21:%.*]]
|
|
// CHECK13: omp.body.continue21:
|
|
// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC22:%.*]]
|
|
// CHECK13: omp.inner.for.inc22:
|
|
// CHECK13-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK13-NEXT: [[ADD23:%.*]] = add i64 [[TMP21]], 1
|
|
// CHECK13-NEXT: store i64 [[ADD23]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND8]], !llvm.loop [[LOOP22:![0-9]+]]
|
|
// CHECK13: omp.inner.for.end24:
|
|
// CHECK13-NEXT: br label [[OMP_IF_END]]
|
|
// CHECK13: omp_if.end:
|
|
// CHECK13-NEXT: store i64 400, i64* [[IT]], align 8
|
|
// CHECK13-NEXT: [[TMP22:%.*]] = mul nsw i64 1, [[TMP2]]
|
|
// CHECK13-NEXT: [[ARRAYIDX25:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP22]]
|
|
// CHECK13-NEXT: [[ARRAYIDX26:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX25]], i64 1
|
|
// CHECK13-NEXT: [[TMP23:%.*]] = load i16, i16* [[ARRAYIDX26]], align 2
|
|
// CHECK13-NEXT: [[CONV27:%.*]] = sext i16 [[TMP23]] to i32
|
|
// CHECK13-NEXT: [[TMP24:%.*]] = load i32, i32* [[B]], align 4
|
|
// CHECK13-NEXT: [[ADD28:%.*]] = add nsw i32 [[CONV27]], [[TMP24]]
|
|
// CHECK13-NEXT: [[TMP25:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
|
|
// CHECK13-NEXT: call void @llvm.stackrestore(i8* [[TMP25]])
|
|
// CHECK13-NEXT: ret i32 [[ADD28]]
|
|
//
|
|
//
|
|
// CHECK13-LABEL: define {{[^@]+}}@_ZL7fstatici
|
|
// CHECK13-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
|
|
// CHECK13-NEXT: entry:
|
|
// CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK13-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK13-NEXT: [[AA:%.*]] = alloca i16, align 2
|
|
// CHECK13-NEXT: [[AAA:%.*]] = alloca i8, align 1
|
|
// CHECK13-NEXT: [[B:%.*]] = alloca [10 x i32], align 4
|
|
// CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK13-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK13-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK13-NEXT: store i16 0, i16* [[AA]], align 2
|
|
// CHECK13-NEXT: store i8 0, i8* [[AAA]], align 1
|
|
// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK13-NEXT: store i32 429496720, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK13-NEXT: ret i32 [[TMP0]]
|
|
//
|
|
//
|
|
// CHECK13-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
|
|
// CHECK13-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat {
|
|
// CHECK13-NEXT: entry:
|
|
// CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK13-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK13-NEXT: [[AA:%.*]] = alloca i16, align 2
|
|
// CHECK13-NEXT: [[B:%.*]] = alloca [10 x i32], align 4
|
|
// CHECK13-NEXT: [[TMP:%.*]] = alloca i64, align 8
|
|
// CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
|
|
// CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
|
|
// CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
|
|
// CHECK13-NEXT: [[I:%.*]] = alloca i64, align 8
|
|
// CHECK13-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK13-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK13-NEXT: store i16 0, i16* [[AA]], align 2
|
|
// CHECK13-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK13-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK13-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK13-NEXT: store i64 [[TMP0]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK13: omp.inner.for.cond:
|
|
// CHECK13-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !24
|
|
// CHECK13-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !24
|
|
// CHECK13-NEXT: [[CMP:%.*]] = icmp sle i64 [[TMP1]], [[TMP2]]
|
|
// CHECK13-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK13: omp.inner.for.body:
|
|
// CHECK13-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !24
|
|
// CHECK13-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP3]], 3
|
|
// CHECK13-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
|
|
// CHECK13-NEXT: store i64 [[ADD]], i64* [[I]], align 8, !llvm.access.group !24
|
|
// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !24
|
|
// CHECK13-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1
|
|
// CHECK13-NEXT: store i32 [[ADD1]], i32* [[A]], align 4, !llvm.access.group !24
|
|
// CHECK13-NEXT: [[TMP5:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !24
|
|
// CHECK13-NEXT: [[CONV:%.*]] = sext i16 [[TMP5]] to i32
|
|
// CHECK13-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 1
|
|
// CHECK13-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
|
|
// CHECK13-NEXT: store i16 [[CONV3]], i16* [[AA]], align 2, !llvm.access.group !24
|
|
// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2
|
|
// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !24
|
|
// CHECK13-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP6]], 1
|
|
// CHECK13-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !24
|
|
// CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK13: omp.body.continue:
|
|
// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK13: omp.inner.for.inc:
|
|
// CHECK13-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !24
|
|
// CHECK13-NEXT: [[ADD5:%.*]] = add nsw i64 [[TMP7]], 1
|
|
// CHECK13-NEXT: store i64 [[ADD5]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !24
|
|
// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]]
|
|
// CHECK13: omp.inner.for.end:
|
|
// CHECK13-NEXT: store i64 11, i64* [[I]], align 8
|
|
// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK13-NEXT: ret i32 [[TMP8]]
|
|
//
|
|
//
|
|
// CHECK14-LABEL: define {{[^@]+}}@_Z7get_valv
|
|
// CHECK14-SAME: () #[[ATTR0:[0-9]+]] {
|
|
// CHECK14-NEXT: entry:
|
|
// CHECK14-NEXT: ret i64 0
|
|
//
|
|
//
|
|
// CHECK14-LABEL: define {{[^@]+}}@_Z3fooi
|
|
// CHECK14-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
|
|
// CHECK14-NEXT: entry:
|
|
// CHECK14-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK14-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK14-NEXT: [[AA:%.*]] = alloca i16, align 2
|
|
// CHECK14-NEXT: [[B:%.*]] = alloca [10 x float], align 4
|
|
// CHECK14-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8
|
|
// CHECK14-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8
|
|
// CHECK14-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8
|
|
// CHECK14-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8
|
|
// CHECK14-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8
|
|
// CHECK14-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK14-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK14-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK14-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4
|
|
// CHECK14-NEXT: [[K:%.*]] = alloca i64, align 8
|
|
// CHECK14-NEXT: [[_TMP3:%.*]] = alloca i32, align 4
|
|
// CHECK14-NEXT: [[DOTOMP_LB4:%.*]] = alloca i32, align 4
|
|
// CHECK14-NEXT: [[DOTOMP_UB5:%.*]] = alloca i32, align 4
|
|
// CHECK14-NEXT: [[DOTOMP_IV6:%.*]] = alloca i32, align 4
|
|
// CHECK14-NEXT: [[DOTLINEAR_START:%.*]] = alloca i64, align 8
|
|
// CHECK14-NEXT: [[I7:%.*]] = alloca i32, align 4
|
|
// CHECK14-NEXT: [[K8:%.*]] = alloca i64, align 8
|
|
// CHECK14-NEXT: [[LIN:%.*]] = alloca i32, align 4
|
|
// CHECK14-NEXT: [[_TMP21:%.*]] = alloca i64, align 8
|
|
// CHECK14-NEXT: [[DOTOMP_LB22:%.*]] = alloca i64, align 8
|
|
// CHECK14-NEXT: [[DOTOMP_UB23:%.*]] = alloca i64, align 8
|
|
// CHECK14-NEXT: [[DOTOMP_IV24:%.*]] = alloca i64, align 8
|
|
// CHECK14-NEXT: [[DOTLINEAR_START25:%.*]] = alloca i32, align 4
|
|
// CHECK14-NEXT: [[DOTLINEAR_START26:%.*]] = alloca i32, align 4
|
|
// CHECK14-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8
|
|
// CHECK14-NEXT: [[IT:%.*]] = alloca i64, align 8
|
|
// CHECK14-NEXT: [[LIN28:%.*]] = alloca i32, align 4
|
|
// CHECK14-NEXT: [[A29:%.*]] = alloca i32, align 4
|
|
// CHECK14-NEXT: [[_TMP58:%.*]] = alloca i16, align 2
|
|
// CHECK14-NEXT: [[DOTOMP_LB59:%.*]] = alloca i32, align 4
|
|
// CHECK14-NEXT: [[DOTOMP_UB60:%.*]] = alloca i32, align 4
|
|
// CHECK14-NEXT: [[DOTOMP_IV61:%.*]] = alloca i32, align 4
|
|
// CHECK14-NEXT: [[IT62:%.*]] = alloca i16, align 2
|
|
// CHECK14-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
|
// CHECK14-NEXT: [[_TMP77:%.*]] = alloca i8, align 1
|
|
// CHECK14-NEXT: [[DOTOMP_LB78:%.*]] = alloca i32, align 4
|
|
// CHECK14-NEXT: [[DOTOMP_UB79:%.*]] = alloca i32, align 4
|
|
// CHECK14-NEXT: [[DOTOMP_IV80:%.*]] = alloca i32, align 4
|
|
// CHECK14-NEXT: [[IT81:%.*]] = alloca i8, align 1
|
|
// CHECK14-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK14-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK14-NEXT: store i16 0, i16* [[AA]], align 2
|
|
// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK14-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
|
|
// CHECK14-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave()
|
|
// CHECK14-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8
|
|
// CHECK14-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4
|
|
// CHECK14-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8
|
|
// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK14-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64
|
|
// CHECK14-NEXT: [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]]
|
|
// CHECK14-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8
|
|
// CHECK14-NEXT: store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8
|
|
// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK14-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK14-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK14: omp.inner.for.cond:
|
|
// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
|
|
// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !2
|
|
// CHECK14-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
|
|
// CHECK14-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK14: omp.inner.for.body:
|
|
// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
|
|
// CHECK14-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 5
|
|
// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]]
|
|
// CHECK14-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !2
|
|
// CHECK14-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK14: omp.body.continue:
|
|
// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK14: omp.inner.for.inc:
|
|
// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
|
|
// CHECK14-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1
|
|
// CHECK14-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
|
|
// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]
|
|
// CHECK14: omp.inner.for.end:
|
|
// CHECK14-NEXT: store i32 33, i32* [[I]], align 4
|
|
// CHECK14-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv()
|
|
// CHECK14-NEXT: store i64 [[CALL]], i64* [[K]], align 8
|
|
// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_LB4]], align 4
|
|
// CHECK14-NEXT: store i32 8, i32* [[DOTOMP_UB5]], align 4
|
|
// CHECK14-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_LB4]], align 4
|
|
// CHECK14-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV6]], align 4
|
|
// CHECK14-NEXT: [[TMP12:%.*]] = load i64, i64* [[K]], align 8
|
|
// CHECK14-NEXT: store i64 [[TMP12]], i64* [[DOTLINEAR_START]], align 8
|
|
// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND9:%.*]]
|
|
// CHECK14: omp.inner.for.cond9:
|
|
// CHECK14-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !6
|
|
// CHECK14-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB5]], align 4, !llvm.access.group !6
|
|
// CHECK14-NEXT: [[CMP10:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
|
|
// CHECK14-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY11:%.*]], label [[OMP_INNER_FOR_END19:%.*]]
|
|
// CHECK14: omp.inner.for.body11:
|
|
// CHECK14-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !6
|
|
// CHECK14-NEXT: [[MUL12:%.*]] = mul nsw i32 [[TMP15]], 1
|
|
// CHECK14-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL12]]
|
|
// CHECK14-NEXT: store i32 [[SUB]], i32* [[I7]], align 4, !llvm.access.group !6
|
|
// CHECK14-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8, !llvm.access.group !6
|
|
// CHECK14-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !6
|
|
// CHECK14-NEXT: [[MUL13:%.*]] = mul nsw i32 [[TMP17]], 3
|
|
// CHECK14-NEXT: [[CONV:%.*]] = sext i32 [[MUL13]] to i64
|
|
// CHECK14-NEXT: [[ADD14:%.*]] = add nsw i64 [[TMP16]], [[CONV]]
|
|
// CHECK14-NEXT: store i64 [[ADD14]], i64* [[K8]], align 8, !llvm.access.group !6
|
|
// CHECK14-NEXT: [[TMP18:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !6
|
|
// CHECK14-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP18]], 1
|
|
// CHECK14-NEXT: store i32 [[ADD15]], i32* [[A]], align 4, !llvm.access.group !6
|
|
// CHECK14-NEXT: br label [[OMP_BODY_CONTINUE16:%.*]]
|
|
// CHECK14: omp.body.continue16:
|
|
// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC17:%.*]]
|
|
// CHECK14: omp.inner.for.inc17:
|
|
// CHECK14-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !6
|
|
// CHECK14-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP19]], 1
|
|
// CHECK14-NEXT: store i32 [[ADD18]], i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !6
|
|
// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND9]], !llvm.loop [[LOOP7:![0-9]+]]
|
|
// CHECK14: omp.inner.for.end19:
|
|
// CHECK14-NEXT: store i32 1, i32* [[I7]], align 4
|
|
// CHECK14-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8
|
|
// CHECK14-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP20]], 27
|
|
// CHECK14-NEXT: store i64 [[ADD20]], i64* [[K]], align 8
|
|
// CHECK14-NEXT: store i32 12, i32* [[LIN]], align 4
|
|
// CHECK14-NEXT: store i64 0, i64* [[DOTOMP_LB22]], align 8
|
|
// CHECK14-NEXT: store i64 3, i64* [[DOTOMP_UB23]], align 8
|
|
// CHECK14-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_LB22]], align 8
|
|
// CHECK14-NEXT: store i64 [[TMP21]], i64* [[DOTOMP_IV24]], align 8
|
|
// CHECK14-NEXT: [[TMP22:%.*]] = load i32, i32* [[LIN]], align 4
|
|
// CHECK14-NEXT: store i32 [[TMP22]], i32* [[DOTLINEAR_START25]], align 4
|
|
// CHECK14-NEXT: [[TMP23:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK14-NEXT: store i32 [[TMP23]], i32* [[DOTLINEAR_START26]], align 4
|
|
// CHECK14-NEXT: [[CALL27:%.*]] = call i64 @_Z7get_valv()
|
|
// CHECK14-NEXT: store i64 [[CALL27]], i64* [[DOTLINEAR_STEP]], align 8
|
|
// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND30:%.*]]
|
|
// CHECK14: omp.inner.for.cond30:
|
|
// CHECK14-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !9
|
|
// CHECK14-NEXT: [[TMP25:%.*]] = load i64, i64* [[DOTOMP_UB23]], align 8, !llvm.access.group !9
|
|
// CHECK14-NEXT: [[CMP31:%.*]] = icmp ule i64 [[TMP24]], [[TMP25]]
|
|
// CHECK14-NEXT: br i1 [[CMP31]], label [[OMP_INNER_FOR_BODY32:%.*]], label [[OMP_INNER_FOR_END49:%.*]]
|
|
// CHECK14: omp.inner.for.body32:
|
|
// CHECK14-NEXT: [[TMP26:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !9
|
|
// CHECK14-NEXT: [[MUL33:%.*]] = mul i64 [[TMP26]], 400
|
|
// CHECK14-NEXT: [[SUB34:%.*]] = sub i64 2000, [[MUL33]]
|
|
// CHECK14-NEXT: store i64 [[SUB34]], i64* [[IT]], align 8, !llvm.access.group !9
|
|
// CHECK14-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTLINEAR_START25]], align 4, !llvm.access.group !9
|
|
// CHECK14-NEXT: [[CONV35:%.*]] = sext i32 [[TMP27]] to i64
|
|
// CHECK14-NEXT: [[TMP28:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !9
|
|
// CHECK14-NEXT: [[TMP29:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !9
|
|
// CHECK14-NEXT: [[MUL36:%.*]] = mul i64 [[TMP28]], [[TMP29]]
|
|
// CHECK14-NEXT: [[ADD37:%.*]] = add i64 [[CONV35]], [[MUL36]]
|
|
// CHECK14-NEXT: [[CONV38:%.*]] = trunc i64 [[ADD37]] to i32
|
|
// CHECK14-NEXT: store i32 [[CONV38]], i32* [[LIN28]], align 4, !llvm.access.group !9
|
|
// CHECK14-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTLINEAR_START26]], align 4, !llvm.access.group !9
|
|
// CHECK14-NEXT: [[CONV39:%.*]] = sext i32 [[TMP30]] to i64
|
|
// CHECK14-NEXT: [[TMP31:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !9
|
|
// CHECK14-NEXT: [[TMP32:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !9
|
|
// CHECK14-NEXT: [[MUL40:%.*]] = mul i64 [[TMP31]], [[TMP32]]
|
|
// CHECK14-NEXT: [[ADD41:%.*]] = add i64 [[CONV39]], [[MUL40]]
|
|
// CHECK14-NEXT: [[CONV42:%.*]] = trunc i64 [[ADD41]] to i32
|
|
// CHECK14-NEXT: store i32 [[CONV42]], i32* [[A29]], align 4, !llvm.access.group !9
|
|
// CHECK14-NEXT: [[TMP33:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !9
|
|
// CHECK14-NEXT: [[CONV43:%.*]] = sext i16 [[TMP33]] to i32
|
|
// CHECK14-NEXT: [[ADD44:%.*]] = add nsw i32 [[CONV43]], 1
|
|
// CHECK14-NEXT: [[CONV45:%.*]] = trunc i32 [[ADD44]] to i16
|
|
// CHECK14-NEXT: store i16 [[CONV45]], i16* [[AA]], align 2, !llvm.access.group !9
|
|
// CHECK14-NEXT: br label [[OMP_BODY_CONTINUE46:%.*]]
|
|
// CHECK14: omp.body.continue46:
|
|
// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC47:%.*]]
|
|
// CHECK14: omp.inner.for.inc47:
|
|
// CHECK14-NEXT: [[TMP34:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !9
|
|
// CHECK14-NEXT: [[ADD48:%.*]] = add i64 [[TMP34]], 1
|
|
// CHECK14-NEXT: store i64 [[ADD48]], i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !9
|
|
// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND30]], !llvm.loop [[LOOP10:![0-9]+]]
|
|
// CHECK14: omp.inner.for.end49:
|
|
// CHECK14-NEXT: store i64 400, i64* [[IT]], align 8
|
|
// CHECK14-NEXT: [[TMP35:%.*]] = load i32, i32* [[DOTLINEAR_START25]], align 4
|
|
// CHECK14-NEXT: [[CONV50:%.*]] = sext i32 [[TMP35]] to i64
|
|
// CHECK14-NEXT: [[TMP36:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
|
|
// CHECK14-NEXT: [[MUL51:%.*]] = mul i64 4, [[TMP36]]
|
|
// CHECK14-NEXT: [[ADD52:%.*]] = add i64 [[CONV50]], [[MUL51]]
|
|
// CHECK14-NEXT: [[CONV53:%.*]] = trunc i64 [[ADD52]] to i32
|
|
// CHECK14-NEXT: store i32 [[CONV53]], i32* [[LIN]], align 4
|
|
// CHECK14-NEXT: [[TMP37:%.*]] = load i32, i32* [[DOTLINEAR_START26]], align 4
|
|
// CHECK14-NEXT: [[CONV54:%.*]] = sext i32 [[TMP37]] to i64
|
|
// CHECK14-NEXT: [[TMP38:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
|
|
// CHECK14-NEXT: [[MUL55:%.*]] = mul i64 4, [[TMP38]]
|
|
// CHECK14-NEXT: [[ADD56:%.*]] = add i64 [[CONV54]], [[MUL55]]
|
|
// CHECK14-NEXT: [[CONV57:%.*]] = trunc i64 [[ADD56]] to i32
|
|
// CHECK14-NEXT: store i32 [[CONV57]], i32* [[A]], align 4
|
|
// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_LB59]], align 4
|
|
// CHECK14-NEXT: store i32 3, i32* [[DOTOMP_UB60]], align 4
|
|
// CHECK14-NEXT: [[TMP39:%.*]] = load i32, i32* [[DOTOMP_LB59]], align 4
|
|
// CHECK14-NEXT: store i32 [[TMP39]], i32* [[DOTOMP_IV61]], align 4
|
|
// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND63:%.*]]
|
|
// CHECK14: omp.inner.for.cond63:
|
|
// CHECK14-NEXT: [[TMP40:%.*]] = load i32, i32* [[DOTOMP_IV61]], align 4, !llvm.access.group !12
|
|
// CHECK14-NEXT: [[TMP41:%.*]] = load i32, i32* [[DOTOMP_UB60]], align 4, !llvm.access.group !12
|
|
// CHECK14-NEXT: [[CMP64:%.*]] = icmp sle i32 [[TMP40]], [[TMP41]]
|
|
// CHECK14-NEXT: br i1 [[CMP64]], label [[OMP_INNER_FOR_BODY65:%.*]], label [[OMP_INNER_FOR_END76:%.*]]
|
|
// CHECK14: omp.inner.for.body65:
|
|
// CHECK14-NEXT: [[TMP42:%.*]] = load i32, i32* [[DOTOMP_IV61]], align 4, !llvm.access.group !12
|
|
// CHECK14-NEXT: [[MUL66:%.*]] = mul nsw i32 [[TMP42]], 4
|
|
// CHECK14-NEXT: [[ADD67:%.*]] = add nsw i32 6, [[MUL66]]
|
|
// CHECK14-NEXT: [[CONV68:%.*]] = trunc i32 [[ADD67]] to i16
|
|
// CHECK14-NEXT: store i16 [[CONV68]], i16* [[IT62]], align 2, !llvm.access.group !12
|
|
// CHECK14-NEXT: [[TMP43:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !12
|
|
// CHECK14-NEXT: [[ADD69:%.*]] = add nsw i32 [[TMP43]], 1
|
|
// CHECK14-NEXT: store i32 [[ADD69]], i32* [[A]], align 4, !llvm.access.group !12
|
|
// CHECK14-NEXT: [[TMP44:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !12
|
|
// CHECK14-NEXT: [[CONV70:%.*]] = sext i16 [[TMP44]] to i32
|
|
// CHECK14-NEXT: [[ADD71:%.*]] = add nsw i32 [[CONV70]], 1
|
|
// CHECK14-NEXT: [[CONV72:%.*]] = trunc i32 [[ADD71]] to i16
|
|
// CHECK14-NEXT: store i16 [[CONV72]], i16* [[AA]], align 2, !llvm.access.group !12
|
|
// CHECK14-NEXT: br label [[OMP_BODY_CONTINUE73:%.*]]
|
|
// CHECK14: omp.body.continue73:
|
|
// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC74:%.*]]
|
|
// CHECK14: omp.inner.for.inc74:
|
|
// CHECK14-NEXT: [[TMP45:%.*]] = load i32, i32* [[DOTOMP_IV61]], align 4, !llvm.access.group !12
|
|
// CHECK14-NEXT: [[ADD75:%.*]] = add nsw i32 [[TMP45]], 1
|
|
// CHECK14-NEXT: store i32 [[ADD75]], i32* [[DOTOMP_IV61]], align 4, !llvm.access.group !12
|
|
// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND63]], !llvm.loop [[LOOP13:![0-9]+]]
|
|
// CHECK14: omp.inner.for.end76:
|
|
// CHECK14-NEXT: store i16 22, i16* [[IT62]], align 2
|
|
// CHECK14-NEXT: [[TMP46:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK14-NEXT: store i32 [[TMP46]], i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_LB78]], align 4
|
|
// CHECK14-NEXT: store i32 25, i32* [[DOTOMP_UB79]], align 4
|
|
// CHECK14-NEXT: [[TMP47:%.*]] = load i32, i32* [[DOTOMP_LB78]], align 4
|
|
// CHECK14-NEXT: store i32 [[TMP47]], i32* [[DOTOMP_IV80]], align 4
|
|
// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND82:%.*]]
|
|
// CHECK14: omp.inner.for.cond82:
|
|
// CHECK14-NEXT: [[TMP48:%.*]] = load i32, i32* [[DOTOMP_IV80]], align 4, !llvm.access.group !15
|
|
// CHECK14-NEXT: [[TMP49:%.*]] = load i32, i32* [[DOTOMP_UB79]], align 4, !llvm.access.group !15
|
|
// CHECK14-NEXT: [[CMP83:%.*]] = icmp sle i32 [[TMP48]], [[TMP49]]
|
|
// CHECK14-NEXT: br i1 [[CMP83]], label [[OMP_INNER_FOR_BODY84:%.*]], label [[OMP_INNER_FOR_END109:%.*]]
|
|
// CHECK14: omp.inner.for.body84:
|
|
// CHECK14-NEXT: [[TMP50:%.*]] = load i32, i32* [[DOTOMP_IV80]], align 4, !llvm.access.group !15
|
|
// CHECK14-NEXT: [[MUL85:%.*]] = mul nsw i32 [[TMP50]], 1
|
|
// CHECK14-NEXT: [[SUB86:%.*]] = sub nsw i32 122, [[MUL85]]
|
|
// CHECK14-NEXT: [[CONV87:%.*]] = trunc i32 [[SUB86]] to i8
|
|
// CHECK14-NEXT: store i8 [[CONV87]], i8* [[IT81]], align 1, !llvm.access.group !15
|
|
// CHECK14-NEXT: [[TMP51:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !15
|
|
// CHECK14-NEXT: [[ADD88:%.*]] = add nsw i32 [[TMP51]], 1
|
|
// CHECK14-NEXT: store i32 [[ADD88]], i32* [[A]], align 4, !llvm.access.group !15
|
|
// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 2
|
|
// CHECK14-NEXT: [[TMP52:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !15
|
|
// CHECK14-NEXT: [[CONV89:%.*]] = fpext float [[TMP52]] to double
|
|
// CHECK14-NEXT: [[ADD90:%.*]] = fadd double [[CONV89]], 1.000000e+00
|
|
// CHECK14-NEXT: [[CONV91:%.*]] = fptrunc double [[ADD90]] to float
|
|
// CHECK14-NEXT: store float [[CONV91]], float* [[ARRAYIDX]], align 4, !llvm.access.group !15
|
|
// CHECK14-NEXT: [[ARRAYIDX92:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 3
|
|
// CHECK14-NEXT: [[TMP53:%.*]] = load float, float* [[ARRAYIDX92]], align 4, !llvm.access.group !15
|
|
// CHECK14-NEXT: [[CONV93:%.*]] = fpext float [[TMP53]] to double
|
|
// CHECK14-NEXT: [[ADD94:%.*]] = fadd double [[CONV93]], 1.000000e+00
|
|
// CHECK14-NEXT: [[CONV95:%.*]] = fptrunc double [[ADD94]] to float
|
|
// CHECK14-NEXT: store float [[CONV95]], float* [[ARRAYIDX92]], align 4, !llvm.access.group !15
|
|
// CHECK14-NEXT: [[ARRAYIDX96:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i64 0, i64 1
|
|
// CHECK14-NEXT: [[ARRAYIDX97:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX96]], i64 0, i64 2
|
|
// CHECK14-NEXT: [[TMP54:%.*]] = load double, double* [[ARRAYIDX97]], align 8, !llvm.access.group !15
|
|
// CHECK14-NEXT: [[ADD98:%.*]] = fadd double [[TMP54]], 1.000000e+00
|
|
// CHECK14-NEXT: store double [[ADD98]], double* [[ARRAYIDX97]], align 8, !llvm.access.group !15
|
|
// CHECK14-NEXT: [[TMP55:%.*]] = mul nsw i64 1, [[TMP4]]
|
|
// CHECK14-NEXT: [[ARRAYIDX99:%.*]] = getelementptr inbounds double, double* [[VLA1]], i64 [[TMP55]]
|
|
// CHECK14-NEXT: [[ARRAYIDX100:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX99]], i64 3
|
|
// CHECK14-NEXT: [[TMP56:%.*]] = load double, double* [[ARRAYIDX100]], align 8, !llvm.access.group !15
|
|
// CHECK14-NEXT: [[ADD101:%.*]] = fadd double [[TMP56]], 1.000000e+00
|
|
// CHECK14-NEXT: store double [[ADD101]], double* [[ARRAYIDX100]], align 8, !llvm.access.group !15
|
|
// CHECK14-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0
|
|
// CHECK14-NEXT: [[TMP57:%.*]] = load i64, i64* [[X]], align 8, !llvm.access.group !15
|
|
// CHECK14-NEXT: [[ADD102:%.*]] = add nsw i64 [[TMP57]], 1
|
|
// CHECK14-NEXT: store i64 [[ADD102]], i64* [[X]], align 8, !llvm.access.group !15
|
|
// CHECK14-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1
|
|
// CHECK14-NEXT: [[TMP58:%.*]] = load i8, i8* [[Y]], align 8, !llvm.access.group !15
|
|
// CHECK14-NEXT: [[CONV103:%.*]] = sext i8 [[TMP58]] to i32
|
|
// CHECK14-NEXT: [[ADD104:%.*]] = add nsw i32 [[CONV103]], 1
|
|
// CHECK14-NEXT: [[CONV105:%.*]] = trunc i32 [[ADD104]] to i8
|
|
// CHECK14-NEXT: store i8 [[CONV105]], i8* [[Y]], align 8, !llvm.access.group !15
|
|
// CHECK14-NEXT: br label [[OMP_BODY_CONTINUE106:%.*]]
|
|
// CHECK14: omp.body.continue106:
|
|
// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC107:%.*]]
|
|
// CHECK14: omp.inner.for.inc107:
|
|
// CHECK14-NEXT: [[TMP59:%.*]] = load i32, i32* [[DOTOMP_IV80]], align 4, !llvm.access.group !15
|
|
// CHECK14-NEXT: [[ADD108:%.*]] = add nsw i32 [[TMP59]], 1
|
|
// CHECK14-NEXT: store i32 [[ADD108]], i32* [[DOTOMP_IV80]], align 4, !llvm.access.group !15
|
|
// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND82]], !llvm.loop [[LOOP16:![0-9]+]]
|
|
// CHECK14: omp.inner.for.end109:
|
|
// CHECK14-NEXT: store i8 96, i8* [[IT81]], align 1
|
|
// CHECK14-NEXT: [[TMP60:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK14-NEXT: [[TMP61:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
|
|
// CHECK14-NEXT: call void @llvm.stackrestore(i8* [[TMP61]])
|
|
// CHECK14-NEXT: ret i32 [[TMP60]]
|
|
//
|
|
//
|
|
// CHECK14-LABEL: define {{[^@]+}}@_Z3bari
|
|
// CHECK14-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
|
|
// CHECK14-NEXT: entry:
|
|
// CHECK14-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK14-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK14-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8
|
|
// CHECK14-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK14-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK14-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]])
|
|
// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
|
|
// CHECK14-NEXT: store i32 [[ADD]], i32* [[A]], align 4
|
|
// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK14-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]])
|
|
// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK14-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
|
|
// CHECK14-NEXT: store i32 [[ADD2]], i32* [[A]], align 4
|
|
// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK14-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]])
|
|
// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK14-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
|
|
// CHECK14-NEXT: store i32 [[ADD4]], i32* [[A]], align 4
|
|
// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK14-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]])
|
|
// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK14-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
|
|
// CHECK14-NEXT: store i32 [[ADD6]], i32* [[A]], align 4
|
|
// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK14-NEXT: ret i32 [[TMP8]]
|
|
//
|
|
//
|
|
// CHECK14-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
|
|
// CHECK14-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 {
|
|
// CHECK14-NEXT: entry:
|
|
// CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
|
|
// CHECK14-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK14-NEXT: [[B:%.*]] = alloca i32, align 4
|
|
// CHECK14-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8
|
|
// CHECK14-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8
|
|
// CHECK14-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
|
|
// CHECK14-NEXT: [[TMP:%.*]] = alloca i64, align 8
|
|
// CHECK14-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
|
|
// CHECK14-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
|
|
// CHECK14-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
|
|
// CHECK14-NEXT: [[IT:%.*]] = alloca i64, align 8
|
|
// CHECK14-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK14-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
|
|
// CHECK14-NEXT: store i32 [[ADD]], i32* [[B]], align 4
|
|
// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK14-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
|
|
// CHECK14-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave()
|
|
// CHECK14-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8
|
|
// CHECK14-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]]
|
|
// CHECK14-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2
|
|
// CHECK14-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8
|
|
// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK14-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 60
|
|
// CHECK14-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8
|
|
// CHECK14-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
|
|
// CHECK14-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK14-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK14-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK14-NEXT: store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK14-NEXT: [[TMP7:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
|
|
// CHECK14-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP7]] to i1
|
|
// CHECK14-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
|
|
// CHECK14: omp_if.then:
|
|
// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK14: omp.inner.for.cond:
|
|
// CHECK14-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18
|
|
// CHECK14-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !18
|
|
// CHECK14-NEXT: [[CMP2:%.*]] = icmp ule i64 [[TMP8]], [[TMP9]]
|
|
// CHECK14-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK14: omp.inner.for.body:
|
|
// CHECK14-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18
|
|
// CHECK14-NEXT: [[MUL:%.*]] = mul i64 [[TMP10]], 400
|
|
// CHECK14-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]
|
|
// CHECK14-NEXT: store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !18
|
|
// CHECK14-NEXT: [[TMP11:%.*]] = load i32, i32* [[B]], align 4, !llvm.access.group !18
|
|
// CHECK14-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP11]] to double
|
|
// CHECK14-NEXT: [[ADD3:%.*]] = fadd double [[CONV]], 1.500000e+00
|
|
// CHECK14-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
|
|
// CHECK14-NEXT: store double [[ADD3]], double* [[A]], align 8, !nontemporal !19, !llvm.access.group !18
|
|
// CHECK14-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
|
|
// CHECK14-NEXT: [[TMP12:%.*]] = load double, double* [[A4]], align 8, !nontemporal !19, !llvm.access.group !18
|
|
// CHECK14-NEXT: [[INC:%.*]] = fadd double [[TMP12]], 1.000000e+00
|
|
// CHECK14-NEXT: store double [[INC]], double* [[A4]], align 8, !nontemporal !19, !llvm.access.group !18
|
|
// CHECK14-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16
|
|
// CHECK14-NEXT: [[TMP13:%.*]] = mul nsw i64 1, [[TMP2]]
|
|
// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP13]]
|
|
// CHECK14-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
|
|
// CHECK14-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2, !llvm.access.group !18
|
|
// CHECK14-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK14: omp.body.continue:
|
|
// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK14: omp.inner.for.inc:
|
|
// CHECK14-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18
|
|
// CHECK14-NEXT: [[ADD7:%.*]] = add i64 [[TMP14]], 1
|
|
// CHECK14-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18
|
|
// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]]
|
|
// CHECK14: omp.inner.for.end:
|
|
// CHECK14-NEXT: br label [[OMP_IF_END:%.*]]
|
|
// CHECK14: omp_if.else:
|
|
// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND8:%.*]]
|
|
// CHECK14: omp.inner.for.cond8:
|
|
// CHECK14-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK14-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK14-NEXT: [[CMP9:%.*]] = icmp ule i64 [[TMP15]], [[TMP16]]
|
|
// CHECK14-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY10:%.*]], label [[OMP_INNER_FOR_END24:%.*]]
|
|
// CHECK14: omp.inner.for.body10:
|
|
// CHECK14-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK14-NEXT: [[MUL11:%.*]] = mul i64 [[TMP17]], 400
|
|
// CHECK14-NEXT: [[SUB12:%.*]] = sub i64 2000, [[MUL11]]
|
|
// CHECK14-NEXT: store i64 [[SUB12]], i64* [[IT]], align 8
|
|
// CHECK14-NEXT: [[TMP18:%.*]] = load i32, i32* [[B]], align 4
|
|
// CHECK14-NEXT: [[CONV13:%.*]] = sitofp i32 [[TMP18]] to double
|
|
// CHECK14-NEXT: [[ADD14:%.*]] = fadd double [[CONV13]], 1.500000e+00
|
|
// CHECK14-NEXT: [[A15:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
|
|
// CHECK14-NEXT: store double [[ADD14]], double* [[A15]], align 8
|
|
// CHECK14-NEXT: [[A16:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
|
|
// CHECK14-NEXT: [[TMP19:%.*]] = load double, double* [[A16]], align 8
|
|
// CHECK14-NEXT: [[INC17:%.*]] = fadd double [[TMP19]], 1.000000e+00
|
|
// CHECK14-NEXT: store double [[INC17]], double* [[A16]], align 8
|
|
// CHECK14-NEXT: [[CONV18:%.*]] = fptosi double [[INC17]] to i16
|
|
// CHECK14-NEXT: [[TMP20:%.*]] = mul nsw i64 1, [[TMP2]]
|
|
// CHECK14-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP20]]
|
|
// CHECK14-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX19]], i64 1
|
|
// CHECK14-NEXT: store i16 [[CONV18]], i16* [[ARRAYIDX20]], align 2
|
|
// CHECK14-NEXT: br label [[OMP_BODY_CONTINUE21:%.*]]
|
|
// CHECK14: omp.body.continue21:
|
|
// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC22:%.*]]
|
|
// CHECK14: omp.inner.for.inc22:
|
|
// CHECK14-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK14-NEXT: [[ADD23:%.*]] = add i64 [[TMP21]], 1
|
|
// CHECK14-NEXT: store i64 [[ADD23]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND8]], !llvm.loop [[LOOP22:![0-9]+]]
|
|
// CHECK14: omp.inner.for.end24:
|
|
// CHECK14-NEXT: br label [[OMP_IF_END]]
|
|
// CHECK14: omp_if.end:
|
|
// CHECK14-NEXT: store i64 400, i64* [[IT]], align 8
|
|
// CHECK14-NEXT: [[TMP22:%.*]] = mul nsw i64 1, [[TMP2]]
|
|
// CHECK14-NEXT: [[ARRAYIDX25:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP22]]
|
|
// CHECK14-NEXT: [[ARRAYIDX26:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX25]], i64 1
|
|
// CHECK14-NEXT: [[TMP23:%.*]] = load i16, i16* [[ARRAYIDX26]], align 2
|
|
// CHECK14-NEXT: [[CONV27:%.*]] = sext i16 [[TMP23]] to i32
|
|
// CHECK14-NEXT: [[TMP24:%.*]] = load i32, i32* [[B]], align 4
|
|
// CHECK14-NEXT: [[ADD28:%.*]] = add nsw i32 [[CONV27]], [[TMP24]]
|
|
// CHECK14-NEXT: [[TMP25:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
|
|
// CHECK14-NEXT: call void @llvm.stackrestore(i8* [[TMP25]])
|
|
// CHECK14-NEXT: ret i32 [[ADD28]]
|
|
//
|
|
//
|
|
// CHECK14-LABEL: define {{[^@]+}}@_ZL7fstatici
|
|
// CHECK14-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
|
|
// CHECK14-NEXT: entry:
|
|
// CHECK14-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK14-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK14-NEXT: [[AA:%.*]] = alloca i16, align 2
|
|
// CHECK14-NEXT: [[AAA:%.*]] = alloca i8, align 1
|
|
// CHECK14-NEXT: [[B:%.*]] = alloca [10 x i32], align 4
|
|
// CHECK14-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK14-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK14-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK14-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK14-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK14-NEXT: store i16 0, i16* [[AA]], align 2
|
|
// CHECK14-NEXT: store i8 0, i8* [[AAA]], align 1
|
|
// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK14-NEXT: store i32 429496720, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK14-NEXT: ret i32 [[TMP0]]
|
|
//
|
|
//
|
|
// CHECK14-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
|
|
// CHECK14-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat {
|
|
// CHECK14-NEXT: entry:
|
|
// CHECK14-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK14-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK14-NEXT: [[AA:%.*]] = alloca i16, align 2
|
|
// CHECK14-NEXT: [[B:%.*]] = alloca [10 x i32], align 4
|
|
// CHECK14-NEXT: [[TMP:%.*]] = alloca i64, align 8
|
|
// CHECK14-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
|
|
// CHECK14-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
|
|
// CHECK14-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
|
|
// CHECK14-NEXT: [[I:%.*]] = alloca i64, align 8
|
|
// CHECK14-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK14-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK14-NEXT: store i16 0, i16* [[AA]], align 2
|
|
// CHECK14-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK14-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK14-NEXT: store i64 [[TMP0]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK14: omp.inner.for.cond:
|
|
// CHECK14-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !24
|
|
// CHECK14-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !24
|
|
// CHECK14-NEXT: [[CMP:%.*]] = icmp sle i64 [[TMP1]], [[TMP2]]
|
|
// CHECK14-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK14: omp.inner.for.body:
|
|
// CHECK14-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !24
|
|
// CHECK14-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP3]], 3
|
|
// CHECK14-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
|
|
// CHECK14-NEXT: store i64 [[ADD]], i64* [[I]], align 8, !llvm.access.group !24
|
|
// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !24
|
|
// CHECK14-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1
|
|
// CHECK14-NEXT: store i32 [[ADD1]], i32* [[A]], align 4, !llvm.access.group !24
|
|
// CHECK14-NEXT: [[TMP5:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !24
|
|
// CHECK14-NEXT: [[CONV:%.*]] = sext i16 [[TMP5]] to i32
|
|
// CHECK14-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 1
|
|
// CHECK14-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
|
|
// CHECK14-NEXT: store i16 [[CONV3]], i16* [[AA]], align 2, !llvm.access.group !24
|
|
// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2
|
|
// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !24
|
|
// CHECK14-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP6]], 1
|
|
// CHECK14-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !24
|
|
// CHECK14-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK14: omp.body.continue:
|
|
// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK14: omp.inner.for.inc:
|
|
// CHECK14-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !24
|
|
// CHECK14-NEXT: [[ADD5:%.*]] = add nsw i64 [[TMP7]], 1
|
|
// CHECK14-NEXT: store i64 [[ADD5]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !24
|
|
// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]]
|
|
// CHECK14: omp.inner.for.end:
|
|
// CHECK14-NEXT: store i64 11, i64* [[I]], align 8
|
|
// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK14-NEXT: ret i32 [[TMP8]]
|
|
//
|
|
//
|
|
// CHECK15-LABEL: define {{[^@]+}}@_Z7get_valv
|
|
// CHECK15-SAME: () #[[ATTR0:[0-9]+]] {
|
|
// CHECK15-NEXT: entry:
|
|
// CHECK15-NEXT: ret i64 0
|
|
//
|
|
//
|
|
// CHECK15-LABEL: define {{[^@]+}}@_Z3fooi
|
|
// CHECK15-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
|
|
// CHECK15-NEXT: entry:
|
|
// CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK15-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK15-NEXT: [[AA:%.*]] = alloca i16, align 2
|
|
// CHECK15-NEXT: [[B:%.*]] = alloca [10 x float], align 4
|
|
// CHECK15-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4
|
|
// CHECK15-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4
|
|
// CHECK15-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8
|
|
// CHECK15-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4
|
|
// CHECK15-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4
|
|
// CHECK15-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK15-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK15-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK15-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4
|
|
// CHECK15-NEXT: [[K:%.*]] = alloca i64, align 8
|
|
// CHECK15-NEXT: [[_TMP3:%.*]] = alloca i32, align 4
|
|
// CHECK15-NEXT: [[DOTOMP_LB4:%.*]] = alloca i32, align 4
|
|
// CHECK15-NEXT: [[DOTOMP_UB5:%.*]] = alloca i32, align 4
|
|
// CHECK15-NEXT: [[DOTOMP_IV6:%.*]] = alloca i32, align 4
|
|
// CHECK15-NEXT: [[DOTLINEAR_START:%.*]] = alloca i64, align 8
|
|
// CHECK15-NEXT: [[I7:%.*]] = alloca i32, align 4
|
|
// CHECK15-NEXT: [[K8:%.*]] = alloca i64, align 8
|
|
// CHECK15-NEXT: [[LIN:%.*]] = alloca i32, align 4
|
|
// CHECK15-NEXT: [[_TMP21:%.*]] = alloca i64, align 4
|
|
// CHECK15-NEXT: [[DOTOMP_LB22:%.*]] = alloca i64, align 8
|
|
// CHECK15-NEXT: [[DOTOMP_UB23:%.*]] = alloca i64, align 8
|
|
// CHECK15-NEXT: [[DOTOMP_IV24:%.*]] = alloca i64, align 8
|
|
// CHECK15-NEXT: [[DOTLINEAR_START25:%.*]] = alloca i32, align 4
|
|
// CHECK15-NEXT: [[DOTLINEAR_START26:%.*]] = alloca i32, align 4
|
|
// CHECK15-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8
|
|
// CHECK15-NEXT: [[IT:%.*]] = alloca i64, align 8
|
|
// CHECK15-NEXT: [[LIN28:%.*]] = alloca i32, align 4
|
|
// CHECK15-NEXT: [[A29:%.*]] = alloca i32, align 4
|
|
// CHECK15-NEXT: [[_TMP58:%.*]] = alloca i16, align 2
|
|
// CHECK15-NEXT: [[DOTOMP_LB59:%.*]] = alloca i32, align 4
|
|
// CHECK15-NEXT: [[DOTOMP_UB60:%.*]] = alloca i32, align 4
|
|
// CHECK15-NEXT: [[DOTOMP_IV61:%.*]] = alloca i32, align 4
|
|
// CHECK15-NEXT: [[IT62:%.*]] = alloca i16, align 2
|
|
// CHECK15-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
|
// CHECK15-NEXT: [[_TMP77:%.*]] = alloca i8, align 1
|
|
// CHECK15-NEXT: [[DOTOMP_LB78:%.*]] = alloca i32, align 4
|
|
// CHECK15-NEXT: [[DOTOMP_UB79:%.*]] = alloca i32, align 4
|
|
// CHECK15-NEXT: [[DOTOMP_IV80:%.*]] = alloca i32, align 4
|
|
// CHECK15-NEXT: [[IT81:%.*]] = alloca i8, align 1
|
|
// CHECK15-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK15-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK15-NEXT: store i16 0, i16* [[AA]], align 2
|
|
// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK15-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave()
|
|
// CHECK15-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4
|
|
// CHECK15-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4
|
|
// CHECK15-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4
|
|
// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK15-NEXT: [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]]
|
|
// CHECK15-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8
|
|
// CHECK15-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4
|
|
// CHECK15-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK15-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK15-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK15: omp.inner.for.cond:
|
|
// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
|
|
// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !3
|
|
// CHECK15-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
|
|
// CHECK15-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK15: omp.inner.for.body:
|
|
// CHECK15-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
|
|
// CHECK15-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5
|
|
// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]]
|
|
// CHECK15-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !3
|
|
// CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK15: omp.body.continue:
|
|
// CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK15: omp.inner.for.inc:
|
|
// CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
|
|
// CHECK15-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
|
|
// CHECK15-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
|
|
// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]
|
|
// CHECK15: omp.inner.for.end:
|
|
// CHECK15-NEXT: store i32 33, i32* [[I]], align 4
|
|
// CHECK15-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv()
|
|
// CHECK15-NEXT: store i64 [[CALL]], i64* [[K]], align 8
|
|
// CHECK15-NEXT: store i32 0, i32* [[DOTOMP_LB4]], align 4
|
|
// CHECK15-NEXT: store i32 8, i32* [[DOTOMP_UB5]], align 4
|
|
// CHECK15-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_LB4]], align 4
|
|
// CHECK15-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV6]], align 4
|
|
// CHECK15-NEXT: [[TMP10:%.*]] = load i64, i64* [[K]], align 8
|
|
// CHECK15-NEXT: store i64 [[TMP10]], i64* [[DOTLINEAR_START]], align 8
|
|
// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND9:%.*]]
|
|
// CHECK15: omp.inner.for.cond9:
|
|
// CHECK15-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !7
|
|
// CHECK15-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB5]], align 4, !llvm.access.group !7
|
|
// CHECK15-NEXT: [[CMP10:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]]
|
|
// CHECK15-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY11:%.*]], label [[OMP_INNER_FOR_END19:%.*]]
|
|
// CHECK15: omp.inner.for.body11:
|
|
// CHECK15-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !7
|
|
// CHECK15-NEXT: [[MUL12:%.*]] = mul nsw i32 [[TMP13]], 1
|
|
// CHECK15-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL12]]
|
|
// CHECK15-NEXT: store i32 [[SUB]], i32* [[I7]], align 4, !llvm.access.group !7
|
|
// CHECK15-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8, !llvm.access.group !7
|
|
// CHECK15-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !7
|
|
// CHECK15-NEXT: [[MUL13:%.*]] = mul nsw i32 [[TMP15]], 3
|
|
// CHECK15-NEXT: [[CONV:%.*]] = sext i32 [[MUL13]] to i64
|
|
// CHECK15-NEXT: [[ADD14:%.*]] = add nsw i64 [[TMP14]], [[CONV]]
|
|
// CHECK15-NEXT: store i64 [[ADD14]], i64* [[K8]], align 8, !llvm.access.group !7
|
|
// CHECK15-NEXT: [[TMP16:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !7
|
|
// CHECK15-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP16]], 1
|
|
// CHECK15-NEXT: store i32 [[ADD15]], i32* [[A]], align 4, !llvm.access.group !7
|
|
// CHECK15-NEXT: br label [[OMP_BODY_CONTINUE16:%.*]]
|
|
// CHECK15: omp.body.continue16:
|
|
// CHECK15-NEXT: br label [[OMP_INNER_FOR_INC17:%.*]]
|
|
// CHECK15: omp.inner.for.inc17:
|
|
// CHECK15-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !7
|
|
// CHECK15-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP17]], 1
|
|
// CHECK15-NEXT: store i32 [[ADD18]], i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !7
|
|
// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND9]], !llvm.loop [[LOOP8:![0-9]+]]
|
|
// CHECK15: omp.inner.for.end19:
|
|
// CHECK15-NEXT: store i32 1, i32* [[I7]], align 4
|
|
// CHECK15-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8
|
|
// CHECK15-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP18]], 27
|
|
// CHECK15-NEXT: store i64 [[ADD20]], i64* [[K]], align 8
|
|
// CHECK15-NEXT: store i32 12, i32* [[LIN]], align 4
|
|
// CHECK15-NEXT: store i64 0, i64* [[DOTOMP_LB22]], align 8
|
|
// CHECK15-NEXT: store i64 3, i64* [[DOTOMP_UB23]], align 8
|
|
// CHECK15-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_LB22]], align 8
|
|
// CHECK15-NEXT: store i64 [[TMP19]], i64* [[DOTOMP_IV24]], align 8
|
|
// CHECK15-NEXT: [[TMP20:%.*]] = load i32, i32* [[LIN]], align 4
|
|
// CHECK15-NEXT: store i32 [[TMP20]], i32* [[DOTLINEAR_START25]], align 4
|
|
// CHECK15-NEXT: [[TMP21:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK15-NEXT: store i32 [[TMP21]], i32* [[DOTLINEAR_START26]], align 4
|
|
// CHECK15-NEXT: [[CALL27:%.*]] = call i64 @_Z7get_valv()
|
|
// CHECK15-NEXT: store i64 [[CALL27]], i64* [[DOTLINEAR_STEP]], align 8
|
|
// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND30:%.*]]
|
|
// CHECK15: omp.inner.for.cond30:
|
|
// CHECK15-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !10
|
|
// CHECK15-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_UB23]], align 8, !llvm.access.group !10
|
|
// CHECK15-NEXT: [[CMP31:%.*]] = icmp ule i64 [[TMP22]], [[TMP23]]
|
|
// CHECK15-NEXT: br i1 [[CMP31]], label [[OMP_INNER_FOR_BODY32:%.*]], label [[OMP_INNER_FOR_END49:%.*]]
|
|
// CHECK15: omp.inner.for.body32:
|
|
// CHECK15-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !10
|
|
// CHECK15-NEXT: [[MUL33:%.*]] = mul i64 [[TMP24]], 400
|
|
// CHECK15-NEXT: [[SUB34:%.*]] = sub i64 2000, [[MUL33]]
|
|
// CHECK15-NEXT: store i64 [[SUB34]], i64* [[IT]], align 8, !llvm.access.group !10
|
|
// CHECK15-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTLINEAR_START25]], align 4, !llvm.access.group !10
|
|
// CHECK15-NEXT: [[CONV35:%.*]] = sext i32 [[TMP25]] to i64
|
|
// CHECK15-NEXT: [[TMP26:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !10
|
|
// CHECK15-NEXT: [[TMP27:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !10
|
|
// CHECK15-NEXT: [[MUL36:%.*]] = mul i64 [[TMP26]], [[TMP27]]
|
|
// CHECK15-NEXT: [[ADD37:%.*]] = add i64 [[CONV35]], [[MUL36]]
|
|
// CHECK15-NEXT: [[CONV38:%.*]] = trunc i64 [[ADD37]] to i32
|
|
// CHECK15-NEXT: store i32 [[CONV38]], i32* [[LIN28]], align 4, !llvm.access.group !10
|
|
// CHECK15-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTLINEAR_START26]], align 4, !llvm.access.group !10
|
|
// CHECK15-NEXT: [[CONV39:%.*]] = sext i32 [[TMP28]] to i64
|
|
// CHECK15-NEXT: [[TMP29:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !10
|
|
// CHECK15-NEXT: [[TMP30:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !10
|
|
// CHECK15-NEXT: [[MUL40:%.*]] = mul i64 [[TMP29]], [[TMP30]]
|
|
// CHECK15-NEXT: [[ADD41:%.*]] = add i64 [[CONV39]], [[MUL40]]
|
|
// CHECK15-NEXT: [[CONV42:%.*]] = trunc i64 [[ADD41]] to i32
|
|
// CHECK15-NEXT: store i32 [[CONV42]], i32* [[A29]], align 4, !llvm.access.group !10
|
|
// CHECK15-NEXT: [[TMP31:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !10
|
|
// CHECK15-NEXT: [[CONV43:%.*]] = sext i16 [[TMP31]] to i32
|
|
// CHECK15-NEXT: [[ADD44:%.*]] = add nsw i32 [[CONV43]], 1
|
|
// CHECK15-NEXT: [[CONV45:%.*]] = trunc i32 [[ADD44]] to i16
|
|
// CHECK15-NEXT: store i16 [[CONV45]], i16* [[AA]], align 2, !llvm.access.group !10
|
|
// CHECK15-NEXT: br label [[OMP_BODY_CONTINUE46:%.*]]
|
|
// CHECK15: omp.body.continue46:
|
|
// CHECK15-NEXT: br label [[OMP_INNER_FOR_INC47:%.*]]
|
|
// CHECK15: omp.inner.for.inc47:
|
|
// CHECK15-NEXT: [[TMP32:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !10
|
|
// CHECK15-NEXT: [[ADD48:%.*]] = add i64 [[TMP32]], 1
|
|
// CHECK15-NEXT: store i64 [[ADD48]], i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !10
|
|
// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND30]], !llvm.loop [[LOOP11:![0-9]+]]
|
|
// CHECK15: omp.inner.for.end49:
|
|
// CHECK15-NEXT: store i64 400, i64* [[IT]], align 8
|
|
// CHECK15-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTLINEAR_START25]], align 4
|
|
// CHECK15-NEXT: [[CONV50:%.*]] = sext i32 [[TMP33]] to i64
|
|
// CHECK15-NEXT: [[TMP34:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
|
|
// CHECK15-NEXT: [[MUL51:%.*]] = mul i64 4, [[TMP34]]
|
|
// CHECK15-NEXT: [[ADD52:%.*]] = add i64 [[CONV50]], [[MUL51]]
|
|
// CHECK15-NEXT: [[CONV53:%.*]] = trunc i64 [[ADD52]] to i32
|
|
// CHECK15-NEXT: store i32 [[CONV53]], i32* [[LIN]], align 4
|
|
// CHECK15-NEXT: [[TMP35:%.*]] = load i32, i32* [[DOTLINEAR_START26]], align 4
|
|
// CHECK15-NEXT: [[CONV54:%.*]] = sext i32 [[TMP35]] to i64
|
|
// CHECK15-NEXT: [[TMP36:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
|
|
// CHECK15-NEXT: [[MUL55:%.*]] = mul i64 4, [[TMP36]]
|
|
// CHECK15-NEXT: [[ADD56:%.*]] = add i64 [[CONV54]], [[MUL55]]
|
|
// CHECK15-NEXT: [[CONV57:%.*]] = trunc i64 [[ADD56]] to i32
|
|
// CHECK15-NEXT: store i32 [[CONV57]], i32* [[A]], align 4
|
|
// CHECK15-NEXT: store i32 0, i32* [[DOTOMP_LB59]], align 4
|
|
// CHECK15-NEXT: store i32 3, i32* [[DOTOMP_UB60]], align 4
|
|
// CHECK15-NEXT: [[TMP37:%.*]] = load i32, i32* [[DOTOMP_LB59]], align 4
|
|
// CHECK15-NEXT: store i32 [[TMP37]], i32* [[DOTOMP_IV61]], align 4
|
|
// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND63:%.*]]
|
|
// CHECK15: omp.inner.for.cond63:
|
|
// CHECK15-NEXT: [[TMP38:%.*]] = load i32, i32* [[DOTOMP_IV61]], align 4, !llvm.access.group !13
|
|
// CHECK15-NEXT: [[TMP39:%.*]] = load i32, i32* [[DOTOMP_UB60]], align 4, !llvm.access.group !13
|
|
// CHECK15-NEXT: [[CMP64:%.*]] = icmp sle i32 [[TMP38]], [[TMP39]]
|
|
// CHECK15-NEXT: br i1 [[CMP64]], label [[OMP_INNER_FOR_BODY65:%.*]], label [[OMP_INNER_FOR_END76:%.*]]
|
|
// CHECK15: omp.inner.for.body65:
|
|
// CHECK15-NEXT: [[TMP40:%.*]] = load i32, i32* [[DOTOMP_IV61]], align 4, !llvm.access.group !13
|
|
// CHECK15-NEXT: [[MUL66:%.*]] = mul nsw i32 [[TMP40]], 4
|
|
// CHECK15-NEXT: [[ADD67:%.*]] = add nsw i32 6, [[MUL66]]
|
|
// CHECK15-NEXT: [[CONV68:%.*]] = trunc i32 [[ADD67]] to i16
|
|
// CHECK15-NEXT: store i16 [[CONV68]], i16* [[IT62]], align 2, !llvm.access.group !13
|
|
// CHECK15-NEXT: [[TMP41:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !13
|
|
// CHECK15-NEXT: [[ADD69:%.*]] = add nsw i32 [[TMP41]], 1
|
|
// CHECK15-NEXT: store i32 [[ADD69]], i32* [[A]], align 4, !llvm.access.group !13
|
|
// CHECK15-NEXT: [[TMP42:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !13
|
|
// CHECK15-NEXT: [[CONV70:%.*]] = sext i16 [[TMP42]] to i32
|
|
// CHECK15-NEXT: [[ADD71:%.*]] = add nsw i32 [[CONV70]], 1
|
|
// CHECK15-NEXT: [[CONV72:%.*]] = trunc i32 [[ADD71]] to i16
|
|
// CHECK15-NEXT: store i16 [[CONV72]], i16* [[AA]], align 2, !llvm.access.group !13
|
|
// CHECK15-NEXT: br label [[OMP_BODY_CONTINUE73:%.*]]
|
|
// CHECK15: omp.body.continue73:
|
|
// CHECK15-NEXT: br label [[OMP_INNER_FOR_INC74:%.*]]
|
|
// CHECK15: omp.inner.for.inc74:
|
|
// CHECK15-NEXT: [[TMP43:%.*]] = load i32, i32* [[DOTOMP_IV61]], align 4, !llvm.access.group !13
|
|
// CHECK15-NEXT: [[ADD75:%.*]] = add nsw i32 [[TMP43]], 1
|
|
// CHECK15-NEXT: store i32 [[ADD75]], i32* [[DOTOMP_IV61]], align 4, !llvm.access.group !13
|
|
// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND63]], !llvm.loop [[LOOP14:![0-9]+]]
|
|
// CHECK15: omp.inner.for.end76:
|
|
// CHECK15-NEXT: store i16 22, i16* [[IT62]], align 2
|
|
// CHECK15-NEXT: [[TMP44:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK15-NEXT: store i32 [[TMP44]], i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK15-NEXT: store i32 0, i32* [[DOTOMP_LB78]], align 4
|
|
// CHECK15-NEXT: store i32 25, i32* [[DOTOMP_UB79]], align 4
|
|
// CHECK15-NEXT: [[TMP45:%.*]] = load i32, i32* [[DOTOMP_LB78]], align 4
|
|
// CHECK15-NEXT: store i32 [[TMP45]], i32* [[DOTOMP_IV80]], align 4
|
|
// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND82:%.*]]
|
|
// CHECK15: omp.inner.for.cond82:
|
|
// CHECK15-NEXT: [[TMP46:%.*]] = load i32, i32* [[DOTOMP_IV80]], align 4, !llvm.access.group !16
|
|
// CHECK15-NEXT: [[TMP47:%.*]] = load i32, i32* [[DOTOMP_UB79]], align 4, !llvm.access.group !16
|
|
// CHECK15-NEXT: [[CMP83:%.*]] = icmp sle i32 [[TMP46]], [[TMP47]]
|
|
// CHECK15-NEXT: br i1 [[CMP83]], label [[OMP_INNER_FOR_BODY84:%.*]], label [[OMP_INNER_FOR_END109:%.*]]
|
|
// CHECK15: omp.inner.for.body84:
|
|
// CHECK15-NEXT: [[TMP48:%.*]] = load i32, i32* [[DOTOMP_IV80]], align 4, !llvm.access.group !16
|
|
// CHECK15-NEXT: [[MUL85:%.*]] = mul nsw i32 [[TMP48]], 1
|
|
// CHECK15-NEXT: [[SUB86:%.*]] = sub nsw i32 122, [[MUL85]]
|
|
// CHECK15-NEXT: [[CONV87:%.*]] = trunc i32 [[SUB86]] to i8
|
|
// CHECK15-NEXT: store i8 [[CONV87]], i8* [[IT81]], align 1, !llvm.access.group !16
|
|
// CHECK15-NEXT: [[TMP49:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !16
|
|
// CHECK15-NEXT: [[ADD88:%.*]] = add nsw i32 [[TMP49]], 1
|
|
// CHECK15-NEXT: store i32 [[ADD88]], i32* [[A]], align 4, !llvm.access.group !16
|
|
// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 2
|
|
// CHECK15-NEXT: [[TMP50:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !16
|
|
// CHECK15-NEXT: [[CONV89:%.*]] = fpext float [[TMP50]] to double
|
|
// CHECK15-NEXT: [[ADD90:%.*]] = fadd double [[CONV89]], 1.000000e+00
|
|
// CHECK15-NEXT: [[CONV91:%.*]] = fptrunc double [[ADD90]] to float
|
|
// CHECK15-NEXT: store float [[CONV91]], float* [[ARRAYIDX]], align 4, !llvm.access.group !16
|
|
// CHECK15-NEXT: [[ARRAYIDX92:%.*]] = getelementptr inbounds float, float* [[VLA]], i32 3
|
|
// CHECK15-NEXT: [[TMP51:%.*]] = load float, float* [[ARRAYIDX92]], align 4, !llvm.access.group !16
|
|
// CHECK15-NEXT: [[CONV93:%.*]] = fpext float [[TMP51]] to double
|
|
// CHECK15-NEXT: [[ADD94:%.*]] = fadd double [[CONV93]], 1.000000e+00
|
|
// CHECK15-NEXT: [[CONV95:%.*]] = fptrunc double [[ADD94]] to float
|
|
// CHECK15-NEXT: store float [[CONV95]], float* [[ARRAYIDX92]], align 4, !llvm.access.group !16
|
|
// CHECK15-NEXT: [[ARRAYIDX96:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i32 0, i32 1
|
|
// CHECK15-NEXT: [[ARRAYIDX97:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX96]], i32 0, i32 2
|
|
// CHECK15-NEXT: [[TMP52:%.*]] = load double, double* [[ARRAYIDX97]], align 8, !llvm.access.group !16
|
|
// CHECK15-NEXT: [[ADD98:%.*]] = fadd double [[TMP52]], 1.000000e+00
|
|
// CHECK15-NEXT: store double [[ADD98]], double* [[ARRAYIDX97]], align 8, !llvm.access.group !16
|
|
// CHECK15-NEXT: [[TMP53:%.*]] = mul nsw i32 1, [[TMP2]]
|
|
// CHECK15-NEXT: [[ARRAYIDX99:%.*]] = getelementptr inbounds double, double* [[VLA1]], i32 [[TMP53]]
|
|
// CHECK15-NEXT: [[ARRAYIDX100:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX99]], i32 3
|
|
// CHECK15-NEXT: [[TMP54:%.*]] = load double, double* [[ARRAYIDX100]], align 8, !llvm.access.group !16
|
|
// CHECK15-NEXT: [[ADD101:%.*]] = fadd double [[TMP54]], 1.000000e+00
|
|
// CHECK15-NEXT: store double [[ADD101]], double* [[ARRAYIDX100]], align 8, !llvm.access.group !16
|
|
// CHECK15-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0
|
|
// CHECK15-NEXT: [[TMP55:%.*]] = load i64, i64* [[X]], align 4, !llvm.access.group !16
|
|
// CHECK15-NEXT: [[ADD102:%.*]] = add nsw i64 [[TMP55]], 1
|
|
// CHECK15-NEXT: store i64 [[ADD102]], i64* [[X]], align 4, !llvm.access.group !16
|
|
// CHECK15-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1
|
|
// CHECK15-NEXT: [[TMP56:%.*]] = load i8, i8* [[Y]], align 4, !llvm.access.group !16
|
|
// CHECK15-NEXT: [[CONV103:%.*]] = sext i8 [[TMP56]] to i32
|
|
// CHECK15-NEXT: [[ADD104:%.*]] = add nsw i32 [[CONV103]], 1
|
|
// CHECK15-NEXT: [[CONV105:%.*]] = trunc i32 [[ADD104]] to i8
|
|
// CHECK15-NEXT: store i8 [[CONV105]], i8* [[Y]], align 4, !llvm.access.group !16
|
|
// CHECK15-NEXT: br label [[OMP_BODY_CONTINUE106:%.*]]
|
|
// CHECK15: omp.body.continue106:
|
|
// CHECK15-NEXT: br label [[OMP_INNER_FOR_INC107:%.*]]
|
|
// CHECK15: omp.inner.for.inc107:
|
|
// CHECK15-NEXT: [[TMP57:%.*]] = load i32, i32* [[DOTOMP_IV80]], align 4, !llvm.access.group !16
|
|
// CHECK15-NEXT: [[ADD108:%.*]] = add nsw i32 [[TMP57]], 1
|
|
// CHECK15-NEXT: store i32 [[ADD108]], i32* [[DOTOMP_IV80]], align 4, !llvm.access.group !16
|
|
// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND82]], !llvm.loop [[LOOP17:![0-9]+]]
|
|
// CHECK15: omp.inner.for.end109:
|
|
// CHECK15-NEXT: store i8 96, i8* [[IT81]], align 1
|
|
// CHECK15-NEXT: [[TMP58:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK15-NEXT: [[TMP59:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
|
|
// CHECK15-NEXT: call void @llvm.stackrestore(i8* [[TMP59]])
|
|
// CHECK15-NEXT: ret i32 [[TMP58]]
|
|
//
|
|
//
|
|
// CHECK15-LABEL: define {{[^@]+}}@_Z3bari
|
|
// CHECK15-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
|
|
// CHECK15-NEXT: entry:
|
|
// CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK15-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK15-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4
|
|
// CHECK15-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK15-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK15-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]])
|
|
// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
|
|
// CHECK15-NEXT: store i32 [[ADD]], i32* [[A]], align 4
|
|
// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK15-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]])
|
|
// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK15-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
|
|
// CHECK15-NEXT: store i32 [[ADD2]], i32* [[A]], align 4
|
|
// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK15-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]])
|
|
// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK15-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
|
|
// CHECK15-NEXT: store i32 [[ADD4]], i32* [[A]], align 4
|
|
// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK15-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]])
|
|
// CHECK15-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK15-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
|
|
// CHECK15-NEXT: store i32 [[ADD6]], i32* [[A]], align 4
|
|
// CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK15-NEXT: ret i32 [[TMP8]]
|
|
//
|
|
//
|
|
// CHECK15-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
|
|
// CHECK15-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 {
|
|
// CHECK15-NEXT: entry:
|
|
// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
|
|
// CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK15-NEXT: [[B:%.*]] = alloca i32, align 4
|
|
// CHECK15-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4
|
|
// CHECK15-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4
|
|
// CHECK15-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
|
|
// CHECK15-NEXT: [[TMP:%.*]] = alloca i64, align 4
|
|
// CHECK15-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
|
|
// CHECK15-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
|
|
// CHECK15-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
|
|
// CHECK15-NEXT: [[IT:%.*]] = alloca i64, align 8
|
|
// CHECK15-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK15-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
|
|
// CHECK15-NEXT: store i32 [[ADD]], i32* [[B]], align 4
|
|
// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK15-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave()
|
|
// CHECK15-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4
|
|
// CHECK15-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]]
|
|
// CHECK15-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2
|
|
// CHECK15-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4
|
|
// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK15-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 60
|
|
// CHECK15-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8
|
|
// CHECK15-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
|
|
// CHECK15-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK15-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK15-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK15-NEXT: store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK15-NEXT: [[TMP6:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
|
|
// CHECK15-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP6]] to i1
|
|
// CHECK15-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
|
|
// CHECK15: omp_if.then:
|
|
// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK15: omp.inner.for.cond:
|
|
// CHECK15-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !19
|
|
// CHECK15-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !19
|
|
// CHECK15-NEXT: [[CMP2:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]]
|
|
// CHECK15-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK15: omp.inner.for.body:
|
|
// CHECK15-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !19
|
|
// CHECK15-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400
|
|
// CHECK15-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]
|
|
// CHECK15-NEXT: store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !19
|
|
// CHECK15-NEXT: [[TMP10:%.*]] = load i32, i32* [[B]], align 4, !llvm.access.group !19
|
|
// CHECK15-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP10]] to double
|
|
// CHECK15-NEXT: [[ADD3:%.*]] = fadd double [[CONV]], 1.500000e+00
|
|
// CHECK15-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
|
|
// CHECK15-NEXT: store double [[ADD3]], double* [[A]], align 4, !nontemporal !20, !llvm.access.group !19
|
|
// CHECK15-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
|
|
// CHECK15-NEXT: [[TMP11:%.*]] = load double, double* [[A4]], align 4, !nontemporal !20, !llvm.access.group !19
|
|
// CHECK15-NEXT: [[INC:%.*]] = fadd double [[TMP11]], 1.000000e+00
|
|
// CHECK15-NEXT: store double [[INC]], double* [[A4]], align 4, !nontemporal !20, !llvm.access.group !19
|
|
// CHECK15-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16
|
|
// CHECK15-NEXT: [[TMP12:%.*]] = mul nsw i32 1, [[TMP1]]
|
|
// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP12]]
|
|
// CHECK15-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
|
|
// CHECK15-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2, !llvm.access.group !19
|
|
// CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK15: omp.body.continue:
|
|
// CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK15: omp.inner.for.inc:
|
|
// CHECK15-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !19
|
|
// CHECK15-NEXT: [[ADD7:%.*]] = add i64 [[TMP13]], 1
|
|
// CHECK15-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !19
|
|
// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]]
|
|
// CHECK15: omp.inner.for.end:
|
|
// CHECK15-NEXT: br label [[OMP_IF_END:%.*]]
|
|
// CHECK15: omp_if.else:
|
|
// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND8:%.*]]
|
|
// CHECK15: omp.inner.for.cond8:
|
|
// CHECK15-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK15-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK15-NEXT: [[CMP9:%.*]] = icmp ule i64 [[TMP14]], [[TMP15]]
|
|
// CHECK15-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY10:%.*]], label [[OMP_INNER_FOR_END24:%.*]]
|
|
// CHECK15: omp.inner.for.body10:
|
|
// CHECK15-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK15-NEXT: [[MUL11:%.*]] = mul i64 [[TMP16]], 400
|
|
// CHECK15-NEXT: [[SUB12:%.*]] = sub i64 2000, [[MUL11]]
|
|
// CHECK15-NEXT: store i64 [[SUB12]], i64* [[IT]], align 8
|
|
// CHECK15-NEXT: [[TMP17:%.*]] = load i32, i32* [[B]], align 4
|
|
// CHECK15-NEXT: [[CONV13:%.*]] = sitofp i32 [[TMP17]] to double
|
|
// CHECK15-NEXT: [[ADD14:%.*]] = fadd double [[CONV13]], 1.500000e+00
|
|
// CHECK15-NEXT: [[A15:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
|
|
// CHECK15-NEXT: store double [[ADD14]], double* [[A15]], align 4
|
|
// CHECK15-NEXT: [[A16:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
|
|
// CHECK15-NEXT: [[TMP18:%.*]] = load double, double* [[A16]], align 4
|
|
// CHECK15-NEXT: [[INC17:%.*]] = fadd double [[TMP18]], 1.000000e+00
|
|
// CHECK15-NEXT: store double [[INC17]], double* [[A16]], align 4
|
|
// CHECK15-NEXT: [[CONV18:%.*]] = fptosi double [[INC17]] to i16
|
|
// CHECK15-NEXT: [[TMP19:%.*]] = mul nsw i32 1, [[TMP1]]
|
|
// CHECK15-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP19]]
|
|
// CHECK15-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX19]], i32 1
|
|
// CHECK15-NEXT: store i16 [[CONV18]], i16* [[ARRAYIDX20]], align 2
|
|
// CHECK15-NEXT: br label [[OMP_BODY_CONTINUE21:%.*]]
|
|
// CHECK15: omp.body.continue21:
|
|
// CHECK15-NEXT: br label [[OMP_INNER_FOR_INC22:%.*]]
|
|
// CHECK15: omp.inner.for.inc22:
|
|
// CHECK15-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK15-NEXT: [[ADD23:%.*]] = add i64 [[TMP20]], 1
|
|
// CHECK15-NEXT: store i64 [[ADD23]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND8]], !llvm.loop [[LOOP23:![0-9]+]]
|
|
// CHECK15: omp.inner.for.end24:
|
|
// CHECK15-NEXT: br label [[OMP_IF_END]]
|
|
// CHECK15: omp_if.end:
|
|
// CHECK15-NEXT: store i64 400, i64* [[IT]], align 8
|
|
// CHECK15-NEXT: [[TMP21:%.*]] = mul nsw i32 1, [[TMP1]]
|
|
// CHECK15-NEXT: [[ARRAYIDX25:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP21]]
|
|
// CHECK15-NEXT: [[ARRAYIDX26:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX25]], i32 1
|
|
// CHECK15-NEXT: [[TMP22:%.*]] = load i16, i16* [[ARRAYIDX26]], align 2
|
|
// CHECK15-NEXT: [[CONV27:%.*]] = sext i16 [[TMP22]] to i32
|
|
// CHECK15-NEXT: [[TMP23:%.*]] = load i32, i32* [[B]], align 4
|
|
// CHECK15-NEXT: [[ADD28:%.*]] = add nsw i32 [[CONV27]], [[TMP23]]
|
|
// CHECK15-NEXT: [[TMP24:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
|
|
// CHECK15-NEXT: call void @llvm.stackrestore(i8* [[TMP24]])
|
|
// CHECK15-NEXT: ret i32 [[ADD28]]
|
|
//
|
|
//
|
|
// CHECK15-LABEL: define {{[^@]+}}@_ZL7fstatici
|
|
// CHECK15-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
|
|
// CHECK15-NEXT: entry:
|
|
// CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK15-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK15-NEXT: [[AA:%.*]] = alloca i16, align 2
|
|
// CHECK15-NEXT: [[AAA:%.*]] = alloca i8, align 1
|
|
// CHECK15-NEXT: [[B:%.*]] = alloca [10 x i32], align 4
|
|
// CHECK15-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK15-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK15-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK15-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK15-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK15-NEXT: store i16 0, i16* [[AA]], align 2
|
|
// CHECK15-NEXT: store i8 0, i8* [[AAA]], align 1
|
|
// CHECK15-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK15-NEXT: store i32 429496720, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK15-NEXT: ret i32 [[TMP0]]
|
|
//
|
|
//
|
|
// CHECK15-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
|
|
// CHECK15-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat {
|
|
// CHECK15-NEXT: entry:
|
|
// CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK15-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK15-NEXT: [[AA:%.*]] = alloca i16, align 2
|
|
// CHECK15-NEXT: [[B:%.*]] = alloca [10 x i32], align 4
|
|
// CHECK15-NEXT: [[TMP:%.*]] = alloca i64, align 4
|
|
// CHECK15-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
|
|
// CHECK15-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
|
|
// CHECK15-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
|
|
// CHECK15-NEXT: [[I:%.*]] = alloca i64, align 8
|
|
// CHECK15-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK15-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK15-NEXT: store i16 0, i16* [[AA]], align 2
|
|
// CHECK15-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK15-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK15-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK15-NEXT: store i64 [[TMP0]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK15: omp.inner.for.cond:
|
|
// CHECK15-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !25
|
|
// CHECK15-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !25
|
|
// CHECK15-NEXT: [[CMP:%.*]] = icmp sle i64 [[TMP1]], [[TMP2]]
|
|
// CHECK15-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK15: omp.inner.for.body:
|
|
// CHECK15-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !25
|
|
// CHECK15-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP3]], 3
|
|
// CHECK15-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
|
|
// CHECK15-NEXT: store i64 [[ADD]], i64* [[I]], align 8, !llvm.access.group !25
|
|
// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !25
|
|
// CHECK15-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1
|
|
// CHECK15-NEXT: store i32 [[ADD1]], i32* [[A]], align 4, !llvm.access.group !25
|
|
// CHECK15-NEXT: [[TMP5:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !25
|
|
// CHECK15-NEXT: [[CONV:%.*]] = sext i16 [[TMP5]] to i32
|
|
// CHECK15-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 1
|
|
// CHECK15-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
|
|
// CHECK15-NEXT: store i16 [[CONV3]], i16* [[AA]], align 2, !llvm.access.group !25
|
|
// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2
|
|
// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !25
|
|
// CHECK15-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP6]], 1
|
|
// CHECK15-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !25
|
|
// CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK15: omp.body.continue:
|
|
// CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK15: omp.inner.for.inc:
|
|
// CHECK15-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !25
|
|
// CHECK15-NEXT: [[ADD5:%.*]] = add nsw i64 [[TMP7]], 1
|
|
// CHECK15-NEXT: store i64 [[ADD5]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !25
|
|
// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP26:![0-9]+]]
|
|
// CHECK15: omp.inner.for.end:
|
|
// CHECK15-NEXT: store i64 11, i64* [[I]], align 8
|
|
// CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK15-NEXT: ret i32 [[TMP8]]
|
|
//
|
|
//
|
|
// CHECK16-LABEL: define {{[^@]+}}@_Z7get_valv
|
|
// CHECK16-SAME: () #[[ATTR0:[0-9]+]] {
|
|
// CHECK16-NEXT: entry:
|
|
// CHECK16-NEXT: ret i64 0
|
|
//
|
|
//
|
|
// CHECK16-LABEL: define {{[^@]+}}@_Z3fooi
|
|
// CHECK16-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
|
|
// CHECK16-NEXT: entry:
|
|
// CHECK16-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK16-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK16-NEXT: [[AA:%.*]] = alloca i16, align 2
|
|
// CHECK16-NEXT: [[B:%.*]] = alloca [10 x float], align 4
|
|
// CHECK16-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4
|
|
// CHECK16-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4
|
|
// CHECK16-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8
|
|
// CHECK16-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4
|
|
// CHECK16-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4
|
|
// CHECK16-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK16-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK16-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK16-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4
|
|
// CHECK16-NEXT: [[K:%.*]] = alloca i64, align 8
|
|
// CHECK16-NEXT: [[_TMP3:%.*]] = alloca i32, align 4
|
|
// CHECK16-NEXT: [[DOTOMP_LB4:%.*]] = alloca i32, align 4
|
|
// CHECK16-NEXT: [[DOTOMP_UB5:%.*]] = alloca i32, align 4
|
|
// CHECK16-NEXT: [[DOTOMP_IV6:%.*]] = alloca i32, align 4
|
|
// CHECK16-NEXT: [[DOTLINEAR_START:%.*]] = alloca i64, align 8
|
|
// CHECK16-NEXT: [[I7:%.*]] = alloca i32, align 4
|
|
// CHECK16-NEXT: [[K8:%.*]] = alloca i64, align 8
|
|
// CHECK16-NEXT: [[LIN:%.*]] = alloca i32, align 4
|
|
// CHECK16-NEXT: [[_TMP21:%.*]] = alloca i64, align 4
|
|
// CHECK16-NEXT: [[DOTOMP_LB22:%.*]] = alloca i64, align 8
|
|
// CHECK16-NEXT: [[DOTOMP_UB23:%.*]] = alloca i64, align 8
|
|
// CHECK16-NEXT: [[DOTOMP_IV24:%.*]] = alloca i64, align 8
|
|
// CHECK16-NEXT: [[DOTLINEAR_START25:%.*]] = alloca i32, align 4
|
|
// CHECK16-NEXT: [[DOTLINEAR_START26:%.*]] = alloca i32, align 4
|
|
// CHECK16-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8
|
|
// CHECK16-NEXT: [[IT:%.*]] = alloca i64, align 8
|
|
// CHECK16-NEXT: [[LIN28:%.*]] = alloca i32, align 4
|
|
// CHECK16-NEXT: [[A29:%.*]] = alloca i32, align 4
|
|
// CHECK16-NEXT: [[_TMP58:%.*]] = alloca i16, align 2
|
|
// CHECK16-NEXT: [[DOTOMP_LB59:%.*]] = alloca i32, align 4
|
|
// CHECK16-NEXT: [[DOTOMP_UB60:%.*]] = alloca i32, align 4
|
|
// CHECK16-NEXT: [[DOTOMP_IV61:%.*]] = alloca i32, align 4
|
|
// CHECK16-NEXT: [[IT62:%.*]] = alloca i16, align 2
|
|
// CHECK16-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
|
// CHECK16-NEXT: [[_TMP77:%.*]] = alloca i8, align 1
|
|
// CHECK16-NEXT: [[DOTOMP_LB78:%.*]] = alloca i32, align 4
|
|
// CHECK16-NEXT: [[DOTOMP_UB79:%.*]] = alloca i32, align 4
|
|
// CHECK16-NEXT: [[DOTOMP_IV80:%.*]] = alloca i32, align 4
|
|
// CHECK16-NEXT: [[IT81:%.*]] = alloca i8, align 1
|
|
// CHECK16-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK16-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK16-NEXT: store i16 0, i16* [[AA]], align 2
|
|
// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK16-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave()
|
|
// CHECK16-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4
|
|
// CHECK16-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4
|
|
// CHECK16-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4
|
|
// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK16-NEXT: [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]]
|
|
// CHECK16-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8
|
|
// CHECK16-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4
|
|
// CHECK16-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK16-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK16-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK16: omp.inner.for.cond:
|
|
// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
|
|
// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !3
|
|
// CHECK16-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
|
|
// CHECK16-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK16: omp.inner.for.body:
|
|
// CHECK16-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
|
|
// CHECK16-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5
|
|
// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]]
|
|
// CHECK16-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !3
|
|
// CHECK16-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK16: omp.body.continue:
|
|
// CHECK16-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK16: omp.inner.for.inc:
|
|
// CHECK16-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
|
|
// CHECK16-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
|
|
// CHECK16-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
|
|
// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]
|
|
// CHECK16: omp.inner.for.end:
|
|
// CHECK16-NEXT: store i32 33, i32* [[I]], align 4
|
|
// CHECK16-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv()
|
|
// CHECK16-NEXT: store i64 [[CALL]], i64* [[K]], align 8
|
|
// CHECK16-NEXT: store i32 0, i32* [[DOTOMP_LB4]], align 4
|
|
// CHECK16-NEXT: store i32 8, i32* [[DOTOMP_UB5]], align 4
|
|
// CHECK16-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_LB4]], align 4
|
|
// CHECK16-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV6]], align 4
|
|
// CHECK16-NEXT: [[TMP10:%.*]] = load i64, i64* [[K]], align 8
|
|
// CHECK16-NEXT: store i64 [[TMP10]], i64* [[DOTLINEAR_START]], align 8
|
|
// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND9:%.*]]
|
|
// CHECK16: omp.inner.for.cond9:
|
|
// CHECK16-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !7
|
|
// CHECK16-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB5]], align 4, !llvm.access.group !7
|
|
// CHECK16-NEXT: [[CMP10:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]]
|
|
// CHECK16-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY11:%.*]], label [[OMP_INNER_FOR_END19:%.*]]
|
|
// CHECK16: omp.inner.for.body11:
|
|
// CHECK16-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !7
|
|
// CHECK16-NEXT: [[MUL12:%.*]] = mul nsw i32 [[TMP13]], 1
|
|
// CHECK16-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL12]]
|
|
// CHECK16-NEXT: store i32 [[SUB]], i32* [[I7]], align 4, !llvm.access.group !7
|
|
// CHECK16-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8, !llvm.access.group !7
|
|
// CHECK16-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !7
|
|
// CHECK16-NEXT: [[MUL13:%.*]] = mul nsw i32 [[TMP15]], 3
|
|
// CHECK16-NEXT: [[CONV:%.*]] = sext i32 [[MUL13]] to i64
|
|
// CHECK16-NEXT: [[ADD14:%.*]] = add nsw i64 [[TMP14]], [[CONV]]
|
|
// CHECK16-NEXT: store i64 [[ADD14]], i64* [[K8]], align 8, !llvm.access.group !7
|
|
// CHECK16-NEXT: [[TMP16:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !7
|
|
// CHECK16-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP16]], 1
|
|
// CHECK16-NEXT: store i32 [[ADD15]], i32* [[A]], align 4, !llvm.access.group !7
|
|
// CHECK16-NEXT: br label [[OMP_BODY_CONTINUE16:%.*]]
|
|
// CHECK16: omp.body.continue16:
|
|
// CHECK16-NEXT: br label [[OMP_INNER_FOR_INC17:%.*]]
|
|
// CHECK16: omp.inner.for.inc17:
|
|
// CHECK16-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !7
|
|
// CHECK16-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP17]], 1
|
|
// CHECK16-NEXT: store i32 [[ADD18]], i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !7
|
|
// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND9]], !llvm.loop [[LOOP8:![0-9]+]]
|
|
// CHECK16: omp.inner.for.end19:
|
|
// CHECK16-NEXT: store i32 1, i32* [[I7]], align 4
|
|
// CHECK16-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8
|
|
// CHECK16-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP18]], 27
|
|
// CHECK16-NEXT: store i64 [[ADD20]], i64* [[K]], align 8
|
|
// CHECK16-NEXT: store i32 12, i32* [[LIN]], align 4
|
|
// CHECK16-NEXT: store i64 0, i64* [[DOTOMP_LB22]], align 8
|
|
// CHECK16-NEXT: store i64 3, i64* [[DOTOMP_UB23]], align 8
|
|
// CHECK16-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_LB22]], align 8
|
|
// CHECK16-NEXT: store i64 [[TMP19]], i64* [[DOTOMP_IV24]], align 8
|
|
// CHECK16-NEXT: [[TMP20:%.*]] = load i32, i32* [[LIN]], align 4
|
|
// CHECK16-NEXT: store i32 [[TMP20]], i32* [[DOTLINEAR_START25]], align 4
|
|
// CHECK16-NEXT: [[TMP21:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK16-NEXT: store i32 [[TMP21]], i32* [[DOTLINEAR_START26]], align 4
|
|
// CHECK16-NEXT: [[CALL27:%.*]] = call i64 @_Z7get_valv()
|
|
// CHECK16-NEXT: store i64 [[CALL27]], i64* [[DOTLINEAR_STEP]], align 8
|
|
// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND30:%.*]]
|
|
// CHECK16: omp.inner.for.cond30:
|
|
// CHECK16-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !10
|
|
// CHECK16-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_UB23]], align 8, !llvm.access.group !10
|
|
// CHECK16-NEXT: [[CMP31:%.*]] = icmp ule i64 [[TMP22]], [[TMP23]]
|
|
// CHECK16-NEXT: br i1 [[CMP31]], label [[OMP_INNER_FOR_BODY32:%.*]], label [[OMP_INNER_FOR_END49:%.*]]
|
|
// CHECK16: omp.inner.for.body32:
|
|
// CHECK16-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !10
|
|
// CHECK16-NEXT: [[MUL33:%.*]] = mul i64 [[TMP24]], 400
|
|
// CHECK16-NEXT: [[SUB34:%.*]] = sub i64 2000, [[MUL33]]
|
|
// CHECK16-NEXT: store i64 [[SUB34]], i64* [[IT]], align 8, !llvm.access.group !10
|
|
// CHECK16-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTLINEAR_START25]], align 4, !llvm.access.group !10
|
|
// CHECK16-NEXT: [[CONV35:%.*]] = sext i32 [[TMP25]] to i64
|
|
// CHECK16-NEXT: [[TMP26:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !10
|
|
// CHECK16-NEXT: [[TMP27:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !10
|
|
// CHECK16-NEXT: [[MUL36:%.*]] = mul i64 [[TMP26]], [[TMP27]]
|
|
// CHECK16-NEXT: [[ADD37:%.*]] = add i64 [[CONV35]], [[MUL36]]
|
|
// CHECK16-NEXT: [[CONV38:%.*]] = trunc i64 [[ADD37]] to i32
|
|
// CHECK16-NEXT: store i32 [[CONV38]], i32* [[LIN28]], align 4, !llvm.access.group !10
|
|
// CHECK16-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTLINEAR_START26]], align 4, !llvm.access.group !10
|
|
// CHECK16-NEXT: [[CONV39:%.*]] = sext i32 [[TMP28]] to i64
|
|
// CHECK16-NEXT: [[TMP29:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !10
|
|
// CHECK16-NEXT: [[TMP30:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !10
|
|
// CHECK16-NEXT: [[MUL40:%.*]] = mul i64 [[TMP29]], [[TMP30]]
|
|
// CHECK16-NEXT: [[ADD41:%.*]] = add i64 [[CONV39]], [[MUL40]]
|
|
// CHECK16-NEXT: [[CONV42:%.*]] = trunc i64 [[ADD41]] to i32
|
|
// CHECK16-NEXT: store i32 [[CONV42]], i32* [[A29]], align 4, !llvm.access.group !10
|
|
// CHECK16-NEXT: [[TMP31:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !10
|
|
// CHECK16-NEXT: [[CONV43:%.*]] = sext i16 [[TMP31]] to i32
|
|
// CHECK16-NEXT: [[ADD44:%.*]] = add nsw i32 [[CONV43]], 1
|
|
// CHECK16-NEXT: [[CONV45:%.*]] = trunc i32 [[ADD44]] to i16
|
|
// CHECK16-NEXT: store i16 [[CONV45]], i16* [[AA]], align 2, !llvm.access.group !10
|
|
// CHECK16-NEXT: br label [[OMP_BODY_CONTINUE46:%.*]]
|
|
// CHECK16: omp.body.continue46:
|
|
// CHECK16-NEXT: br label [[OMP_INNER_FOR_INC47:%.*]]
|
|
// CHECK16: omp.inner.for.inc47:
|
|
// CHECK16-NEXT: [[TMP32:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !10
|
|
// CHECK16-NEXT: [[ADD48:%.*]] = add i64 [[TMP32]], 1
|
|
// CHECK16-NEXT: store i64 [[ADD48]], i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !10
|
|
// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND30]], !llvm.loop [[LOOP11:![0-9]+]]
|
|
// CHECK16: omp.inner.for.end49:
|
|
// CHECK16-NEXT: store i64 400, i64* [[IT]], align 8
|
|
// CHECK16-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTLINEAR_START25]], align 4
|
|
// CHECK16-NEXT: [[CONV50:%.*]] = sext i32 [[TMP33]] to i64
|
|
// CHECK16-NEXT: [[TMP34:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
|
|
// CHECK16-NEXT: [[MUL51:%.*]] = mul i64 4, [[TMP34]]
|
|
// CHECK16-NEXT: [[ADD52:%.*]] = add i64 [[CONV50]], [[MUL51]]
|
|
// CHECK16-NEXT: [[CONV53:%.*]] = trunc i64 [[ADD52]] to i32
|
|
// CHECK16-NEXT: store i32 [[CONV53]], i32* [[LIN]], align 4
|
|
// CHECK16-NEXT: [[TMP35:%.*]] = load i32, i32* [[DOTLINEAR_START26]], align 4
|
|
// CHECK16-NEXT: [[CONV54:%.*]] = sext i32 [[TMP35]] to i64
|
|
// CHECK16-NEXT: [[TMP36:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
|
|
// CHECK16-NEXT: [[MUL55:%.*]] = mul i64 4, [[TMP36]]
|
|
// CHECK16-NEXT: [[ADD56:%.*]] = add i64 [[CONV54]], [[MUL55]]
|
|
// CHECK16-NEXT: [[CONV57:%.*]] = trunc i64 [[ADD56]] to i32
|
|
// CHECK16-NEXT: store i32 [[CONV57]], i32* [[A]], align 4
|
|
// CHECK16-NEXT: store i32 0, i32* [[DOTOMP_LB59]], align 4
|
|
// CHECK16-NEXT: store i32 3, i32* [[DOTOMP_UB60]], align 4
|
|
// CHECK16-NEXT: [[TMP37:%.*]] = load i32, i32* [[DOTOMP_LB59]], align 4
|
|
// CHECK16-NEXT: store i32 [[TMP37]], i32* [[DOTOMP_IV61]], align 4
|
|
// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND63:%.*]]
|
|
// CHECK16: omp.inner.for.cond63:
|
|
// CHECK16-NEXT: [[TMP38:%.*]] = load i32, i32* [[DOTOMP_IV61]], align 4, !llvm.access.group !13
|
|
// CHECK16-NEXT: [[TMP39:%.*]] = load i32, i32* [[DOTOMP_UB60]], align 4, !llvm.access.group !13
|
|
// CHECK16-NEXT: [[CMP64:%.*]] = icmp sle i32 [[TMP38]], [[TMP39]]
|
|
// CHECK16-NEXT: br i1 [[CMP64]], label [[OMP_INNER_FOR_BODY65:%.*]], label [[OMP_INNER_FOR_END76:%.*]]
|
|
// CHECK16: omp.inner.for.body65:
|
|
// CHECK16-NEXT: [[TMP40:%.*]] = load i32, i32* [[DOTOMP_IV61]], align 4, !llvm.access.group !13
|
|
// CHECK16-NEXT: [[MUL66:%.*]] = mul nsw i32 [[TMP40]], 4
|
|
// CHECK16-NEXT: [[ADD67:%.*]] = add nsw i32 6, [[MUL66]]
|
|
// CHECK16-NEXT: [[CONV68:%.*]] = trunc i32 [[ADD67]] to i16
|
|
// CHECK16-NEXT: store i16 [[CONV68]], i16* [[IT62]], align 2, !llvm.access.group !13
|
|
// CHECK16-NEXT: [[TMP41:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !13
|
|
// CHECK16-NEXT: [[ADD69:%.*]] = add nsw i32 [[TMP41]], 1
|
|
// CHECK16-NEXT: store i32 [[ADD69]], i32* [[A]], align 4, !llvm.access.group !13
|
|
// CHECK16-NEXT: [[TMP42:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !13
|
|
// CHECK16-NEXT: [[CONV70:%.*]] = sext i16 [[TMP42]] to i32
|
|
// CHECK16-NEXT: [[ADD71:%.*]] = add nsw i32 [[CONV70]], 1
|
|
// CHECK16-NEXT: [[CONV72:%.*]] = trunc i32 [[ADD71]] to i16
|
|
// CHECK16-NEXT: store i16 [[CONV72]], i16* [[AA]], align 2, !llvm.access.group !13
|
|
// CHECK16-NEXT: br label [[OMP_BODY_CONTINUE73:%.*]]
|
|
// CHECK16: omp.body.continue73:
|
|
// CHECK16-NEXT: br label [[OMP_INNER_FOR_INC74:%.*]]
|
|
// CHECK16: omp.inner.for.inc74:
|
|
// CHECK16-NEXT: [[TMP43:%.*]] = load i32, i32* [[DOTOMP_IV61]], align 4, !llvm.access.group !13
|
|
// CHECK16-NEXT: [[ADD75:%.*]] = add nsw i32 [[TMP43]], 1
|
|
// CHECK16-NEXT: store i32 [[ADD75]], i32* [[DOTOMP_IV61]], align 4, !llvm.access.group !13
|
|
// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND63]], !llvm.loop [[LOOP14:![0-9]+]]
|
|
// CHECK16: omp.inner.for.end76:
|
|
// CHECK16-NEXT: store i16 22, i16* [[IT62]], align 2
|
|
// CHECK16-NEXT: [[TMP44:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK16-NEXT: store i32 [[TMP44]], i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK16-NEXT: store i32 0, i32* [[DOTOMP_LB78]], align 4
|
|
// CHECK16-NEXT: store i32 25, i32* [[DOTOMP_UB79]], align 4
|
|
// CHECK16-NEXT: [[TMP45:%.*]] = load i32, i32* [[DOTOMP_LB78]], align 4
|
|
// CHECK16-NEXT: store i32 [[TMP45]], i32* [[DOTOMP_IV80]], align 4
|
|
// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND82:%.*]]
|
|
// CHECK16: omp.inner.for.cond82:
|
|
// CHECK16-NEXT: [[TMP46:%.*]] = load i32, i32* [[DOTOMP_IV80]], align 4, !llvm.access.group !16
|
|
// CHECK16-NEXT: [[TMP47:%.*]] = load i32, i32* [[DOTOMP_UB79]], align 4, !llvm.access.group !16
|
|
// CHECK16-NEXT: [[CMP83:%.*]] = icmp sle i32 [[TMP46]], [[TMP47]]
|
|
// CHECK16-NEXT: br i1 [[CMP83]], label [[OMP_INNER_FOR_BODY84:%.*]], label [[OMP_INNER_FOR_END109:%.*]]
|
|
// CHECK16: omp.inner.for.body84:
|
|
// CHECK16-NEXT: [[TMP48:%.*]] = load i32, i32* [[DOTOMP_IV80]], align 4, !llvm.access.group !16
|
|
// CHECK16-NEXT: [[MUL85:%.*]] = mul nsw i32 [[TMP48]], 1
|
|
// CHECK16-NEXT: [[SUB86:%.*]] = sub nsw i32 122, [[MUL85]]
|
|
// CHECK16-NEXT: [[CONV87:%.*]] = trunc i32 [[SUB86]] to i8
|
|
// CHECK16-NEXT: store i8 [[CONV87]], i8* [[IT81]], align 1, !llvm.access.group !16
|
|
// CHECK16-NEXT: [[TMP49:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !16
|
|
// CHECK16-NEXT: [[ADD88:%.*]] = add nsw i32 [[TMP49]], 1
|
|
// CHECK16-NEXT: store i32 [[ADD88]], i32* [[A]], align 4, !llvm.access.group !16
|
|
// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 2
|
|
// CHECK16-NEXT: [[TMP50:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !16
|
|
// CHECK16-NEXT: [[CONV89:%.*]] = fpext float [[TMP50]] to double
|
|
// CHECK16-NEXT: [[ADD90:%.*]] = fadd double [[CONV89]], 1.000000e+00
|
|
// CHECK16-NEXT: [[CONV91:%.*]] = fptrunc double [[ADD90]] to float
|
|
// CHECK16-NEXT: store float [[CONV91]], float* [[ARRAYIDX]], align 4, !llvm.access.group !16
|
|
// CHECK16-NEXT: [[ARRAYIDX92:%.*]] = getelementptr inbounds float, float* [[VLA]], i32 3
|
|
// CHECK16-NEXT: [[TMP51:%.*]] = load float, float* [[ARRAYIDX92]], align 4, !llvm.access.group !16
|
|
// CHECK16-NEXT: [[CONV93:%.*]] = fpext float [[TMP51]] to double
|
|
// CHECK16-NEXT: [[ADD94:%.*]] = fadd double [[CONV93]], 1.000000e+00
|
|
// CHECK16-NEXT: [[CONV95:%.*]] = fptrunc double [[ADD94]] to float
|
|
// CHECK16-NEXT: store float [[CONV95]], float* [[ARRAYIDX92]], align 4, !llvm.access.group !16
|
|
// CHECK16-NEXT: [[ARRAYIDX96:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i32 0, i32 1
|
|
// CHECK16-NEXT: [[ARRAYIDX97:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX96]], i32 0, i32 2
|
|
// CHECK16-NEXT: [[TMP52:%.*]] = load double, double* [[ARRAYIDX97]], align 8, !llvm.access.group !16
|
|
// CHECK16-NEXT: [[ADD98:%.*]] = fadd double [[TMP52]], 1.000000e+00
|
|
// CHECK16-NEXT: store double [[ADD98]], double* [[ARRAYIDX97]], align 8, !llvm.access.group !16
|
|
// CHECK16-NEXT: [[TMP53:%.*]] = mul nsw i32 1, [[TMP2]]
|
|
// CHECK16-NEXT: [[ARRAYIDX99:%.*]] = getelementptr inbounds double, double* [[VLA1]], i32 [[TMP53]]
|
|
// CHECK16-NEXT: [[ARRAYIDX100:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX99]], i32 3
|
|
// CHECK16-NEXT: [[TMP54:%.*]] = load double, double* [[ARRAYIDX100]], align 8, !llvm.access.group !16
|
|
// CHECK16-NEXT: [[ADD101:%.*]] = fadd double [[TMP54]], 1.000000e+00
|
|
// CHECK16-NEXT: store double [[ADD101]], double* [[ARRAYIDX100]], align 8, !llvm.access.group !16
|
|
// CHECK16-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0
|
|
// CHECK16-NEXT: [[TMP55:%.*]] = load i64, i64* [[X]], align 4, !llvm.access.group !16
|
|
// CHECK16-NEXT: [[ADD102:%.*]] = add nsw i64 [[TMP55]], 1
|
|
// CHECK16-NEXT: store i64 [[ADD102]], i64* [[X]], align 4, !llvm.access.group !16
|
|
// CHECK16-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1
|
|
// CHECK16-NEXT: [[TMP56:%.*]] = load i8, i8* [[Y]], align 4, !llvm.access.group !16
|
|
// CHECK16-NEXT: [[CONV103:%.*]] = sext i8 [[TMP56]] to i32
|
|
// CHECK16-NEXT: [[ADD104:%.*]] = add nsw i32 [[CONV103]], 1
|
|
// CHECK16-NEXT: [[CONV105:%.*]] = trunc i32 [[ADD104]] to i8
|
|
// CHECK16-NEXT: store i8 [[CONV105]], i8* [[Y]], align 4, !llvm.access.group !16
|
|
// CHECK16-NEXT: br label [[OMP_BODY_CONTINUE106:%.*]]
|
|
// CHECK16: omp.body.continue106:
|
|
// CHECK16-NEXT: br label [[OMP_INNER_FOR_INC107:%.*]]
|
|
// CHECK16: omp.inner.for.inc107:
|
|
// CHECK16-NEXT: [[TMP57:%.*]] = load i32, i32* [[DOTOMP_IV80]], align 4, !llvm.access.group !16
|
|
// CHECK16-NEXT: [[ADD108:%.*]] = add nsw i32 [[TMP57]], 1
|
|
// CHECK16-NEXT: store i32 [[ADD108]], i32* [[DOTOMP_IV80]], align 4, !llvm.access.group !16
|
|
// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND82]], !llvm.loop [[LOOP17:![0-9]+]]
|
|
// CHECK16: omp.inner.for.end109:
|
|
// CHECK16-NEXT: store i8 96, i8* [[IT81]], align 1
|
|
// CHECK16-NEXT: [[TMP58:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK16-NEXT: [[TMP59:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
|
|
// CHECK16-NEXT: call void @llvm.stackrestore(i8* [[TMP59]])
|
|
// CHECK16-NEXT: ret i32 [[TMP58]]
|
|
//
|
|
//
|
|
// CHECK16-LABEL: define {{[^@]+}}@_Z3bari
|
|
// CHECK16-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
|
|
// CHECK16-NEXT: entry:
|
|
// CHECK16-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK16-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK16-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4
|
|
// CHECK16-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK16-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK16-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]])
|
|
// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
|
|
// CHECK16-NEXT: store i32 [[ADD]], i32* [[A]], align 4
|
|
// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK16-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]])
|
|
// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK16-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
|
|
// CHECK16-NEXT: store i32 [[ADD2]], i32* [[A]], align 4
|
|
// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK16-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]])
|
|
// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK16-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
|
|
// CHECK16-NEXT: store i32 [[ADD4]], i32* [[A]], align 4
|
|
// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK16-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]])
|
|
// CHECK16-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK16-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
|
|
// CHECK16-NEXT: store i32 [[ADD6]], i32* [[A]], align 4
|
|
// CHECK16-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK16-NEXT: ret i32 [[TMP8]]
|
|
//
|
|
//
|
|
// CHECK16-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
|
|
// CHECK16-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 {
|
|
// CHECK16-NEXT: entry:
|
|
// CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
|
|
// CHECK16-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK16-NEXT: [[B:%.*]] = alloca i32, align 4
|
|
// CHECK16-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4
|
|
// CHECK16-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4
|
|
// CHECK16-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
|
|
// CHECK16-NEXT: [[TMP:%.*]] = alloca i64, align 4
|
|
// CHECK16-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
|
|
// CHECK16-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
|
|
// CHECK16-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
|
|
// CHECK16-NEXT: [[IT:%.*]] = alloca i64, align 8
|
|
// CHECK16-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK16-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
|
|
// CHECK16-NEXT: store i32 [[ADD]], i32* [[B]], align 4
|
|
// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK16-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave()
|
|
// CHECK16-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4
|
|
// CHECK16-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]]
|
|
// CHECK16-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2
|
|
// CHECK16-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4
|
|
// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK16-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 60
|
|
// CHECK16-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8
|
|
// CHECK16-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
|
|
// CHECK16-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK16-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK16-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK16-NEXT: store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK16-NEXT: [[TMP6:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
|
|
// CHECK16-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP6]] to i1
|
|
// CHECK16-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
|
|
// CHECK16: omp_if.then:
|
|
// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK16: omp.inner.for.cond:
|
|
// CHECK16-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !19
|
|
// CHECK16-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !19
|
|
// CHECK16-NEXT: [[CMP2:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]]
|
|
// CHECK16-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK16: omp.inner.for.body:
|
|
// CHECK16-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !19
|
|
// CHECK16-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400
|
|
// CHECK16-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]
|
|
// CHECK16-NEXT: store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !19
|
|
// CHECK16-NEXT: [[TMP10:%.*]] = load i32, i32* [[B]], align 4, !llvm.access.group !19
|
|
// CHECK16-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP10]] to double
|
|
// CHECK16-NEXT: [[ADD3:%.*]] = fadd double [[CONV]], 1.500000e+00
|
|
// CHECK16-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
|
|
// CHECK16-NEXT: store double [[ADD3]], double* [[A]], align 4, !nontemporal !20, !llvm.access.group !19
|
|
// CHECK16-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
|
|
// CHECK16-NEXT: [[TMP11:%.*]] = load double, double* [[A4]], align 4, !nontemporal !20, !llvm.access.group !19
|
|
// CHECK16-NEXT: [[INC:%.*]] = fadd double [[TMP11]], 1.000000e+00
|
|
// CHECK16-NEXT: store double [[INC]], double* [[A4]], align 4, !nontemporal !20, !llvm.access.group !19
|
|
// CHECK16-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16
|
|
// CHECK16-NEXT: [[TMP12:%.*]] = mul nsw i32 1, [[TMP1]]
|
|
// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP12]]
|
|
// CHECK16-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
|
|
// CHECK16-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2, !llvm.access.group !19
|
|
// CHECK16-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK16: omp.body.continue:
|
|
// CHECK16-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK16: omp.inner.for.inc:
|
|
// CHECK16-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !19
|
|
// CHECK16-NEXT: [[ADD7:%.*]] = add i64 [[TMP13]], 1
|
|
// CHECK16-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !19
|
|
// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]]
|
|
// CHECK16: omp.inner.for.end:
|
|
// CHECK16-NEXT: br label [[OMP_IF_END:%.*]]
|
|
// CHECK16: omp_if.else:
|
|
// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND8:%.*]]
|
|
// CHECK16: omp.inner.for.cond8:
|
|
// CHECK16-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK16-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK16-NEXT: [[CMP9:%.*]] = icmp ule i64 [[TMP14]], [[TMP15]]
|
|
// CHECK16-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY10:%.*]], label [[OMP_INNER_FOR_END24:%.*]]
|
|
// CHECK16: omp.inner.for.body10:
|
|
// CHECK16-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK16-NEXT: [[MUL11:%.*]] = mul i64 [[TMP16]], 400
|
|
// CHECK16-NEXT: [[SUB12:%.*]] = sub i64 2000, [[MUL11]]
|
|
// CHECK16-NEXT: store i64 [[SUB12]], i64* [[IT]], align 8
|
|
// CHECK16-NEXT: [[TMP17:%.*]] = load i32, i32* [[B]], align 4
|
|
// CHECK16-NEXT: [[CONV13:%.*]] = sitofp i32 [[TMP17]] to double
|
|
// CHECK16-NEXT: [[ADD14:%.*]] = fadd double [[CONV13]], 1.500000e+00
|
|
// CHECK16-NEXT: [[A15:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
|
|
// CHECK16-NEXT: store double [[ADD14]], double* [[A15]], align 4
|
|
// CHECK16-NEXT: [[A16:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
|
|
// CHECK16-NEXT: [[TMP18:%.*]] = load double, double* [[A16]], align 4
|
|
// CHECK16-NEXT: [[INC17:%.*]] = fadd double [[TMP18]], 1.000000e+00
|
|
// CHECK16-NEXT: store double [[INC17]], double* [[A16]], align 4
|
|
// CHECK16-NEXT: [[CONV18:%.*]] = fptosi double [[INC17]] to i16
|
|
// CHECK16-NEXT: [[TMP19:%.*]] = mul nsw i32 1, [[TMP1]]
|
|
// CHECK16-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP19]]
|
|
// CHECK16-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX19]], i32 1
|
|
// CHECK16-NEXT: store i16 [[CONV18]], i16* [[ARRAYIDX20]], align 2
|
|
// CHECK16-NEXT: br label [[OMP_BODY_CONTINUE21:%.*]]
|
|
// CHECK16: omp.body.continue21:
|
|
// CHECK16-NEXT: br label [[OMP_INNER_FOR_INC22:%.*]]
|
|
// CHECK16: omp.inner.for.inc22:
|
|
// CHECK16-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK16-NEXT: [[ADD23:%.*]] = add i64 [[TMP20]], 1
|
|
// CHECK16-NEXT: store i64 [[ADD23]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND8]], !llvm.loop [[LOOP23:![0-9]+]]
|
|
// CHECK16: omp.inner.for.end24:
|
|
// CHECK16-NEXT: br label [[OMP_IF_END]]
|
|
// CHECK16: omp_if.end:
|
|
// CHECK16-NEXT: store i64 400, i64* [[IT]], align 8
|
|
// CHECK16-NEXT: [[TMP21:%.*]] = mul nsw i32 1, [[TMP1]]
|
|
// CHECK16-NEXT: [[ARRAYIDX25:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP21]]
|
|
// CHECK16-NEXT: [[ARRAYIDX26:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX25]], i32 1
|
|
// CHECK16-NEXT: [[TMP22:%.*]] = load i16, i16* [[ARRAYIDX26]], align 2
|
|
// CHECK16-NEXT: [[CONV27:%.*]] = sext i16 [[TMP22]] to i32
|
|
// CHECK16-NEXT: [[TMP23:%.*]] = load i32, i32* [[B]], align 4
|
|
// CHECK16-NEXT: [[ADD28:%.*]] = add nsw i32 [[CONV27]], [[TMP23]]
|
|
// CHECK16-NEXT: [[TMP24:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
|
|
// CHECK16-NEXT: call void @llvm.stackrestore(i8* [[TMP24]])
|
|
// CHECK16-NEXT: ret i32 [[ADD28]]
|
|
//
|
|
//
|
|
// CHECK16-LABEL: define {{[^@]+}}@_ZL7fstatici
|
|
// CHECK16-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
|
|
// CHECK16-NEXT: entry:
|
|
// CHECK16-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK16-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK16-NEXT: [[AA:%.*]] = alloca i16, align 2
|
|
// CHECK16-NEXT: [[AAA:%.*]] = alloca i8, align 1
|
|
// CHECK16-NEXT: [[B:%.*]] = alloca [10 x i32], align 4
|
|
// CHECK16-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK16-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK16-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK16-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK16-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK16-NEXT: store i16 0, i16* [[AA]], align 2
|
|
// CHECK16-NEXT: store i8 0, i8* [[AAA]], align 1
|
|
// CHECK16-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK16-NEXT: store i32 429496720, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK16-NEXT: ret i32 [[TMP0]]
|
|
//
|
|
//
|
|
// CHECK16-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
|
|
// CHECK16-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat {
|
|
// CHECK16-NEXT: entry:
|
|
// CHECK16-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK16-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK16-NEXT: [[AA:%.*]] = alloca i16, align 2
|
|
// CHECK16-NEXT: [[B:%.*]] = alloca [10 x i32], align 4
|
|
// CHECK16-NEXT: [[TMP:%.*]] = alloca i64, align 4
|
|
// CHECK16-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
|
|
// CHECK16-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
|
|
// CHECK16-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
|
|
// CHECK16-NEXT: [[I:%.*]] = alloca i64, align 8
|
|
// CHECK16-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK16-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK16-NEXT: store i16 0, i16* [[AA]], align 2
|
|
// CHECK16-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK16-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK16-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK16-NEXT: store i64 [[TMP0]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK16: omp.inner.for.cond:
|
|
// CHECK16-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !25
|
|
// CHECK16-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !25
|
|
// CHECK16-NEXT: [[CMP:%.*]] = icmp sle i64 [[TMP1]], [[TMP2]]
|
|
// CHECK16-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK16: omp.inner.for.body:
|
|
// CHECK16-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !25
|
|
// CHECK16-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP3]], 3
|
|
// CHECK16-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
|
|
// CHECK16-NEXT: store i64 [[ADD]], i64* [[I]], align 8, !llvm.access.group !25
|
|
// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !25
|
|
// CHECK16-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1
|
|
// CHECK16-NEXT: store i32 [[ADD1]], i32* [[A]], align 4, !llvm.access.group !25
|
|
// CHECK16-NEXT: [[TMP5:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !25
|
|
// CHECK16-NEXT: [[CONV:%.*]] = sext i16 [[TMP5]] to i32
|
|
// CHECK16-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 1
|
|
// CHECK16-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
|
|
// CHECK16-NEXT: store i16 [[CONV3]], i16* [[AA]], align 2, !llvm.access.group !25
|
|
// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2
|
|
// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !25
|
|
// CHECK16-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP6]], 1
|
|
// CHECK16-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !25
|
|
// CHECK16-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK16: omp.body.continue:
|
|
// CHECK16-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK16: omp.inner.for.inc:
|
|
// CHECK16-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !25
|
|
// CHECK16-NEXT: [[ADD5:%.*]] = add nsw i64 [[TMP7]], 1
|
|
// CHECK16-NEXT: store i64 [[ADD5]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !25
|
|
// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP26:![0-9]+]]
|
|
// CHECK16: omp.inner.for.end:
|
|
// CHECK16-NEXT: store i64 11, i64* [[I]], align 8
|
|
// CHECK16-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK16-NEXT: ret i32 [[TMP8]]
|
|
//
|
|
//
|
|
// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96
|
|
// CHECK17-SAME: () #[[ATTR0:[0-9]+]] {
|
|
// CHECK17-NEXT: entry:
|
|
// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
|
|
// CHECK17-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined.
|
|
// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] {
|
|
// CHECK17-NEXT: entry:
|
|
// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK17-NEXT: [[I:%.*]] = alloca i32, align 4
|
|
// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK17-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK17-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
|
|
// CHECK17-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
|
|
// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5
|
|
// CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK17: cond.true:
|
|
// CHECK17-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK17: cond.false:
|
|
// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK17-NEXT: br label [[COND_END]]
|
|
// CHECK17: cond.end:
|
|
// CHECK17-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
|
|
// CHECK17-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK17-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK17: omp.inner.for.cond:
|
|
// CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
|
|
// CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !11
|
|
// CHECK17-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
|
|
// CHECK17-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK17: omp.inner.for.body:
|
|
// CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
|
|
// CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5
|
|
// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]]
|
|
// CHECK17-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11
|
|
// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK17: omp.body.continue:
|
|
// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK17: omp.inner.for.inc:
|
|
// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
|
|
// CHECK17-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
|
|
// CHECK17-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
|
|
// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]
|
|
// CHECK17: omp.inner.for.end:
|
|
// CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK17: omp.loop.exit:
|
|
// CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
|
|
// CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK17-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0
|
|
// CHECK17-NEXT: br i1 [[TMP10]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
|
|
// CHECK17: .omp.final.then:
|
|
// CHECK17-NEXT: store i32 33, i32* [[I]], align 4
|
|
// CHECK17-NEXT: br label [[DOTOMP_FINAL_DONE]]
|
|
// CHECK17: .omp.final.done:
|
|
// CHECK17-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108
|
|
// CHECK17-SAME: (i64 [[AA:%.*]], i64 [[LIN:%.*]], i64 [[A:%.*]]) #[[ATTR0]] {
|
|
// CHECK17-NEXT: entry:
|
|
// CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
|
|
// CHECK17-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8
|
|
// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
|
|
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32*
|
|
// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK17-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8
|
|
// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
|
|
// CHECK17-NEXT: store i16 [[TMP0]], i16* [[CONV3]], align 2
|
|
// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
|
|
// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8
|
|
// CHECK17-NEXT: [[CONV4:%.*]] = bitcast i64* [[LIN_CASTED]] to i32*
|
|
// CHECK17-NEXT: store i32 [[TMP2]], i32* [[CONV4]], align 4
|
|
// CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[LIN_CASTED]], align 8
|
|
// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV2]], align 8
|
|
// CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
|
|
// CHECK17-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4
|
|
// CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[A_CASTED]], align 8
|
|
// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]])
|
|
// CHECK17-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..1
|
|
// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]], i64 [[LIN:%.*]], i64 [[A:%.*]]) #[[ATTR1]] {
|
|
// CHECK17-NEXT: entry:
|
|
// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[TMP:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4
|
|
// CHECK17-NEXT: [[DOTLINEAR_START3:%.*]] = alloca i32, align 4
|
|
// CHECK17-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK17-NEXT: [[IT:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[LIN4:%.*]] = alloca i32, align 4
|
|
// CHECK17-NEXT: [[A5:%.*]] = alloca i32, align 4
|
|
// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
|
|
// CHECK17-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8
|
|
// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
|
|
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32*
|
|
// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV1]], align 8
|
|
// CHECK17-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4
|
|
// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 8
|
|
// CHECK17-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START3]], align 4
|
|
// CHECK17-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() #[[ATTR5:[0-9]+]]
|
|
// CHECK17-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8
|
|
// CHECK17-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK17-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK17-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
|
|
// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK17-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
|
|
// CHECK17-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP3]])
|
|
// CHECK17-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
|
|
// CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK17-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3
|
|
// CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK17: cond.true:
|
|
// CHECK17-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK17: cond.false:
|
|
// CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK17-NEXT: br label [[COND_END]]
|
|
// CHECK17: cond.end:
|
|
// CHECK17-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
|
|
// CHECK17-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
|
|
// CHECK17-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK17-NEXT: store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK17: omp.inner.for.cond:
|
|
// CHECK17-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !17
|
|
// CHECK17-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !17
|
|
// CHECK17-NEXT: [[CMP6:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]]
|
|
// CHECK17-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK17: omp.inner.for.body:
|
|
// CHECK17-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !17
|
|
// CHECK17-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400
|
|
// CHECK17-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]
|
|
// CHECK17-NEXT: store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !17
|
|
// CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4, !llvm.access.group !17
|
|
// CHECK17-NEXT: [[CONV7:%.*]] = sext i32 [[TMP10]] to i64
|
|
// CHECK17-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !17
|
|
// CHECK17-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !17
|
|
// CHECK17-NEXT: [[MUL8:%.*]] = mul i64 [[TMP11]], [[TMP12]]
|
|
// CHECK17-NEXT: [[ADD:%.*]] = add i64 [[CONV7]], [[MUL8]]
|
|
// CHECK17-NEXT: [[CONV9:%.*]] = trunc i64 [[ADD]] to i32
|
|
// CHECK17-NEXT: store i32 [[CONV9]], i32* [[LIN4]], align 4, !llvm.access.group !17
|
|
// CHECK17-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START3]], align 4, !llvm.access.group !17
|
|
// CHECK17-NEXT: [[CONV10:%.*]] = sext i32 [[TMP13]] to i64
|
|
// CHECK17-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !17
|
|
// CHECK17-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !17
|
|
// CHECK17-NEXT: [[MUL11:%.*]] = mul i64 [[TMP14]], [[TMP15]]
|
|
// CHECK17-NEXT: [[ADD12:%.*]] = add i64 [[CONV10]], [[MUL11]]
|
|
// CHECK17-NEXT: [[CONV13:%.*]] = trunc i64 [[ADD12]] to i32
|
|
// CHECK17-NEXT: store i32 [[CONV13]], i32* [[A5]], align 4, !llvm.access.group !17
|
|
// CHECK17-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 8, !llvm.access.group !17
|
|
// CHECK17-NEXT: [[CONV14:%.*]] = sext i16 [[TMP16]] to i32
|
|
// CHECK17-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1
|
|
// CHECK17-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16
|
|
// CHECK17-NEXT: store i16 [[CONV16]], i16* [[CONV]], align 8, !llvm.access.group !17
|
|
// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK17: omp.body.continue:
|
|
// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK17: omp.inner.for.inc:
|
|
// CHECK17-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !17
|
|
// CHECK17-NEXT: [[ADD17:%.*]] = add i64 [[TMP17]], 1
|
|
// CHECK17-NEXT: store i64 [[ADD17]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !17
|
|
// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]]
|
|
// CHECK17: omp.inner.for.end:
|
|
// CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK17: omp.loop.exit:
|
|
// CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
|
|
// CHECK17-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK17-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
|
|
// CHECK17-NEXT: br i1 [[TMP19]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
|
|
// CHECK17: .omp.final.then:
|
|
// CHECK17-NEXT: store i64 400, i64* [[IT]], align 8
|
|
// CHECK17-NEXT: br label [[DOTOMP_FINAL_DONE]]
|
|
// CHECK17: .omp.final.done:
|
|
// CHECK17-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK17-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0
|
|
// CHECK17-NEXT: br i1 [[TMP21]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
|
|
// CHECK17: .omp.linear.pu:
|
|
// CHECK17-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4
|
|
// CHECK17-NEXT: [[CONV18:%.*]] = sext i32 [[TMP22]] to i64
|
|
// CHECK17-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
|
|
// CHECK17-NEXT: [[MUL19:%.*]] = mul i64 4, [[TMP23]]
|
|
// CHECK17-NEXT: [[ADD20:%.*]] = add i64 [[CONV18]], [[MUL19]]
|
|
// CHECK17-NEXT: [[CONV21:%.*]] = trunc i64 [[ADD20]] to i32
|
|
// CHECK17-NEXT: store i32 [[CONV21]], i32* [[CONV1]], align 8
|
|
// CHECK17-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTLINEAR_START3]], align 4
|
|
// CHECK17-NEXT: [[CONV22:%.*]] = sext i32 [[TMP24]] to i64
|
|
// CHECK17-NEXT: [[TMP25:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
|
|
// CHECK17-NEXT: [[MUL23:%.*]] = mul i64 4, [[TMP25]]
|
|
// CHECK17-NEXT: [[ADD24:%.*]] = add i64 [[CONV22]], [[MUL23]]
|
|
// CHECK17-NEXT: [[CONV25:%.*]] = trunc i64 [[ADD24]] to i32
|
|
// CHECK17-NEXT: store i32 [[CONV25]], i32* [[CONV2]], align 8
|
|
// CHECK17-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]]
|
|
// CHECK17: .omp.linear.pu.done:
|
|
// CHECK17-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK17-LABEL: define {{[^@]+}}@_Z7get_valv
|
|
// CHECK17-SAME: () #[[ATTR3:[0-9]+]] {
|
|
// CHECK17-NEXT: entry:
|
|
// CHECK17-NEXT: ret i64 0
|
|
//
|
|
//
|
|
// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116
|
|
// CHECK17-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] {
|
|
// CHECK17-NEXT: entry:
|
|
// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
|
|
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
|
|
// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
|
|
// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
|
|
// CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4
|
|
// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
|
|
// CHECK17-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
|
|
// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
|
|
// CHECK17-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2
|
|
// CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
|
|
// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
|
|
// CHECK17-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..2
|
|
// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR1]] {
|
|
// CHECK17-NEXT: entry:
|
|
// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK17-NEXT: [[TMP:%.*]] = alloca i16, align 2
|
|
// CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK17-NEXT: [[IT:%.*]] = alloca i16, align 2
|
|
// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
|
|
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
|
|
// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK17-NEXT: store i32 3, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK17-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
|
|
// CHECK17-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
|
|
// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3
|
|
// CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK17: cond.true:
|
|
// CHECK17-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK17: cond.false:
|
|
// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK17-NEXT: br label [[COND_END]]
|
|
// CHECK17: cond.end:
|
|
// CHECK17-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
|
|
// CHECK17-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK17-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK17: omp.inner.for.cond:
|
|
// CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20
|
|
// CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !20
|
|
// CHECK17-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
|
|
// CHECK17-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK17: omp.inner.for.body:
|
|
// CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20
|
|
// CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4
|
|
// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]]
|
|
// CHECK17-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD]] to i16
|
|
// CHECK17-NEXT: store i16 [[CONV3]], i16* [[IT]], align 2, !llvm.access.group !20
|
|
// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !20
|
|
// CHECK17-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1
|
|
// CHECK17-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 8, !llvm.access.group !20
|
|
// CHECK17-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 8, !llvm.access.group !20
|
|
// CHECK17-NEXT: [[CONV5:%.*]] = sext i16 [[TMP9]] to i32
|
|
// CHECK17-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1
|
|
// CHECK17-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16
|
|
// CHECK17-NEXT: store i16 [[CONV7]], i16* [[CONV1]], align 8, !llvm.access.group !20
|
|
// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK17: omp.body.continue:
|
|
// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK17: omp.inner.for.inc:
|
|
// CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20
|
|
// CHECK17-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP10]], 1
|
|
// CHECK17-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20
|
|
// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]]
|
|
// CHECK17: omp.inner.for.end:
|
|
// CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK17: omp.loop.exit:
|
|
// CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
|
|
// CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK17-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
|
|
// CHECK17-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
|
|
// CHECK17: .omp.final.then:
|
|
// CHECK17-NEXT: store i16 22, i16* [[IT]], align 2
|
|
// CHECK17-NEXT: br label [[DOTOMP_FINAL_DONE]]
|
|
// CHECK17: .omp.final.done:
|
|
// CHECK17-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140
|
|
// CHECK17-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
|
|
// CHECK17-NEXT: entry:
|
|
// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
|
|
// CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8
|
|
// CHECK17-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
|
|
// CHECK17-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8
|
|
// CHECK17-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
|
|
// CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK17-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
|
|
// CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
|
|
// CHECK17-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8
|
|
// CHECK17-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
|
|
// CHECK17-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
|
|
// CHECK17-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
|
|
// CHECK17-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8
|
|
// CHECK17-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
|
|
// CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
|
|
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK17-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
|
|
// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
|
|
// CHECK17-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
|
|
// CHECK17-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
|
|
// CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
|
|
// CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
|
|
// CHECK17-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
|
|
// CHECK17-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
|
|
// CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
|
|
// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
|
|
// CHECK17-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32*
|
|
// CHECK17-NEXT: store i32 [[TMP8]], i32* [[CONV6]], align 4
|
|
// CHECK17-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
|
|
// CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 8
|
|
// CHECK17-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
|
|
// CHECK17-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4
|
|
// CHECK17-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
|
|
// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]])
|
|
// CHECK17-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..3
|
|
// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
|
|
// CHECK17-NEXT: entry:
|
|
// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
|
|
// CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8
|
|
// CHECK17-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
|
|
// CHECK17-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8
|
|
// CHECK17-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
|
|
// CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK17-NEXT: [[TMP:%.*]] = alloca i8, align 1
|
|
// CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK17-NEXT: [[IT:%.*]] = alloca i8, align 1
|
|
// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK17-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
|
|
// CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
|
|
// CHECK17-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8
|
|
// CHECK17-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
|
|
// CHECK17-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
|
|
// CHECK17-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
|
|
// CHECK17-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8
|
|
// CHECK17-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
|
|
// CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
|
|
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK17-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
|
|
// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
|
|
// CHECK17-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
|
|
// CHECK17-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
|
|
// CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
|
|
// CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
|
|
// CHECK17-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
|
|
// CHECK17-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
|
|
// CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
|
|
// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK17-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 8
|
|
// CHECK17-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
|
|
// CHECK17-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
|
|
// CHECK17-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
|
|
// CHECK17: omp.dispatch.cond:
|
|
// CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25
|
|
// CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK17: cond.true:
|
|
// CHECK17-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK17: cond.false:
|
|
// CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK17-NEXT: br label [[COND_END]]
|
|
// CHECK17: cond.end:
|
|
// CHECK17-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
|
|
// CHECK17-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK17-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK17-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK17-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK17-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK17-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
|
|
// CHECK17-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
|
|
// CHECK17: omp.dispatch.body:
|
|
// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK17: omp.inner.for.cond:
|
|
// CHECK17-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23
|
|
// CHECK17-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !23
|
|
// CHECK17-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
|
|
// CHECK17-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK17: omp.inner.for.body:
|
|
// CHECK17-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23
|
|
// CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
|
|
// CHECK17-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]]
|
|
// CHECK17-NEXT: [[CONV8:%.*]] = trunc i32 [[SUB]] to i8
|
|
// CHECK17-NEXT: store i8 [[CONV8]], i8* [[IT]], align 1, !llvm.access.group !23
|
|
// CHECK17-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !23
|
|
// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1
|
|
// CHECK17-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8, !llvm.access.group !23
|
|
// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
|
|
// CHECK17-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !23
|
|
// CHECK17-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double
|
|
// CHECK17-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00
|
|
// CHECK17-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float
|
|
// CHECK17-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4, !llvm.access.group !23
|
|
// CHECK17-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3
|
|
// CHECK17-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4, !llvm.access.group !23
|
|
// CHECK17-NEXT: [[CONV13:%.*]] = fpext float [[TMP21]] to double
|
|
// CHECK17-NEXT: [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00
|
|
// CHECK17-NEXT: [[CONV15:%.*]] = fptrunc double [[ADD14]] to float
|
|
// CHECK17-NEXT: store float [[CONV15]], float* [[ARRAYIDX12]], align 4, !llvm.access.group !23
|
|
// CHECK17-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1
|
|
// CHECK17-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX16]], i64 0, i64 2
|
|
// CHECK17-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX17]], align 8, !llvm.access.group !23
|
|
// CHECK17-NEXT: [[ADD18:%.*]] = fadd double [[TMP22]], 1.000000e+00
|
|
// CHECK17-NEXT: store double [[ADD18]], double* [[ARRAYIDX17]], align 8, !llvm.access.group !23
|
|
// CHECK17-NEXT: [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]]
|
|
// CHECK17-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP23]]
|
|
// CHECK17-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX19]], i64 3
|
|
// CHECK17-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX20]], align 8, !llvm.access.group !23
|
|
// CHECK17-NEXT: [[ADD21:%.*]] = fadd double [[TMP24]], 1.000000e+00
|
|
// CHECK17-NEXT: store double [[ADD21]], double* [[ARRAYIDX20]], align 8, !llvm.access.group !23
|
|
// CHECK17-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0
|
|
// CHECK17-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 8, !llvm.access.group !23
|
|
// CHECK17-NEXT: [[ADD22:%.*]] = add nsw i64 [[TMP25]], 1
|
|
// CHECK17-NEXT: store i64 [[ADD22]], i64* [[X]], align 8, !llvm.access.group !23
|
|
// CHECK17-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1
|
|
// CHECK17-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 8, !llvm.access.group !23
|
|
// CHECK17-NEXT: [[CONV23:%.*]] = sext i8 [[TMP26]] to i32
|
|
// CHECK17-NEXT: [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1
|
|
// CHECK17-NEXT: [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8
|
|
// CHECK17-NEXT: store i8 [[CONV25]], i8* [[Y]], align 8, !llvm.access.group !23
|
|
// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK17: omp.body.continue:
|
|
// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK17: omp.inner.for.inc:
|
|
// CHECK17-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23
|
|
// CHECK17-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP27]], 1
|
|
// CHECK17-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23
|
|
// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP24:![0-9]+]]
|
|
// CHECK17: omp.inner.for.end:
|
|
// CHECK17-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
|
|
// CHECK17: omp.dispatch.inc:
|
|
// CHECK17-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK17-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK17-NEXT: [[ADD27:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]
|
|
// CHECK17-NEXT: store i32 [[ADD27]], i32* [[DOTOMP_LB]], align 4
|
|
// CHECK17-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK17-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK17-NEXT: [[ADD28:%.*]] = add nsw i32 [[TMP30]], [[TMP31]]
|
|
// CHECK17-NEXT: store i32 [[ADD28]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK17-NEXT: br label [[OMP_DISPATCH_COND]]
|
|
// CHECK17: omp.dispatch.end:
|
|
// CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]])
|
|
// CHECK17-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK17-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0
|
|
// CHECK17-NEXT: br i1 [[TMP33]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
|
|
// CHECK17: .omp.final.then:
|
|
// CHECK17-NEXT: store i8 96, i8* [[IT]], align 1
|
|
// CHECK17-NEXT: br label [[DOTOMP_FINAL_DONE]]
|
|
// CHECK17: .omp.final.done:
|
|
// CHECK17-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195
|
|
// CHECK17-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
|
|
// CHECK17-NEXT: entry:
|
|
// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
|
|
// CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
|
|
// CHECK17-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
|
|
// CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
|
|
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
|
|
// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
|
|
// CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
|
|
// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
|
|
// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
|
|
// CHECK17-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4
|
|
// CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
|
|
// CHECK17-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
|
|
// CHECK17-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
|
|
// CHECK17-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2
|
|
// CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
|
|
// CHECK17-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 8
|
|
// CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
|
|
// CHECK17-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1
|
|
// CHECK17-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
|
|
// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]])
|
|
// CHECK17-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..4
|
|
// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {
|
|
// CHECK17-NEXT: entry:
|
|
// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
|
|
// CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
|
|
// CHECK17-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
|
|
// CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
|
|
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
|
|
// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
|
|
// CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
|
|
// CHECK17-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216
|
|
// CHECK17-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {
|
|
// CHECK17-NEXT: entry:
|
|
// CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
|
|
// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8
|
|
// CHECK17-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK17-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
|
|
// CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
|
|
// CHECK17-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
|
|
// CHECK17-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8
|
|
// CHECK17-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
|
|
// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
|
|
// CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
|
|
// CHECK17-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
|
|
// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
|
|
// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32*
|
|
// CHECK17-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
|
|
// CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
|
|
// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]])
|
|
// CHECK17-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..5
|
|
// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] {
|
|
// CHECK17-NEXT: entry:
|
|
// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
|
|
// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8
|
|
// CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[TMP:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK17-NEXT: [[IT:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK17-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK17-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
|
|
// CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
|
|
// CHECK17-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
|
|
// CHECK17-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8
|
|
// CHECK17-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
|
|
// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
|
|
// CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
|
|
// CHECK17-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
|
|
// CHECK17-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK17-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK17-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
|
|
// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK17-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
|
|
// CHECK17-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
|
|
// CHECK17-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK17-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 3
|
|
// CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK17: cond.true:
|
|
// CHECK17-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK17: cond.false:
|
|
// CHECK17-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK17-NEXT: br label [[COND_END]]
|
|
// CHECK17: cond.end:
|
|
// CHECK17-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
|
|
// CHECK17-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
|
|
// CHECK17-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK17-NEXT: store i64 [[TMP8]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK17: omp.inner.for.cond:
|
|
// CHECK17-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !26
|
|
// CHECK17-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !26
|
|
// CHECK17-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]]
|
|
// CHECK17-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK17: omp.inner.for.body:
|
|
// CHECK17-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !26
|
|
// CHECK17-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400
|
|
// CHECK17-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]
|
|
// CHECK17-NEXT: store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !26
|
|
// CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !26
|
|
// CHECK17-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double
|
|
// CHECK17-NEXT: [[ADD:%.*]] = fadd double [[CONV4]], 1.500000e+00
|
|
// CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
|
|
// CHECK17-NEXT: store double [[ADD]], double* [[A]], align 8, !llvm.access.group !26
|
|
// CHECK17-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
|
|
// CHECK17-NEXT: [[TMP13:%.*]] = load double, double* [[A5]], align 8, !llvm.access.group !26
|
|
// CHECK17-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00
|
|
// CHECK17-NEXT: store double [[INC]], double* [[A5]], align 8, !llvm.access.group !26
|
|
// CHECK17-NEXT: [[CONV6:%.*]] = fptosi double [[INC]] to i16
|
|
// CHECK17-NEXT: [[TMP14:%.*]] = mul nsw i64 1, [[TMP2]]
|
|
// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP14]]
|
|
// CHECK17-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
|
|
// CHECK17-NEXT: store i16 [[CONV6]], i16* [[ARRAYIDX7]], align 2, !llvm.access.group !26
|
|
// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK17: omp.body.continue:
|
|
// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK17: omp.inner.for.inc:
|
|
// CHECK17-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !26
|
|
// CHECK17-NEXT: [[ADD8:%.*]] = add i64 [[TMP15]], 1
|
|
// CHECK17-NEXT: store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !26
|
|
// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP27:![0-9]+]]
|
|
// CHECK17: omp.inner.for.end:
|
|
// CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK17: omp.loop.exit:
|
|
// CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
|
|
// CHECK17-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK17-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0
|
|
// CHECK17-NEXT: br i1 [[TMP17]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
|
|
// CHECK17: .omp.final.then:
|
|
// CHECK17-NEXT: store i64 400, i64* [[IT]], align 8
|
|
// CHECK17-NEXT: br label [[DOTOMP_FINAL_DONE]]
|
|
// CHECK17: .omp.final.done:
|
|
// CHECK17-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178
|
|
// CHECK17-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
|
|
// CHECK17-NEXT: entry:
|
|
// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
|
|
// CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
|
|
// CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
|
|
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
|
|
// CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
|
|
// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
|
|
// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
|
|
// CHECK17-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4
|
|
// CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
|
|
// CHECK17-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
|
|
// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
|
|
// CHECK17-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
|
|
// CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
|
|
// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]])
|
|
// CHECK17-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..6
|
|
// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {
|
|
// CHECK17-NEXT: entry:
|
|
// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
|
|
// CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[TMP:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK17-NEXT: [[I:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
|
|
// CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
|
|
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
|
|
// CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
|
|
// CHECK17-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK17-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK17-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
|
|
// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
|
|
// CHECK17-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
|
|
// CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6
|
|
// CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK17: cond.true:
|
|
// CHECK17-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK17: cond.false:
|
|
// CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK17-NEXT: br label [[COND_END]]
|
|
// CHECK17: cond.end:
|
|
// CHECK17-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
|
|
// CHECK17-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
|
|
// CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK17-NEXT: store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK17: omp.inner.for.cond:
|
|
// CHECK17-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !29
|
|
// CHECK17-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !29
|
|
// CHECK17-NEXT: [[CMP2:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]]
|
|
// CHECK17-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK17: omp.inner.for.body:
|
|
// CHECK17-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !29
|
|
// CHECK17-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3
|
|
// CHECK17-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
|
|
// CHECK17-NEXT: store i64 [[ADD]], i64* [[I]], align 8, !llvm.access.group !29
|
|
// CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !29
|
|
// CHECK17-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1
|
|
// CHECK17-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 8, !llvm.access.group !29
|
|
// CHECK17-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 8, !llvm.access.group !29
|
|
// CHECK17-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32
|
|
// CHECK17-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
|
|
// CHECK17-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
|
|
// CHECK17-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 8, !llvm.access.group !29
|
|
// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
|
|
// CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !29
|
|
// CHECK17-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1
|
|
// CHECK17-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !29
|
|
// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK17: omp.body.continue:
|
|
// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK17: omp.inner.for.inc:
|
|
// CHECK17-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !29
|
|
// CHECK17-NEXT: [[ADD8:%.*]] = add nsw i64 [[TMP12]], 1
|
|
// CHECK17-NEXT: store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !29
|
|
// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP30:![0-9]+]]
|
|
// CHECK17: omp.inner.for.end:
|
|
// CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK17: omp.loop.exit:
|
|
// CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
|
|
// CHECK17-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK17-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
|
|
// CHECK17-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
|
|
// CHECK17: .omp.final.then:
|
|
// CHECK17-NEXT: store i64 11, i64* [[I]], align 8
|
|
// CHECK17-NEXT: br label [[DOTOMP_FINAL_DONE]]
|
|
// CHECK17: .omp.final.done:
|
|
// CHECK17-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96
|
|
// CHECK18-SAME: () #[[ATTR0:[0-9]+]] {
|
|
// CHECK18-NEXT: entry:
|
|
// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
|
|
// CHECK18-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined.
|
|
// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] {
|
|
// CHECK18-NEXT: entry:
|
|
// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK18-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK18-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK18-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK18-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK18-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK18-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK18-NEXT: [[I:%.*]] = alloca i32, align 4
|
|
// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK18-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK18-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
|
|
// CHECK18-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
|
|
// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK18-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5
|
|
// CHECK18-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK18: cond.true:
|
|
// CHECK18-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK18: cond.false:
|
|
// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK18-NEXT: br label [[COND_END]]
|
|
// CHECK18: cond.end:
|
|
// CHECK18-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
|
|
// CHECK18-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK18-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK18: omp.inner.for.cond:
|
|
// CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
|
|
// CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !11
|
|
// CHECK18-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
|
|
// CHECK18-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK18: omp.inner.for.body:
|
|
// CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
|
|
// CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5
|
|
// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]]
|
|
// CHECK18-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11
|
|
// CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK18: omp.body.continue:
|
|
// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK18: omp.inner.for.inc:
|
|
// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
|
|
// CHECK18-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
|
|
// CHECK18-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
|
|
// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]
|
|
// CHECK18: omp.inner.for.end:
|
|
// CHECK18-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK18: omp.loop.exit:
|
|
// CHECK18-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
|
|
// CHECK18-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK18-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0
|
|
// CHECK18-NEXT: br i1 [[TMP10]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
|
|
// CHECK18: .omp.final.then:
|
|
// CHECK18-NEXT: store i32 33, i32* [[I]], align 4
|
|
// CHECK18-NEXT: br label [[DOTOMP_FINAL_DONE]]
|
|
// CHECK18: .omp.final.done:
|
|
// CHECK18-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108
|
|
// CHECK18-SAME: (i64 [[AA:%.*]], i64 [[LIN:%.*]], i64 [[A:%.*]]) #[[ATTR0]] {
|
|
// CHECK18-NEXT: entry:
|
|
// CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
|
|
// CHECK18-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8
|
|
// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
|
|
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32*
|
|
// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK18-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8
|
|
// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
|
|
// CHECK18-NEXT: store i16 [[TMP0]], i16* [[CONV3]], align 2
|
|
// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
|
|
// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8
|
|
// CHECK18-NEXT: [[CONV4:%.*]] = bitcast i64* [[LIN_CASTED]] to i32*
|
|
// CHECK18-NEXT: store i32 [[TMP2]], i32* [[CONV4]], align 4
|
|
// CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[LIN_CASTED]], align 8
|
|
// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV2]], align 8
|
|
// CHECK18-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
|
|
// CHECK18-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4
|
|
// CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[A_CASTED]], align 8
|
|
// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]])
|
|
// CHECK18-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..1
|
|
// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]], i64 [[LIN:%.*]], i64 [[A:%.*]]) #[[ATTR1]] {
|
|
// CHECK18-NEXT: entry:
|
|
// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[TMP:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4
|
|
// CHECK18-NEXT: [[DOTLINEAR_START3:%.*]] = alloca i32, align 4
|
|
// CHECK18-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK18-NEXT: [[IT:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[LIN4:%.*]] = alloca i32, align 4
|
|
// CHECK18-NEXT: [[A5:%.*]] = alloca i32, align 4
|
|
// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
|
|
// CHECK18-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8
|
|
// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
|
|
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32*
|
|
// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV1]], align 8
|
|
// CHECK18-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4
|
|
// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 8
|
|
// CHECK18-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START3]], align 4
|
|
// CHECK18-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() #[[ATTR5:[0-9]+]]
|
|
// CHECK18-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8
|
|
// CHECK18-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK18-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK18-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
|
|
// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK18-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
|
|
// CHECK18-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP3]])
|
|
// CHECK18-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
|
|
// CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK18-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3
|
|
// CHECK18-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK18: cond.true:
|
|
// CHECK18-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK18: cond.false:
|
|
// CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK18-NEXT: br label [[COND_END]]
|
|
// CHECK18: cond.end:
|
|
// CHECK18-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
|
|
// CHECK18-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
|
|
// CHECK18-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK18-NEXT: store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK18: omp.inner.for.cond:
|
|
// CHECK18-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !17
|
|
// CHECK18-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !17
|
|
// CHECK18-NEXT: [[CMP6:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]]
|
|
// CHECK18-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK18: omp.inner.for.body:
|
|
// CHECK18-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !17
|
|
// CHECK18-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400
|
|
// CHECK18-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]
|
|
// CHECK18-NEXT: store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !17
|
|
// CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4, !llvm.access.group !17
|
|
// CHECK18-NEXT: [[CONV7:%.*]] = sext i32 [[TMP10]] to i64
|
|
// CHECK18-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !17
|
|
// CHECK18-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !17
|
|
// CHECK18-NEXT: [[MUL8:%.*]] = mul i64 [[TMP11]], [[TMP12]]
|
|
// CHECK18-NEXT: [[ADD:%.*]] = add i64 [[CONV7]], [[MUL8]]
|
|
// CHECK18-NEXT: [[CONV9:%.*]] = trunc i64 [[ADD]] to i32
|
|
// CHECK18-NEXT: store i32 [[CONV9]], i32* [[LIN4]], align 4, !llvm.access.group !17
|
|
// CHECK18-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START3]], align 4, !llvm.access.group !17
|
|
// CHECK18-NEXT: [[CONV10:%.*]] = sext i32 [[TMP13]] to i64
|
|
// CHECK18-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !17
|
|
// CHECK18-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !17
|
|
// CHECK18-NEXT: [[MUL11:%.*]] = mul i64 [[TMP14]], [[TMP15]]
|
|
// CHECK18-NEXT: [[ADD12:%.*]] = add i64 [[CONV10]], [[MUL11]]
|
|
// CHECK18-NEXT: [[CONV13:%.*]] = trunc i64 [[ADD12]] to i32
|
|
// CHECK18-NEXT: store i32 [[CONV13]], i32* [[A5]], align 4, !llvm.access.group !17
|
|
// CHECK18-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 8, !llvm.access.group !17
|
|
// CHECK18-NEXT: [[CONV14:%.*]] = sext i16 [[TMP16]] to i32
|
|
// CHECK18-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1
|
|
// CHECK18-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16
|
|
// CHECK18-NEXT: store i16 [[CONV16]], i16* [[CONV]], align 8, !llvm.access.group !17
|
|
// CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK18: omp.body.continue:
|
|
// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK18: omp.inner.for.inc:
|
|
// CHECK18-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !17
|
|
// CHECK18-NEXT: [[ADD17:%.*]] = add i64 [[TMP17]], 1
|
|
// CHECK18-NEXT: store i64 [[ADD17]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !17
|
|
// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]]
|
|
// CHECK18: omp.inner.for.end:
|
|
// CHECK18-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK18: omp.loop.exit:
|
|
// CHECK18-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
|
|
// CHECK18-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK18-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
|
|
// CHECK18-NEXT: br i1 [[TMP19]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
|
|
// CHECK18: .omp.final.then:
|
|
// CHECK18-NEXT: store i64 400, i64* [[IT]], align 8
|
|
// CHECK18-NEXT: br label [[DOTOMP_FINAL_DONE]]
|
|
// CHECK18: .omp.final.done:
|
|
// CHECK18-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK18-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0
|
|
// CHECK18-NEXT: br i1 [[TMP21]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
|
|
// CHECK18: .omp.linear.pu:
|
|
// CHECK18-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4
|
|
// CHECK18-NEXT: [[CONV18:%.*]] = sext i32 [[TMP22]] to i64
|
|
// CHECK18-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
|
|
// CHECK18-NEXT: [[MUL19:%.*]] = mul i64 4, [[TMP23]]
|
|
// CHECK18-NEXT: [[ADD20:%.*]] = add i64 [[CONV18]], [[MUL19]]
|
|
// CHECK18-NEXT: [[CONV21:%.*]] = trunc i64 [[ADD20]] to i32
|
|
// CHECK18-NEXT: store i32 [[CONV21]], i32* [[CONV1]], align 8
|
|
// CHECK18-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTLINEAR_START3]], align 4
|
|
// CHECK18-NEXT: [[CONV22:%.*]] = sext i32 [[TMP24]] to i64
|
|
// CHECK18-NEXT: [[TMP25:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
|
|
// CHECK18-NEXT: [[MUL23:%.*]] = mul i64 4, [[TMP25]]
|
|
// CHECK18-NEXT: [[ADD24:%.*]] = add i64 [[CONV22]], [[MUL23]]
|
|
// CHECK18-NEXT: [[CONV25:%.*]] = trunc i64 [[ADD24]] to i32
|
|
// CHECK18-NEXT: store i32 [[CONV25]], i32* [[CONV2]], align 8
|
|
// CHECK18-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]]
|
|
// CHECK18: .omp.linear.pu.done:
|
|
// CHECK18-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK18-LABEL: define {{[^@]+}}@_Z7get_valv
|
|
// CHECK18-SAME: () #[[ATTR3:[0-9]+]] {
|
|
// CHECK18-NEXT: entry:
|
|
// CHECK18-NEXT: ret i64 0
|
|
//
|
|
//
|
|
// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116
|
|
// CHECK18-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] {
|
|
// CHECK18-NEXT: entry:
|
|
// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
|
|
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
|
|
// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
|
|
// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
|
|
// CHECK18-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4
|
|
// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
|
|
// CHECK18-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
|
|
// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
|
|
// CHECK18-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2
|
|
// CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
|
|
// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
|
|
// CHECK18-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..2
|
|
// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR1]] {
|
|
// CHECK18-NEXT: entry:
|
|
// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK18-NEXT: [[TMP:%.*]] = alloca i16, align 2
|
|
// CHECK18-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK18-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK18-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK18-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK18-NEXT: [[IT:%.*]] = alloca i16, align 2
|
|
// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
|
|
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
|
|
// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK18-NEXT: store i32 3, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK18-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
|
|
// CHECK18-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
|
|
// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK18-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3
|
|
// CHECK18-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK18: cond.true:
|
|
// CHECK18-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK18: cond.false:
|
|
// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK18-NEXT: br label [[COND_END]]
|
|
// CHECK18: cond.end:
|
|
// CHECK18-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
|
|
// CHECK18-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK18-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK18: omp.inner.for.cond:
|
|
// CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20
|
|
// CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !20
|
|
// CHECK18-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
|
|
// CHECK18-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK18: omp.inner.for.body:
|
|
// CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20
|
|
// CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4
|
|
// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]]
|
|
// CHECK18-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD]] to i16
|
|
// CHECK18-NEXT: store i16 [[CONV3]], i16* [[IT]], align 2, !llvm.access.group !20
|
|
// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !20
|
|
// CHECK18-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1
|
|
// CHECK18-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 8, !llvm.access.group !20
|
|
// CHECK18-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 8, !llvm.access.group !20
|
|
// CHECK18-NEXT: [[CONV5:%.*]] = sext i16 [[TMP9]] to i32
|
|
// CHECK18-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1
|
|
// CHECK18-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16
|
|
// CHECK18-NEXT: store i16 [[CONV7]], i16* [[CONV1]], align 8, !llvm.access.group !20
|
|
// CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK18: omp.body.continue:
|
|
// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK18: omp.inner.for.inc:
|
|
// CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20
|
|
// CHECK18-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP10]], 1
|
|
// CHECK18-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20
|
|
// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]]
|
|
// CHECK18: omp.inner.for.end:
|
|
// CHECK18-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK18: omp.loop.exit:
|
|
// CHECK18-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
|
|
// CHECK18-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK18-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
|
|
// CHECK18-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
|
|
// CHECK18: .omp.final.then:
|
|
// CHECK18-NEXT: store i16 22, i16* [[IT]], align 2
|
|
// CHECK18-NEXT: br label [[DOTOMP_FINAL_DONE]]
|
|
// CHECK18: .omp.final.done:
|
|
// CHECK18-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140
|
|
// CHECK18-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
|
|
// CHECK18-NEXT: entry:
|
|
// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
|
|
// CHECK18-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8
|
|
// CHECK18-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
|
|
// CHECK18-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8
|
|
// CHECK18-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
|
|
// CHECK18-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK18-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
|
|
// CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
|
|
// CHECK18-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8
|
|
// CHECK18-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
|
|
// CHECK18-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
|
|
// CHECK18-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
|
|
// CHECK18-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8
|
|
// CHECK18-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
|
|
// CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
|
|
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK18-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
|
|
// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
|
|
// CHECK18-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
|
|
// CHECK18-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
|
|
// CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
|
|
// CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
|
|
// CHECK18-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
|
|
// CHECK18-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
|
|
// CHECK18-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
|
|
// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
|
|
// CHECK18-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32*
|
|
// CHECK18-NEXT: store i32 [[TMP8]], i32* [[CONV6]], align 4
|
|
// CHECK18-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
|
|
// CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 8
|
|
// CHECK18-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
|
|
// CHECK18-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4
|
|
// CHECK18-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
|
|
// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]])
|
|
// CHECK18-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..3
|
|
// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
|
|
// CHECK18-NEXT: entry:
|
|
// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
|
|
// CHECK18-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8
|
|
// CHECK18-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
|
|
// CHECK18-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8
|
|
// CHECK18-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
|
|
// CHECK18-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK18-NEXT: [[TMP:%.*]] = alloca i8, align 1
|
|
// CHECK18-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK18-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK18-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK18-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK18-NEXT: [[IT:%.*]] = alloca i8, align 1
|
|
// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK18-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
|
|
// CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
|
|
// CHECK18-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8
|
|
// CHECK18-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
|
|
// CHECK18-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
|
|
// CHECK18-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
|
|
// CHECK18-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8
|
|
// CHECK18-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
|
|
// CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
|
|
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK18-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
|
|
// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
|
|
// CHECK18-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
|
|
// CHECK18-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
|
|
// CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
|
|
// CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
|
|
// CHECK18-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
|
|
// CHECK18-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
|
|
// CHECK18-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
|
|
// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK18-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 8
|
|
// CHECK18-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
|
|
// CHECK18-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
|
|
// CHECK18-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
|
|
// CHECK18: omp.dispatch.cond:
|
|
// CHECK18-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK18-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25
|
|
// CHECK18-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK18: cond.true:
|
|
// CHECK18-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK18: cond.false:
|
|
// CHECK18-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK18-NEXT: br label [[COND_END]]
|
|
// CHECK18: cond.end:
|
|
// CHECK18-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
|
|
// CHECK18-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK18-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK18-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK18-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK18-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK18-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
|
|
// CHECK18-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
|
|
// CHECK18: omp.dispatch.body:
|
|
// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK18: omp.inner.for.cond:
|
|
// CHECK18-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23
|
|
// CHECK18-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !23
|
|
// CHECK18-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
|
|
// CHECK18-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK18: omp.inner.for.body:
|
|
// CHECK18-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23
|
|
// CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
|
|
// CHECK18-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]]
|
|
// CHECK18-NEXT: [[CONV8:%.*]] = trunc i32 [[SUB]] to i8
|
|
// CHECK18-NEXT: store i8 [[CONV8]], i8* [[IT]], align 1, !llvm.access.group !23
|
|
// CHECK18-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !23
|
|
// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1
|
|
// CHECK18-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8, !llvm.access.group !23
|
|
// CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
|
|
// CHECK18-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !23
|
|
// CHECK18-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double
|
|
// CHECK18-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00
|
|
// CHECK18-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float
|
|
// CHECK18-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4, !llvm.access.group !23
|
|
// CHECK18-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3
|
|
// CHECK18-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4, !llvm.access.group !23
|
|
// CHECK18-NEXT: [[CONV13:%.*]] = fpext float [[TMP21]] to double
|
|
// CHECK18-NEXT: [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00
|
|
// CHECK18-NEXT: [[CONV15:%.*]] = fptrunc double [[ADD14]] to float
|
|
// CHECK18-NEXT: store float [[CONV15]], float* [[ARRAYIDX12]], align 4, !llvm.access.group !23
|
|
// CHECK18-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1
|
|
// CHECK18-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX16]], i64 0, i64 2
|
|
// CHECK18-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX17]], align 8, !llvm.access.group !23
|
|
// CHECK18-NEXT: [[ADD18:%.*]] = fadd double [[TMP22]], 1.000000e+00
|
|
// CHECK18-NEXT: store double [[ADD18]], double* [[ARRAYIDX17]], align 8, !llvm.access.group !23
|
|
// CHECK18-NEXT: [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]]
|
|
// CHECK18-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP23]]
|
|
// CHECK18-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX19]], i64 3
|
|
// CHECK18-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX20]], align 8, !llvm.access.group !23
|
|
// CHECK18-NEXT: [[ADD21:%.*]] = fadd double [[TMP24]], 1.000000e+00
|
|
// CHECK18-NEXT: store double [[ADD21]], double* [[ARRAYIDX20]], align 8, !llvm.access.group !23
|
|
// CHECK18-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0
|
|
// CHECK18-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 8, !llvm.access.group !23
|
|
// CHECK18-NEXT: [[ADD22:%.*]] = add nsw i64 [[TMP25]], 1
|
|
// CHECK18-NEXT: store i64 [[ADD22]], i64* [[X]], align 8, !llvm.access.group !23
|
|
// CHECK18-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1
|
|
// CHECK18-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 8, !llvm.access.group !23
|
|
// CHECK18-NEXT: [[CONV23:%.*]] = sext i8 [[TMP26]] to i32
|
|
// CHECK18-NEXT: [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1
|
|
// CHECK18-NEXT: [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8
|
|
// CHECK18-NEXT: store i8 [[CONV25]], i8* [[Y]], align 8, !llvm.access.group !23
|
|
// CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK18: omp.body.continue:
|
|
// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK18: omp.inner.for.inc:
|
|
// CHECK18-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23
|
|
// CHECK18-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP27]], 1
|
|
// CHECK18-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23
|
|
// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP24:![0-9]+]]
|
|
// CHECK18: omp.inner.for.end:
|
|
// CHECK18-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
|
|
// CHECK18: omp.dispatch.inc:
|
|
// CHECK18-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK18-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK18-NEXT: [[ADD27:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]
|
|
// CHECK18-NEXT: store i32 [[ADD27]], i32* [[DOTOMP_LB]], align 4
|
|
// CHECK18-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK18-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK18-NEXT: [[ADD28:%.*]] = add nsw i32 [[TMP30]], [[TMP31]]
|
|
// CHECK18-NEXT: store i32 [[ADD28]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK18-NEXT: br label [[OMP_DISPATCH_COND]]
|
|
// CHECK18: omp.dispatch.end:
|
|
// CHECK18-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]])
|
|
// CHECK18-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK18-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0
|
|
// CHECK18-NEXT: br i1 [[TMP33]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
|
|
// CHECK18: .omp.final.then:
|
|
// CHECK18-NEXT: store i8 96, i8* [[IT]], align 1
|
|
// CHECK18-NEXT: br label [[DOTOMP_FINAL_DONE]]
|
|
// CHECK18: .omp.final.done:
|
|
// CHECK18-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195
|
|
// CHECK18-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
|
|
// CHECK18-NEXT: entry:
|
|
// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
|
|
// CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
|
|
// CHECK18-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
|
|
// CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
|
|
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
|
|
// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
|
|
// CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
|
|
// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
|
|
// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
|
|
// CHECK18-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4
|
|
// CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
|
|
// CHECK18-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
|
|
// CHECK18-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
|
|
// CHECK18-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2
|
|
// CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
|
|
// CHECK18-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 8
|
|
// CHECK18-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
|
|
// CHECK18-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1
|
|
// CHECK18-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
|
|
// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]])
|
|
// CHECK18-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..4
|
|
// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {
|
|
// CHECK18-NEXT: entry:
|
|
// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
|
|
// CHECK18-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK18-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
|
|
// CHECK18-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
|
|
// CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
|
|
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
|
|
// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
|
|
// CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
|
|
// CHECK18-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216
|
|
// CHECK18-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {
|
|
// CHECK18-NEXT: entry:
|
|
// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
|
|
// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8
|
|
// CHECK18-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK18-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
|
|
// CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
|
|
// CHECK18-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
|
|
// CHECK18-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8
|
|
// CHECK18-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
|
|
// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
|
|
// CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
|
|
// CHECK18-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
|
|
// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
|
|
// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32*
|
|
// CHECK18-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
|
|
// CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
|
|
// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]])
|
|
// CHECK18-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..5
|
|
// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] {
|
|
// CHECK18-NEXT: entry:
|
|
// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
|
|
// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8
|
|
// CHECK18-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[TMP:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK18-NEXT: [[IT:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK18-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK18-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
|
|
// CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
|
|
// CHECK18-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
|
|
// CHECK18-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8
|
|
// CHECK18-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
|
|
// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
|
|
// CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
|
|
// CHECK18-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
|
|
// CHECK18-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK18-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK18-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
|
|
// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK18-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
|
|
// CHECK18-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
|
|
// CHECK18-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK18-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 3
|
|
// CHECK18-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK18: cond.true:
|
|
// CHECK18-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK18: cond.false:
|
|
// CHECK18-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK18-NEXT: br label [[COND_END]]
|
|
// CHECK18: cond.end:
|
|
// CHECK18-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
|
|
// CHECK18-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
|
|
// CHECK18-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK18-NEXT: store i64 [[TMP8]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK18: omp.inner.for.cond:
|
|
// CHECK18-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !26
|
|
// CHECK18-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !26
|
|
// CHECK18-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]]
|
|
// CHECK18-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK18: omp.inner.for.body:
|
|
// CHECK18-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !26
|
|
// CHECK18-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400
|
|
// CHECK18-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]
|
|
// CHECK18-NEXT: store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !26
|
|
// CHECK18-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !26
|
|
// CHECK18-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double
|
|
// CHECK18-NEXT: [[ADD:%.*]] = fadd double [[CONV4]], 1.500000e+00
|
|
// CHECK18-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
|
|
// CHECK18-NEXT: store double [[ADD]], double* [[A]], align 8, !llvm.access.group !26
|
|
// CHECK18-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
|
|
// CHECK18-NEXT: [[TMP13:%.*]] = load double, double* [[A5]], align 8, !llvm.access.group !26
|
|
// CHECK18-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00
|
|
// CHECK18-NEXT: store double [[INC]], double* [[A5]], align 8, !llvm.access.group !26
|
|
// CHECK18-NEXT: [[CONV6:%.*]] = fptosi double [[INC]] to i16
|
|
// CHECK18-NEXT: [[TMP14:%.*]] = mul nsw i64 1, [[TMP2]]
|
|
// CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP14]]
|
|
// CHECK18-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
|
|
// CHECK18-NEXT: store i16 [[CONV6]], i16* [[ARRAYIDX7]], align 2, !llvm.access.group !26
|
|
// CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK18: omp.body.continue:
|
|
// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK18: omp.inner.for.inc:
|
|
// CHECK18-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !26
|
|
// CHECK18-NEXT: [[ADD8:%.*]] = add i64 [[TMP15]], 1
|
|
// CHECK18-NEXT: store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !26
|
|
// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP27:![0-9]+]]
|
|
// CHECK18: omp.inner.for.end:
|
|
// CHECK18-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK18: omp.loop.exit:
|
|
// CHECK18-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
|
|
// CHECK18-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK18-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0
|
|
// CHECK18-NEXT: br i1 [[TMP17]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
|
|
// CHECK18: .omp.final.then:
|
|
// CHECK18-NEXT: store i64 400, i64* [[IT]], align 8
|
|
// CHECK18-NEXT: br label [[DOTOMP_FINAL_DONE]]
|
|
// CHECK18: .omp.final.done:
|
|
// CHECK18-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178
|
|
// CHECK18-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
|
|
// CHECK18-NEXT: entry:
|
|
// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
|
|
// CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
|
|
// CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
|
|
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
|
|
// CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
|
|
// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
|
|
// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
|
|
// CHECK18-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4
|
|
// CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
|
|
// CHECK18-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
|
|
// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
|
|
// CHECK18-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
|
|
// CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
|
|
// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]])
|
|
// CHECK18-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..6
|
|
// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {
|
|
// CHECK18-NEXT: entry:
|
|
// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
|
|
// CHECK18-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[TMP:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK18-NEXT: [[I:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
|
|
// CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
|
|
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
|
|
// CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
|
|
// CHECK18-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK18-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK18-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
|
|
// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK18-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
|
|
// CHECK18-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
|
|
// CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK18-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6
|
|
// CHECK18-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK18: cond.true:
|
|
// CHECK18-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK18: cond.false:
|
|
// CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK18-NEXT: br label [[COND_END]]
|
|
// CHECK18: cond.end:
|
|
// CHECK18-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
|
|
// CHECK18-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
|
|
// CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK18-NEXT: store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK18: omp.inner.for.cond:
|
|
// CHECK18-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !29
|
|
// CHECK18-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !29
|
|
// CHECK18-NEXT: [[CMP2:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]]
|
|
// CHECK18-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK18: omp.inner.for.body:
|
|
// CHECK18-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !29
|
|
// CHECK18-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3
|
|
// CHECK18-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
|
|
// CHECK18-NEXT: store i64 [[ADD]], i64* [[I]], align 8, !llvm.access.group !29
|
|
// CHECK18-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !29
|
|
// CHECK18-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1
|
|
// CHECK18-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 8, !llvm.access.group !29
|
|
// CHECK18-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 8, !llvm.access.group !29
|
|
// CHECK18-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32
|
|
// CHECK18-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
|
|
// CHECK18-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
|
|
// CHECK18-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 8, !llvm.access.group !29
|
|
// CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
|
|
// CHECK18-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !29
|
|
// CHECK18-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1
|
|
// CHECK18-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !29
|
|
// CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK18: omp.body.continue:
|
|
// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK18: omp.inner.for.inc:
|
|
// CHECK18-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !29
|
|
// CHECK18-NEXT: [[ADD8:%.*]] = add nsw i64 [[TMP12]], 1
|
|
// CHECK18-NEXT: store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !29
|
|
// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP30:![0-9]+]]
|
|
// CHECK18: omp.inner.for.end:
|
|
// CHECK18-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK18: omp.loop.exit:
|
|
// CHECK18-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
|
|
// CHECK18-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK18-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
|
|
// CHECK18-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
|
|
// CHECK18: .omp.final.then:
|
|
// CHECK18-NEXT: store i64 11, i64* [[I]], align 8
|
|
// CHECK18-NEXT: br label [[DOTOMP_FINAL_DONE]]
|
|
// CHECK18: .omp.final.done:
|
|
// CHECK18-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96
|
|
// CHECK19-SAME: () #[[ATTR0:[0-9]+]] {
|
|
// CHECK19-NEXT: entry:
|
|
// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
|
|
// CHECK19-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined.
|
|
// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] {
|
|
// CHECK19-NEXT: entry:
|
|
// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[I:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK19-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK19-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK19-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
|
|
// CHECK19-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
|
|
// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5
|
|
// CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK19: cond.true:
|
|
// CHECK19-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK19: cond.false:
|
|
// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK19-NEXT: br label [[COND_END]]
|
|
// CHECK19: cond.end:
|
|
// CHECK19-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
|
|
// CHECK19-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK19-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK19: omp.inner.for.cond:
|
|
// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
|
|
// CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !12
|
|
// CHECK19-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
|
|
// CHECK19-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK19: omp.inner.for.body:
|
|
// CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
|
|
// CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5
|
|
// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]]
|
|
// CHECK19-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !12
|
|
// CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK19: omp.body.continue:
|
|
// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK19: omp.inner.for.inc:
|
|
// CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
|
|
// CHECK19-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
|
|
// CHECK19-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
|
|
// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]
|
|
// CHECK19: omp.inner.for.end:
|
|
// CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK19: omp.loop.exit:
|
|
// CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
|
|
// CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK19-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0
|
|
// CHECK19-NEXT: br i1 [[TMP10]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
|
|
// CHECK19: .omp.final.then:
|
|
// CHECK19-NEXT: store i32 33, i32* [[I]], align 4
|
|
// CHECK19-NEXT: br label [[DOTOMP_FINAL_DONE]]
|
|
// CHECK19: .omp.final.done:
|
|
// CHECK19-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108
|
|
// CHECK19-SAME: (i32 [[AA:%.*]], i32 [[LIN:%.*]], i32 [[A:%.*]]) #[[ATTR0]] {
|
|
// CHECK19-NEXT: entry:
|
|
// CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
|
|
// CHECK19-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
|
|
// CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
|
|
// CHECK19-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
|
|
// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
|
|
// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[LIN_ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 [[TMP2]], i32* [[LIN_CASTED]], align 4
|
|
// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[LIN_CASTED]], align 4
|
|
// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 [[TMP4]], i32* [[A_CASTED]], align 4
|
|
// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[A_CASTED]], align 4
|
|
// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]])
|
|
// CHECK19-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..1
|
|
// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]], i32 [[LIN:%.*]], i32 [[A:%.*]]) #[[ATTR1]] {
|
|
// CHECK19-NEXT: entry:
|
|
// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
|
|
// CHECK19-NEXT: [[TMP:%.*]] = alloca i64, align 4
|
|
// CHECK19-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[DOTLINEAR_START1:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8
|
|
// CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
|
|
// CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
|
|
// CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
|
|
// CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[IT:%.*]] = alloca i64, align 8
|
|
// CHECK19-NEXT: [[LIN2:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[A3:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
|
|
// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[LIN_ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4
|
|
// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START1]], align 4
|
|
// CHECK19-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() #[[ATTR5:[0-9]+]]
|
|
// CHECK19-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8
|
|
// CHECK19-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK19-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK19-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
|
|
// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK19-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
|
|
// CHECK19-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP3]])
|
|
// CHECK19-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
|
|
// CHECK19-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK19-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3
|
|
// CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK19: cond.true:
|
|
// CHECK19-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK19: cond.false:
|
|
// CHECK19-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK19-NEXT: br label [[COND_END]]
|
|
// CHECK19: cond.end:
|
|
// CHECK19-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
|
|
// CHECK19-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
|
|
// CHECK19-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK19-NEXT: store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK19: omp.inner.for.cond:
|
|
// CHECK19-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18
|
|
// CHECK19-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !18
|
|
// CHECK19-NEXT: [[CMP4:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]]
|
|
// CHECK19-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK19: omp.inner.for.body:
|
|
// CHECK19-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18
|
|
// CHECK19-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400
|
|
// CHECK19-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]
|
|
// CHECK19-NEXT: store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !18
|
|
// CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4, !llvm.access.group !18
|
|
// CHECK19-NEXT: [[CONV5:%.*]] = sext i32 [[TMP10]] to i64
|
|
// CHECK19-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18
|
|
// CHECK19-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !18
|
|
// CHECK19-NEXT: [[MUL6:%.*]] = mul i64 [[TMP11]], [[TMP12]]
|
|
// CHECK19-NEXT: [[ADD:%.*]] = add i64 [[CONV5]], [[MUL6]]
|
|
// CHECK19-NEXT: [[CONV7:%.*]] = trunc i64 [[ADD]] to i32
|
|
// CHECK19-NEXT: store i32 [[CONV7]], i32* [[LIN2]], align 4, !llvm.access.group !18
|
|
// CHECK19-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START1]], align 4, !llvm.access.group !18
|
|
// CHECK19-NEXT: [[CONV8:%.*]] = sext i32 [[TMP13]] to i64
|
|
// CHECK19-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18
|
|
// CHECK19-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !18
|
|
// CHECK19-NEXT: [[MUL9:%.*]] = mul i64 [[TMP14]], [[TMP15]]
|
|
// CHECK19-NEXT: [[ADD10:%.*]] = add i64 [[CONV8]], [[MUL9]]
|
|
// CHECK19-NEXT: [[CONV11:%.*]] = trunc i64 [[ADD10]] to i32
|
|
// CHECK19-NEXT: store i32 [[CONV11]], i32* [[A3]], align 4, !llvm.access.group !18
|
|
// CHECK19-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !18
|
|
// CHECK19-NEXT: [[CONV12:%.*]] = sext i16 [[TMP16]] to i32
|
|
// CHECK19-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1
|
|
// CHECK19-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16
|
|
// CHECK19-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 4, !llvm.access.group !18
|
|
// CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK19: omp.body.continue:
|
|
// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK19: omp.inner.for.inc:
|
|
// CHECK19-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18
|
|
// CHECK19-NEXT: [[ADD15:%.*]] = add i64 [[TMP17]], 1
|
|
// CHECK19-NEXT: store i64 [[ADD15]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18
|
|
// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]
|
|
// CHECK19: omp.inner.for.end:
|
|
// CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK19: omp.loop.exit:
|
|
// CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
|
|
// CHECK19-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK19-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
|
|
// CHECK19-NEXT: br i1 [[TMP19]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
|
|
// CHECK19: .omp.final.then:
|
|
// CHECK19-NEXT: store i64 400, i64* [[IT]], align 8
|
|
// CHECK19-NEXT: br label [[DOTOMP_FINAL_DONE]]
|
|
// CHECK19: .omp.final.done:
|
|
// CHECK19-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK19-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0
|
|
// CHECK19-NEXT: br i1 [[TMP21]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
|
|
// CHECK19: .omp.linear.pu:
|
|
// CHECK19-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4
|
|
// CHECK19-NEXT: [[CONV16:%.*]] = sext i32 [[TMP22]] to i64
|
|
// CHECK19-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
|
|
// CHECK19-NEXT: [[MUL17:%.*]] = mul i64 4, [[TMP23]]
|
|
// CHECK19-NEXT: [[ADD18:%.*]] = add i64 [[CONV16]], [[MUL17]]
|
|
// CHECK19-NEXT: [[CONV19:%.*]] = trunc i64 [[ADD18]] to i32
|
|
// CHECK19-NEXT: store i32 [[CONV19]], i32* [[LIN_ADDR]], align 4
|
|
// CHECK19-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTLINEAR_START1]], align 4
|
|
// CHECK19-NEXT: [[CONV20:%.*]] = sext i32 [[TMP24]] to i64
|
|
// CHECK19-NEXT: [[TMP25:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
|
|
// CHECK19-NEXT: [[MUL21:%.*]] = mul i64 4, [[TMP25]]
|
|
// CHECK19-NEXT: [[ADD22:%.*]] = add i64 [[CONV20]], [[MUL21]]
|
|
// CHECK19-NEXT: [[CONV23:%.*]] = trunc i64 [[ADD22]] to i32
|
|
// CHECK19-NEXT: store i32 [[CONV23]], i32* [[A_ADDR]], align 4
|
|
// CHECK19-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]]
|
|
// CHECK19: .omp.linear.pu.done:
|
|
// CHECK19-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK19-LABEL: define {{[^@]+}}@_Z7get_valv
|
|
// CHECK19-SAME: () #[[ATTR3:[0-9]+]] {
|
|
// CHECK19-NEXT: entry:
|
|
// CHECK19-NEXT: ret i64 0
|
|
//
|
|
//
|
|
// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116
|
|
// CHECK19-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] {
|
|
// CHECK19-NEXT: entry:
|
|
// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
|
|
// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
|
|
// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
|
|
// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
|
|
// CHECK19-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
|
|
// CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
|
|
// CHECK19-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
|
|
// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
|
|
// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]])
|
|
// CHECK19-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..2
|
|
// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR1]] {
|
|
// CHECK19-NEXT: entry:
|
|
// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[TMP:%.*]] = alloca i16, align 2
|
|
// CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[IT:%.*]] = alloca i16, align 2
|
|
// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
|
|
// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
|
|
// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK19-NEXT: store i32 3, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK19-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK19-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
|
|
// CHECK19-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
|
|
// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3
|
|
// CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK19: cond.true:
|
|
// CHECK19-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK19: cond.false:
|
|
// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK19-NEXT: br label [[COND_END]]
|
|
// CHECK19: cond.end:
|
|
// CHECK19-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
|
|
// CHECK19-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK19-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK19: omp.inner.for.cond:
|
|
// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
|
|
// CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !21
|
|
// CHECK19-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
|
|
// CHECK19-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK19: omp.inner.for.body:
|
|
// CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
|
|
// CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4
|
|
// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]]
|
|
// CHECK19-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
|
|
// CHECK19-NEXT: store i16 [[CONV2]], i16* [[IT]], align 2, !llvm.access.group !21
|
|
// CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !21
|
|
// CHECK19-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1
|
|
// CHECK19-NEXT: store i32 [[ADD3]], i32* [[A_ADDR]], align 4, !llvm.access.group !21
|
|
// CHECK19-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !21
|
|
// CHECK19-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32
|
|
// CHECK19-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
|
|
// CHECK19-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
|
|
// CHECK19-NEXT: store i16 [[CONV6]], i16* [[CONV]], align 4, !llvm.access.group !21
|
|
// CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK19: omp.body.continue:
|
|
// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK19: omp.inner.for.inc:
|
|
// CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
|
|
// CHECK19-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1
|
|
// CHECK19-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
|
|
// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]]
|
|
// CHECK19: omp.inner.for.end:
|
|
// CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK19: omp.loop.exit:
|
|
// CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
|
|
// CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK19-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
|
|
// CHECK19-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
|
|
// CHECK19: .omp.final.then:
|
|
// CHECK19-NEXT: store i16 22, i16* [[IT]], align 2
|
|
// CHECK19-NEXT: br label [[DOTOMP_FINAL_DONE]]
|
|
// CHECK19: .omp.final.done:
|
|
// CHECK19-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140
|
|
// CHECK19-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
|
|
// CHECK19-NEXT: entry:
|
|
// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
|
|
// CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4
|
|
// CHECK19-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
|
|
// CHECK19-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4
|
|
// CHECK19-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
|
|
// CHECK19-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK19-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
|
|
// CHECK19-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4
|
|
// CHECK19-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
|
|
// CHECK19-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
|
|
// CHECK19-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4
|
|
// CHECK19-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK19-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
|
|
// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
|
|
// CHECK19-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
|
|
// CHECK19-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
|
|
// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
|
|
// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
|
|
// CHECK19-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
|
|
// CHECK19-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
|
|
// CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4
|
|
// CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4
|
|
// CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
|
|
// CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
|
|
// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i32 [[TMP11]])
|
|
// CHECK19-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..3
|
|
// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
|
|
// CHECK19-NEXT: entry:
|
|
// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
|
|
// CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4
|
|
// CHECK19-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
|
|
// CHECK19-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4
|
|
// CHECK19-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
|
|
// CHECK19-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[TMP:%.*]] = alloca i8, align 1
|
|
// CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[IT:%.*]] = alloca i8, align 1
|
|
// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK19-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
|
|
// CHECK19-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4
|
|
// CHECK19-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
|
|
// CHECK19-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
|
|
// CHECK19-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4
|
|
// CHECK19-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK19-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
|
|
// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
|
|
// CHECK19-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
|
|
// CHECK19-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
|
|
// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
|
|
// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
|
|
// CHECK19-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
|
|
// CHECK19-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK19-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK19-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK19-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
|
|
// CHECK19-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
|
|
// CHECK19-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
|
|
// CHECK19: omp.dispatch.cond:
|
|
// CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25
|
|
// CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK19: cond.true:
|
|
// CHECK19-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK19: cond.false:
|
|
// CHECK19-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK19-NEXT: br label [[COND_END]]
|
|
// CHECK19: cond.end:
|
|
// CHECK19-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
|
|
// CHECK19-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK19-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK19-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK19-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK19-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK19-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
|
|
// CHECK19-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
|
|
// CHECK19: omp.dispatch.body:
|
|
// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK19: omp.inner.for.cond:
|
|
// CHECK19-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
|
|
// CHECK19-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !24
|
|
// CHECK19-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
|
|
// CHECK19-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK19: omp.inner.for.body:
|
|
// CHECK19-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
|
|
// CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
|
|
// CHECK19-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]]
|
|
// CHECK19-NEXT: [[CONV:%.*]] = trunc i32 [[SUB]] to i8
|
|
// CHECK19-NEXT: store i8 [[CONV]], i8* [[IT]], align 1, !llvm.access.group !24
|
|
// CHECK19-NEXT: [[TMP19:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !24
|
|
// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1
|
|
// CHECK19-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4, !llvm.access.group !24
|
|
// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2
|
|
// CHECK19-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !24
|
|
// CHECK19-NEXT: [[CONV7:%.*]] = fpext float [[TMP20]] to double
|
|
// CHECK19-NEXT: [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00
|
|
// CHECK19-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float
|
|
// CHECK19-NEXT: store float [[CONV9]], float* [[ARRAYIDX]], align 4, !llvm.access.group !24
|
|
// CHECK19-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3
|
|
// CHECK19-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX10]], align 4, !llvm.access.group !24
|
|
// CHECK19-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double
|
|
// CHECK19-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00
|
|
// CHECK19-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float
|
|
// CHECK19-NEXT: store float [[CONV13]], float* [[ARRAYIDX10]], align 4, !llvm.access.group !24
|
|
// CHECK19-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1
|
|
// CHECK19-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX14]], i32 0, i32 2
|
|
// CHECK19-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX15]], align 8, !llvm.access.group !24
|
|
// CHECK19-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00
|
|
// CHECK19-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8, !llvm.access.group !24
|
|
// CHECK19-NEXT: [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]]
|
|
// CHECK19-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP23]]
|
|
// CHECK19-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX17]], i32 3
|
|
// CHECK19-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX18]], align 8, !llvm.access.group !24
|
|
// CHECK19-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00
|
|
// CHECK19-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8, !llvm.access.group !24
|
|
// CHECK19-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0
|
|
// CHECK19-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 4, !llvm.access.group !24
|
|
// CHECK19-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1
|
|
// CHECK19-NEXT: store i64 [[ADD20]], i64* [[X]], align 4, !llvm.access.group !24
|
|
// CHECK19-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1
|
|
// CHECK19-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 4, !llvm.access.group !24
|
|
// CHECK19-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i32
|
|
// CHECK19-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1
|
|
// CHECK19-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8
|
|
// CHECK19-NEXT: store i8 [[CONV23]], i8* [[Y]], align 4, !llvm.access.group !24
|
|
// CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK19: omp.body.continue:
|
|
// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK19: omp.inner.for.inc:
|
|
// CHECK19-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
|
|
// CHECK19-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1
|
|
// CHECK19-NEXT: store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
|
|
// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]]
|
|
// CHECK19: omp.inner.for.end:
|
|
// CHECK19-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
|
|
// CHECK19: omp.dispatch.inc:
|
|
// CHECK19-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK19-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK19-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]
|
|
// CHECK19-NEXT: store i32 [[ADD25]], i32* [[DOTOMP_LB]], align 4
|
|
// CHECK19-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK19-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK19-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]]
|
|
// CHECK19-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK19-NEXT: br label [[OMP_DISPATCH_COND]]
|
|
// CHECK19: omp.dispatch.end:
|
|
// CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]])
|
|
// CHECK19-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK19-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0
|
|
// CHECK19-NEXT: br i1 [[TMP33]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
|
|
// CHECK19: .omp.final.then:
|
|
// CHECK19-NEXT: store i8 96, i8* [[IT]], align 1
|
|
// CHECK19-NEXT: br label [[DOTOMP_FINAL_DONE]]
|
|
// CHECK19: .omp.final.done:
|
|
// CHECK19-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195
|
|
// CHECK19-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
|
|
// CHECK19-NEXT: entry:
|
|
// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
|
|
// CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
|
|
// CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
|
|
// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
|
|
// CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
|
|
// CHECK19-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
|
|
// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
|
|
// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
|
|
// CHECK19-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
|
|
// CHECK19-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
|
|
// CHECK19-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2
|
|
// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
|
|
// CHECK19-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 4
|
|
// CHECK19-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
|
|
// CHECK19-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1
|
|
// CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
|
|
// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]])
|
|
// CHECK19-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..4
|
|
// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {
|
|
// CHECK19-NEXT: entry:
|
|
// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
|
|
// CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
|
|
// CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
|
|
// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
|
|
// CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
|
|
// CHECK19-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
|
|
// CHECK19-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216
|
|
// CHECK19-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {
|
|
// CHECK19-NEXT: entry:
|
|
// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
|
|
// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4
|
|
// CHECK19-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
|
|
// CHECK19-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4
|
|
// CHECK19-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
|
|
// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
|
|
// CHECK19-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
|
|
// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4
|
|
// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4
|
|
// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]])
|
|
// CHECK19-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..5
|
|
// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] {
|
|
// CHECK19-NEXT: entry:
|
|
// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
|
|
// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4
|
|
// CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
|
|
// CHECK19-NEXT: [[TMP:%.*]] = alloca i64, align 4
|
|
// CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
|
|
// CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
|
|
// CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
|
|
// CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[IT:%.*]] = alloca i64, align 8
|
|
// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK19-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
|
|
// CHECK19-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4
|
|
// CHECK19-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
|
|
// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
|
|
// CHECK19-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
|
|
// CHECK19-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK19-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK19-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
|
|
// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK19-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
|
|
// CHECK19-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
|
|
// CHECK19-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK19-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 3
|
|
// CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK19: cond.true:
|
|
// CHECK19-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK19: cond.false:
|
|
// CHECK19-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK19-NEXT: br label [[COND_END]]
|
|
// CHECK19: cond.end:
|
|
// CHECK19-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
|
|
// CHECK19-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
|
|
// CHECK19-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK19-NEXT: store i64 [[TMP8]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK19: omp.inner.for.cond:
|
|
// CHECK19-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !27
|
|
// CHECK19-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !27
|
|
// CHECK19-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]]
|
|
// CHECK19-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK19: omp.inner.for.body:
|
|
// CHECK19-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !27
|
|
// CHECK19-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400
|
|
// CHECK19-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]
|
|
// CHECK19-NEXT: store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !27
|
|
// CHECK19-NEXT: [[TMP12:%.*]] = load i32, i32* [[B_ADDR]], align 4, !llvm.access.group !27
|
|
// CHECK19-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP12]] to double
|
|
// CHECK19-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00
|
|
// CHECK19-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
|
|
// CHECK19-NEXT: store double [[ADD]], double* [[A]], align 4, !llvm.access.group !27
|
|
// CHECK19-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
|
|
// CHECK19-NEXT: [[TMP13:%.*]] = load double, double* [[A4]], align 4, !llvm.access.group !27
|
|
// CHECK19-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00
|
|
// CHECK19-NEXT: store double [[INC]], double* [[A4]], align 4, !llvm.access.group !27
|
|
// CHECK19-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16
|
|
// CHECK19-NEXT: [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]]
|
|
// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP14]]
|
|
// CHECK19-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
|
|
// CHECK19-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2, !llvm.access.group !27
|
|
// CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK19: omp.body.continue:
|
|
// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK19: omp.inner.for.inc:
|
|
// CHECK19-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !27
|
|
// CHECK19-NEXT: [[ADD7:%.*]] = add i64 [[TMP15]], 1
|
|
// CHECK19-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !27
|
|
// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]]
|
|
// CHECK19: omp.inner.for.end:
|
|
// CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK19: omp.loop.exit:
|
|
// CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
|
|
// CHECK19-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK19-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0
|
|
// CHECK19-NEXT: br i1 [[TMP17]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
|
|
// CHECK19: .omp.final.then:
|
|
// CHECK19-NEXT: store i64 400, i64* [[IT]], align 8
|
|
// CHECK19-NEXT: br label [[DOTOMP_FINAL_DONE]]
|
|
// CHECK19: .omp.final.done:
|
|
// CHECK19-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178
|
|
// CHECK19-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
|
|
// CHECK19-NEXT: entry:
|
|
// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
|
|
// CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
|
|
// CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
|
|
// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
|
|
// CHECK19-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
|
|
// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
|
|
// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
|
|
// CHECK19-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
|
|
// CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
|
|
// CHECK19-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2
|
|
// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
|
|
// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]])
|
|
// CHECK19-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..6
|
|
// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {
|
|
// CHECK19-NEXT: entry:
|
|
// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
|
|
// CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
|
|
// CHECK19-NEXT: [[TMP:%.*]] = alloca i64, align 4
|
|
// CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
|
|
// CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
|
|
// CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
|
|
// CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[I:%.*]] = alloca i64, align 8
|
|
// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
|
|
// CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
|
|
// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
|
|
// CHECK19-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
|
|
// CHECK19-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK19-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK19-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
|
|
// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK19-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
|
|
// CHECK19-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
|
|
// CHECK19-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6
|
|
// CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK19: cond.true:
|
|
// CHECK19-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK19: cond.false:
|
|
// CHECK19-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK19-NEXT: br label [[COND_END]]
|
|
// CHECK19: cond.end:
|
|
// CHECK19-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
|
|
// CHECK19-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
|
|
// CHECK19-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK19-NEXT: store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK19: omp.inner.for.cond:
|
|
// CHECK19-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !30
|
|
// CHECK19-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !30
|
|
// CHECK19-NEXT: [[CMP1:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]]
|
|
// CHECK19-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK19: omp.inner.for.body:
|
|
// CHECK19-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !30
|
|
// CHECK19-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3
|
|
// CHECK19-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
|
|
// CHECK19-NEXT: store i64 [[ADD]], i64* [[I]], align 8, !llvm.access.group !30
|
|
// CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !30
|
|
// CHECK19-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
|
|
// CHECK19-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4, !llvm.access.group !30
|
|
// CHECK19-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !30
|
|
// CHECK19-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32
|
|
// CHECK19-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
|
|
// CHECK19-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
|
|
// CHECK19-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 4, !llvm.access.group !30
|
|
// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
|
|
// CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !30
|
|
// CHECK19-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1
|
|
// CHECK19-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !30
|
|
// CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK19: omp.body.continue:
|
|
// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK19: omp.inner.for.inc:
|
|
// CHECK19-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !30
|
|
// CHECK19-NEXT: [[ADD7:%.*]] = add nsw i64 [[TMP12]], 1
|
|
// CHECK19-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !30
|
|
// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP31:![0-9]+]]
|
|
// CHECK19: omp.inner.for.end:
|
|
// CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK19: omp.loop.exit:
|
|
// CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
|
|
// CHECK19-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK19-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
|
|
// CHECK19-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
|
|
// CHECK19: .omp.final.then:
|
|
// CHECK19-NEXT: store i64 11, i64* [[I]], align 8
|
|
// CHECK19-NEXT: br label [[DOTOMP_FINAL_DONE]]
|
|
// CHECK19: .omp.final.done:
|
|
// CHECK19-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96
|
|
// CHECK20-SAME: () #[[ATTR0:[0-9]+]] {
|
|
// CHECK20-NEXT: entry:
|
|
// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
|
|
// CHECK20-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined.
|
|
// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] {
|
|
// CHECK20-NEXT: entry:
|
|
// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[I:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK20-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK20-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK20-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
|
|
// CHECK20-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
|
|
// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5
|
|
// CHECK20-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK20: cond.true:
|
|
// CHECK20-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK20: cond.false:
|
|
// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK20-NEXT: br label [[COND_END]]
|
|
// CHECK20: cond.end:
|
|
// CHECK20-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
|
|
// CHECK20-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK20-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK20: omp.inner.for.cond:
|
|
// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
|
|
// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !12
|
|
// CHECK20-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
|
|
// CHECK20-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK20: omp.inner.for.body:
|
|
// CHECK20-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
|
|
// CHECK20-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5
|
|
// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]]
|
|
// CHECK20-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !12
|
|
// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK20: omp.body.continue:
|
|
// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK20: omp.inner.for.inc:
|
|
// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
|
|
// CHECK20-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
|
|
// CHECK20-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
|
|
// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]
|
|
// CHECK20: omp.inner.for.end:
|
|
// CHECK20-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK20: omp.loop.exit:
|
|
// CHECK20-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
|
|
// CHECK20-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK20-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0
|
|
// CHECK20-NEXT: br i1 [[TMP10]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
|
|
// CHECK20: .omp.final.then:
|
|
// CHECK20-NEXT: store i32 33, i32* [[I]], align 4
|
|
// CHECK20-NEXT: br label [[DOTOMP_FINAL_DONE]]
|
|
// CHECK20: .omp.final.done:
|
|
// CHECK20-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108
|
|
// CHECK20-SAME: (i32 [[AA:%.*]], i32 [[LIN:%.*]], i32 [[A:%.*]]) #[[ATTR0]] {
|
|
// CHECK20-NEXT: entry:
|
|
// CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
|
|
// CHECK20-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4
|
|
// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
|
|
// CHECK20-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
|
|
// CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
|
|
// CHECK20-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
|
|
// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
|
|
// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[LIN_ADDR]], align 4
|
|
// CHECK20-NEXT: store i32 [[TMP2]], i32* [[LIN_CASTED]], align 4
|
|
// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[LIN_CASTED]], align 4
|
|
// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK20-NEXT: store i32 [[TMP4]], i32* [[A_CASTED]], align 4
|
|
// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[A_CASTED]], align 4
|
|
// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]])
|
|
// CHECK20-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..1
|
|
// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]], i32 [[LIN:%.*]], i32 [[A:%.*]]) #[[ATTR1]] {
|
|
// CHECK20-NEXT: entry:
|
|
// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
|
|
// CHECK20-NEXT: [[TMP:%.*]] = alloca i64, align 4
|
|
// CHECK20-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[DOTLINEAR_START1:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8
|
|
// CHECK20-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
|
|
// CHECK20-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
|
|
// CHECK20-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
|
|
// CHECK20-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[IT:%.*]] = alloca i64, align 8
|
|
// CHECK20-NEXT: [[LIN2:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[A3:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
|
|
// CHECK20-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4
|
|
// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
|
|
// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[LIN_ADDR]], align 4
|
|
// CHECK20-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4
|
|
// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK20-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START1]], align 4
|
|
// CHECK20-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() #[[ATTR5:[0-9]+]]
|
|
// CHECK20-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8
|
|
// CHECK20-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK20-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK20-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
|
|
// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK20-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
|
|
// CHECK20-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP3]])
|
|
// CHECK20-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
|
|
// CHECK20-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK20-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3
|
|
// CHECK20-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK20: cond.true:
|
|
// CHECK20-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK20: cond.false:
|
|
// CHECK20-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK20-NEXT: br label [[COND_END]]
|
|
// CHECK20: cond.end:
|
|
// CHECK20-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
|
|
// CHECK20-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
|
|
// CHECK20-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK20-NEXT: store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK20: omp.inner.for.cond:
|
|
// CHECK20-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18
|
|
// CHECK20-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !18
|
|
// CHECK20-NEXT: [[CMP4:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]]
|
|
// CHECK20-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK20: omp.inner.for.body:
|
|
// CHECK20-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18
|
|
// CHECK20-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400
|
|
// CHECK20-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]
|
|
// CHECK20-NEXT: store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !18
|
|
// CHECK20-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4, !llvm.access.group !18
|
|
// CHECK20-NEXT: [[CONV5:%.*]] = sext i32 [[TMP10]] to i64
|
|
// CHECK20-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18
|
|
// CHECK20-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !18
|
|
// CHECK20-NEXT: [[MUL6:%.*]] = mul i64 [[TMP11]], [[TMP12]]
|
|
// CHECK20-NEXT: [[ADD:%.*]] = add i64 [[CONV5]], [[MUL6]]
|
|
// CHECK20-NEXT: [[CONV7:%.*]] = trunc i64 [[ADD]] to i32
|
|
// CHECK20-NEXT: store i32 [[CONV7]], i32* [[LIN2]], align 4, !llvm.access.group !18
|
|
// CHECK20-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START1]], align 4, !llvm.access.group !18
|
|
// CHECK20-NEXT: [[CONV8:%.*]] = sext i32 [[TMP13]] to i64
|
|
// CHECK20-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18
|
|
// CHECK20-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !18
|
|
// CHECK20-NEXT: [[MUL9:%.*]] = mul i64 [[TMP14]], [[TMP15]]
|
|
// CHECK20-NEXT: [[ADD10:%.*]] = add i64 [[CONV8]], [[MUL9]]
|
|
// CHECK20-NEXT: [[CONV11:%.*]] = trunc i64 [[ADD10]] to i32
|
|
// CHECK20-NEXT: store i32 [[CONV11]], i32* [[A3]], align 4, !llvm.access.group !18
|
|
// CHECK20-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !18
|
|
// CHECK20-NEXT: [[CONV12:%.*]] = sext i16 [[TMP16]] to i32
|
|
// CHECK20-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1
|
|
// CHECK20-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16
|
|
// CHECK20-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 4, !llvm.access.group !18
|
|
// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK20: omp.body.continue:
|
|
// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK20: omp.inner.for.inc:
|
|
// CHECK20-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18
|
|
// CHECK20-NEXT: [[ADD15:%.*]] = add i64 [[TMP17]], 1
|
|
// CHECK20-NEXT: store i64 [[ADD15]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18
|
|
// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]
|
|
// CHECK20: omp.inner.for.end:
|
|
// CHECK20-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK20: omp.loop.exit:
|
|
// CHECK20-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
|
|
// CHECK20-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK20-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
|
|
// CHECK20-NEXT: br i1 [[TMP19]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
|
|
// CHECK20: .omp.final.then:
|
|
// CHECK20-NEXT: store i64 400, i64* [[IT]], align 8
|
|
// CHECK20-NEXT: br label [[DOTOMP_FINAL_DONE]]
|
|
// CHECK20: .omp.final.done:
|
|
// CHECK20-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK20-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0
|
|
// CHECK20-NEXT: br i1 [[TMP21]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
|
|
// CHECK20: .omp.linear.pu:
|
|
// CHECK20-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4
|
|
// CHECK20-NEXT: [[CONV16:%.*]] = sext i32 [[TMP22]] to i64
|
|
// CHECK20-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
|
|
// CHECK20-NEXT: [[MUL17:%.*]] = mul i64 4, [[TMP23]]
|
|
// CHECK20-NEXT: [[ADD18:%.*]] = add i64 [[CONV16]], [[MUL17]]
|
|
// CHECK20-NEXT: [[CONV19:%.*]] = trunc i64 [[ADD18]] to i32
|
|
// CHECK20-NEXT: store i32 [[CONV19]], i32* [[LIN_ADDR]], align 4
|
|
// CHECK20-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTLINEAR_START1]], align 4
|
|
// CHECK20-NEXT: [[CONV20:%.*]] = sext i32 [[TMP24]] to i64
|
|
// CHECK20-NEXT: [[TMP25:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
|
|
// CHECK20-NEXT: [[MUL21:%.*]] = mul i64 4, [[TMP25]]
|
|
// CHECK20-NEXT: [[ADD22:%.*]] = add i64 [[CONV20]], [[MUL21]]
|
|
// CHECK20-NEXT: [[CONV23:%.*]] = trunc i64 [[ADD22]] to i32
|
|
// CHECK20-NEXT: store i32 [[CONV23]], i32* [[A_ADDR]], align 4
|
|
// CHECK20-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]]
|
|
// CHECK20: .omp.linear.pu.done:
|
|
// CHECK20-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK20-LABEL: define {{[^@]+}}@_Z7get_valv
|
|
// CHECK20-SAME: () #[[ATTR3:[0-9]+]] {
|
|
// CHECK20-NEXT: entry:
|
|
// CHECK20-NEXT: ret i64 0
|
|
//
|
|
//
|
|
// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116
|
|
// CHECK20-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] {
|
|
// CHECK20-NEXT: entry:
|
|
// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
|
|
// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
|
|
// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK20-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
|
|
// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
|
|
// CHECK20-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
|
|
// CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
|
|
// CHECK20-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
|
|
// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
|
|
// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]])
|
|
// CHECK20-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..2
|
|
// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR1]] {
|
|
// CHECK20-NEXT: entry:
|
|
// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[TMP:%.*]] = alloca i16, align 2
|
|
// CHECK20-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[IT:%.*]] = alloca i16, align 2
|
|
// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
|
|
// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
|
|
// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK20-NEXT: store i32 3, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK20-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK20-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
|
|
// CHECK20-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
|
|
// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3
|
|
// CHECK20-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK20: cond.true:
|
|
// CHECK20-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK20: cond.false:
|
|
// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK20-NEXT: br label [[COND_END]]
|
|
// CHECK20: cond.end:
|
|
// CHECK20-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
|
|
// CHECK20-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK20-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK20: omp.inner.for.cond:
|
|
// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
|
|
// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !21
|
|
// CHECK20-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
|
|
// CHECK20-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK20: omp.inner.for.body:
|
|
// CHECK20-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
|
|
// CHECK20-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4
|
|
// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]]
|
|
// CHECK20-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
|
|
// CHECK20-NEXT: store i16 [[CONV2]], i16* [[IT]], align 2, !llvm.access.group !21
|
|
// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !21
|
|
// CHECK20-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1
|
|
// CHECK20-NEXT: store i32 [[ADD3]], i32* [[A_ADDR]], align 4, !llvm.access.group !21
|
|
// CHECK20-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !21
|
|
// CHECK20-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32
|
|
// CHECK20-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
|
|
// CHECK20-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
|
|
// CHECK20-NEXT: store i16 [[CONV6]], i16* [[CONV]], align 4, !llvm.access.group !21
|
|
// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK20: omp.body.continue:
|
|
// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK20: omp.inner.for.inc:
|
|
// CHECK20-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
|
|
// CHECK20-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1
|
|
// CHECK20-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
|
|
// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]]
|
|
// CHECK20: omp.inner.for.end:
|
|
// CHECK20-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK20: omp.loop.exit:
|
|
// CHECK20-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
|
|
// CHECK20-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK20-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
|
|
// CHECK20-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
|
|
// CHECK20: .omp.final.then:
|
|
// CHECK20-NEXT: store i16 22, i16* [[IT]], align 2
|
|
// CHECK20-NEXT: br label [[DOTOMP_FINAL_DONE]]
|
|
// CHECK20: .omp.final.done:
|
|
// CHECK20-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140
|
|
// CHECK20-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
|
|
// CHECK20-NEXT: entry:
|
|
// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
|
|
// CHECK20-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4
|
|
// CHECK20-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
|
|
// CHECK20-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4
|
|
// CHECK20-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
|
|
// CHECK20-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK20-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
|
|
// CHECK20-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
|
|
// CHECK20-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4
|
|
// CHECK20-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
|
|
// CHECK20-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
|
|
// CHECK20-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
|
|
// CHECK20-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4
|
|
// CHECK20-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
|
|
// CHECK20-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK20-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
|
|
// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
|
|
// CHECK20-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
|
|
// CHECK20-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
|
|
// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
|
|
// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
|
|
// CHECK20-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
|
|
// CHECK20-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
|
|
// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK20-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4
|
|
// CHECK20-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4
|
|
// CHECK20-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK20-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
|
|
// CHECK20-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
|
|
// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i32 [[TMP11]])
|
|
// CHECK20-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..3
|
|
// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
|
|
// CHECK20-NEXT: entry:
|
|
// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
|
|
// CHECK20-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4
|
|
// CHECK20-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
|
|
// CHECK20-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4
|
|
// CHECK20-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
|
|
// CHECK20-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[TMP:%.*]] = alloca i8, align 1
|
|
// CHECK20-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[IT:%.*]] = alloca i8, align 1
|
|
// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK20-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
|
|
// CHECK20-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
|
|
// CHECK20-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4
|
|
// CHECK20-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
|
|
// CHECK20-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
|
|
// CHECK20-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
|
|
// CHECK20-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4
|
|
// CHECK20-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
|
|
// CHECK20-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK20-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
|
|
// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
|
|
// CHECK20-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
|
|
// CHECK20-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
|
|
// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
|
|
// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
|
|
// CHECK20-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
|
|
// CHECK20-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
|
|
// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK20-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK20-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK20-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK20-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
|
|
// CHECK20-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
|
|
// CHECK20-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
|
|
// CHECK20: omp.dispatch.cond:
|
|
// CHECK20-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25
|
|
// CHECK20-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK20: cond.true:
|
|
// CHECK20-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK20: cond.false:
|
|
// CHECK20-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK20-NEXT: br label [[COND_END]]
|
|
// CHECK20: cond.end:
|
|
// CHECK20-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
|
|
// CHECK20-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK20-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK20-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK20-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK20-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK20-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
|
|
// CHECK20-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
|
|
// CHECK20: omp.dispatch.body:
|
|
// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK20: omp.inner.for.cond:
|
|
// CHECK20-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
|
|
// CHECK20-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !24
|
|
// CHECK20-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
|
|
// CHECK20-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK20: omp.inner.for.body:
|
|
// CHECK20-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
|
|
// CHECK20-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
|
|
// CHECK20-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]]
|
|
// CHECK20-NEXT: [[CONV:%.*]] = trunc i32 [[SUB]] to i8
|
|
// CHECK20-NEXT: store i8 [[CONV]], i8* [[IT]], align 1, !llvm.access.group !24
|
|
// CHECK20-NEXT: [[TMP19:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !24
|
|
// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1
|
|
// CHECK20-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4, !llvm.access.group !24
|
|
// CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2
|
|
// CHECK20-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !24
|
|
// CHECK20-NEXT: [[CONV7:%.*]] = fpext float [[TMP20]] to double
|
|
// CHECK20-NEXT: [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00
|
|
// CHECK20-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float
|
|
// CHECK20-NEXT: store float [[CONV9]], float* [[ARRAYIDX]], align 4, !llvm.access.group !24
|
|
// CHECK20-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3
|
|
// CHECK20-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX10]], align 4, !llvm.access.group !24
|
|
// CHECK20-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double
|
|
// CHECK20-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00
|
|
// CHECK20-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float
|
|
// CHECK20-NEXT: store float [[CONV13]], float* [[ARRAYIDX10]], align 4, !llvm.access.group !24
|
|
// CHECK20-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1
|
|
// CHECK20-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX14]], i32 0, i32 2
|
|
// CHECK20-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX15]], align 8, !llvm.access.group !24
|
|
// CHECK20-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00
|
|
// CHECK20-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8, !llvm.access.group !24
|
|
// CHECK20-NEXT: [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]]
|
|
// CHECK20-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP23]]
|
|
// CHECK20-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX17]], i32 3
|
|
// CHECK20-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX18]], align 8, !llvm.access.group !24
|
|
// CHECK20-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00
|
|
// CHECK20-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8, !llvm.access.group !24
|
|
// CHECK20-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0
|
|
// CHECK20-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 4, !llvm.access.group !24
|
|
// CHECK20-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1
|
|
// CHECK20-NEXT: store i64 [[ADD20]], i64* [[X]], align 4, !llvm.access.group !24
|
|
// CHECK20-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1
|
|
// CHECK20-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 4, !llvm.access.group !24
|
|
// CHECK20-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i32
|
|
// CHECK20-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1
|
|
// CHECK20-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8
|
|
// CHECK20-NEXT: store i8 [[CONV23]], i8* [[Y]], align 4, !llvm.access.group !24
|
|
// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK20: omp.body.continue:
|
|
// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK20: omp.inner.for.inc:
|
|
// CHECK20-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
|
|
// CHECK20-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1
|
|
// CHECK20-NEXT: store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
|
|
// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]]
|
|
// CHECK20: omp.inner.for.end:
|
|
// CHECK20-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
|
|
// CHECK20: omp.dispatch.inc:
|
|
// CHECK20-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK20-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK20-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]
|
|
// CHECK20-NEXT: store i32 [[ADD25]], i32* [[DOTOMP_LB]], align 4
|
|
// CHECK20-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK20-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK20-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]]
|
|
// CHECK20-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK20-NEXT: br label [[OMP_DISPATCH_COND]]
|
|
// CHECK20: omp.dispatch.end:
|
|
// CHECK20-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]])
|
|
// CHECK20-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK20-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0
|
|
// CHECK20-NEXT: br i1 [[TMP33]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
|
|
// CHECK20: .omp.final.then:
|
|
// CHECK20-NEXT: store i8 96, i8* [[IT]], align 1
|
|
// CHECK20-NEXT: br label [[DOTOMP_FINAL_DONE]]
|
|
// CHECK20: .omp.final.done:
|
|
// CHECK20-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195
|
|
// CHECK20-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
|
|
// CHECK20-NEXT: entry:
|
|
// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
|
|
// CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
|
|
// CHECK20-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
|
|
// CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
|
|
// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
|
|
// CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
|
|
// CHECK20-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
|
|
// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK20-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
|
|
// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
|
|
// CHECK20-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
|
|
// CHECK20-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
|
|
// CHECK20-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2
|
|
// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
|
|
// CHECK20-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 4
|
|
// CHECK20-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
|
|
// CHECK20-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1
|
|
// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
|
|
// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]])
|
|
// CHECK20-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..4
|
|
// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {
|
|
// CHECK20-NEXT: entry:
|
|
// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
|
|
// CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
|
|
// CHECK20-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
|
|
// CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
|
|
// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
|
|
// CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
|
|
// CHECK20-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
|
|
// CHECK20-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216
|
|
// CHECK20-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {
|
|
// CHECK20-NEXT: entry:
|
|
// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
|
|
// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4
|
|
// CHECK20-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK20-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
|
|
// CHECK20-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
|
|
// CHECK20-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
|
|
// CHECK20-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4
|
|
// CHECK20-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
|
|
// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
|
|
// CHECK20-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
|
|
// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4
|
|
// CHECK20-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4
|
|
// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4
|
|
// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]])
|
|
// CHECK20-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..5
|
|
// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] {
|
|
// CHECK20-NEXT: entry:
|
|
// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
|
|
// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4
|
|
// CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
|
|
// CHECK20-NEXT: [[TMP:%.*]] = alloca i64, align 4
|
|
// CHECK20-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
|
|
// CHECK20-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
|
|
// CHECK20-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
|
|
// CHECK20-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[IT:%.*]] = alloca i64, align 8
|
|
// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK20-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK20-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
|
|
// CHECK20-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
|
|
// CHECK20-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
|
|
// CHECK20-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4
|
|
// CHECK20-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
|
|
// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
|
|
// CHECK20-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
|
|
// CHECK20-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK20-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK20-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
|
|
// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK20-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
|
|
// CHECK20-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
|
|
// CHECK20-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK20-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 3
|
|
// CHECK20-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK20: cond.true:
|
|
// CHECK20-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK20: cond.false:
|
|
// CHECK20-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK20-NEXT: br label [[COND_END]]
|
|
// CHECK20: cond.end:
|
|
// CHECK20-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
|
|
// CHECK20-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
|
|
// CHECK20-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK20-NEXT: store i64 [[TMP8]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK20: omp.inner.for.cond:
|
|
// CHECK20-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !27
|
|
// CHECK20-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !27
|
|
// CHECK20-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]]
|
|
// CHECK20-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK20: omp.inner.for.body:
|
|
// CHECK20-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !27
|
|
// CHECK20-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400
|
|
// CHECK20-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]
|
|
// CHECK20-NEXT: store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !27
|
|
// CHECK20-NEXT: [[TMP12:%.*]] = load i32, i32* [[B_ADDR]], align 4, !llvm.access.group !27
|
|
// CHECK20-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP12]] to double
|
|
// CHECK20-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00
|
|
// CHECK20-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
|
|
// CHECK20-NEXT: store double [[ADD]], double* [[A]], align 4, !llvm.access.group !27
|
|
// CHECK20-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
|
|
// CHECK20-NEXT: [[TMP13:%.*]] = load double, double* [[A4]], align 4, !llvm.access.group !27
|
|
// CHECK20-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00
|
|
// CHECK20-NEXT: store double [[INC]], double* [[A4]], align 4, !llvm.access.group !27
|
|
// CHECK20-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16
|
|
// CHECK20-NEXT: [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]]
|
|
// CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP14]]
|
|
// CHECK20-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
|
|
// CHECK20-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2, !llvm.access.group !27
|
|
// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK20: omp.body.continue:
|
|
// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK20: omp.inner.for.inc:
|
|
// CHECK20-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !27
|
|
// CHECK20-NEXT: [[ADD7:%.*]] = add i64 [[TMP15]], 1
|
|
// CHECK20-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !27
|
|
// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]]
|
|
// CHECK20: omp.inner.for.end:
|
|
// CHECK20-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK20: omp.loop.exit:
|
|
// CHECK20-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
|
|
// CHECK20-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK20-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0
|
|
// CHECK20-NEXT: br i1 [[TMP17]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
|
|
// CHECK20: .omp.final.then:
|
|
// CHECK20-NEXT: store i64 400, i64* [[IT]], align 8
|
|
// CHECK20-NEXT: br label [[DOTOMP_FINAL_DONE]]
|
|
// CHECK20: .omp.final.done:
|
|
// CHECK20-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178
|
|
// CHECK20-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
|
|
// CHECK20-NEXT: entry:
|
|
// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
|
|
// CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
|
|
// CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
|
|
// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
|
|
// CHECK20-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
|
|
// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK20-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
|
|
// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
|
|
// CHECK20-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
|
|
// CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
|
|
// CHECK20-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2
|
|
// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
|
|
// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]])
|
|
// CHECK20-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..6
|
|
// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {
|
|
// CHECK20-NEXT: entry:
|
|
// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
|
|
// CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
|
|
// CHECK20-NEXT: [[TMP:%.*]] = alloca i64, align 4
|
|
// CHECK20-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
|
|
// CHECK20-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
|
|
// CHECK20-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
|
|
// CHECK20-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[I:%.*]] = alloca i64, align 8
|
|
// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
|
|
// CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
|
|
// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
|
|
// CHECK20-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
|
|
// CHECK20-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK20-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK20-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
|
|
// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK20-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
|
|
// CHECK20-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
|
|
// CHECK20-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6
|
|
// CHECK20-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK20: cond.true:
|
|
// CHECK20-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK20: cond.false:
|
|
// CHECK20-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK20-NEXT: br label [[COND_END]]
|
|
// CHECK20: cond.end:
|
|
// CHECK20-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
|
|
// CHECK20-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
|
|
// CHECK20-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK20-NEXT: store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK20: omp.inner.for.cond:
|
|
// CHECK20-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !30
|
|
// CHECK20-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !30
|
|
// CHECK20-NEXT: [[CMP1:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]]
|
|
// CHECK20-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK20: omp.inner.for.body:
|
|
// CHECK20-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !30
|
|
// CHECK20-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3
|
|
// CHECK20-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
|
|
// CHECK20-NEXT: store i64 [[ADD]], i64* [[I]], align 8, !llvm.access.group !30
|
|
// CHECK20-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !30
|
|
// CHECK20-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
|
|
// CHECK20-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4, !llvm.access.group !30
|
|
// CHECK20-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !30
|
|
// CHECK20-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32
|
|
// CHECK20-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
|
|
// CHECK20-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
|
|
// CHECK20-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 4, !llvm.access.group !30
|
|
// CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
|
|
// CHECK20-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !30
|
|
// CHECK20-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1
|
|
// CHECK20-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !30
|
|
// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK20: omp.body.continue:
|
|
// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK20: omp.inner.for.inc:
|
|
// CHECK20-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !30
|
|
// CHECK20-NEXT: [[ADD7:%.*]] = add nsw i64 [[TMP12]], 1
|
|
// CHECK20-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !30
|
|
// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP31:![0-9]+]]
|
|
// CHECK20: omp.inner.for.end:
|
|
// CHECK20-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK20: omp.loop.exit:
|
|
// CHECK20-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
|
|
// CHECK20-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK20-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
|
|
// CHECK20-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
|
|
// CHECK20: .omp.final.then:
|
|
// CHECK20-NEXT: store i64 11, i64* [[I]], align 8
|
|
// CHECK20-NEXT: br label [[DOTOMP_FINAL_DONE]]
|
|
// CHECK20: .omp.final.done:
|
|
// CHECK20-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96
|
|
// CHECK21-SAME: () #[[ATTR0:[0-9]+]] {
|
|
// CHECK21-NEXT: entry:
|
|
// CHECK21-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
|
|
// CHECK21-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK21-LABEL: define {{[^@]+}}@.omp_outlined.
|
|
// CHECK21-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] {
|
|
// CHECK21-NEXT: entry:
|
|
// CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK21-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK21-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK21-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK21-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK21-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK21-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK21-NEXT: [[I:%.*]] = alloca i32, align 4
|
|
// CHECK21-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK21-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK21-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK21-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK21-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK21-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK21-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK21-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
|
|
// CHECK21-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
|
|
// CHECK21-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK21-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5
|
|
// CHECK21-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK21: cond.true:
|
|
// CHECK21-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK21: cond.false:
|
|
// CHECK21-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK21-NEXT: br label [[COND_END]]
|
|
// CHECK21: cond.end:
|
|
// CHECK21-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
|
|
// CHECK21-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK21-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK21-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK21-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK21: omp.inner.for.cond:
|
|
// CHECK21-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
|
|
// CHECK21-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !11
|
|
// CHECK21-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
|
|
// CHECK21-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK21: omp.inner.for.body:
|
|
// CHECK21-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
|
|
// CHECK21-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5
|
|
// CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]]
|
|
// CHECK21-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11
|
|
// CHECK21-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK21: omp.body.continue:
|
|
// CHECK21-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK21: omp.inner.for.inc:
|
|
// CHECK21-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
|
|
// CHECK21-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
|
|
// CHECK21-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
|
|
// CHECK21-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]
|
|
// CHECK21: omp.inner.for.end:
|
|
// CHECK21-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK21: omp.loop.exit:
|
|
// CHECK21-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
|
|
// CHECK21-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK21-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0
|
|
// CHECK21-NEXT: br i1 [[TMP10]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
|
|
// CHECK21: .omp.final.then:
|
|
// CHECK21-NEXT: store i32 33, i32* [[I]], align 4
|
|
// CHECK21-NEXT: br label [[DOTOMP_FINAL_DONE]]
|
|
// CHECK21: .omp.final.done:
|
|
// CHECK21-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108
|
|
// CHECK21-SAME: (i64 [[AA:%.*]], i64 [[LIN:%.*]], i64 [[A:%.*]]) #[[ATTR0]] {
|
|
// CHECK21-NEXT: entry:
|
|
// CHECK21-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK21-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK21-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK21-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK21-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK21-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK21-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
|
|
// CHECK21-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8
|
|
// CHECK21-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK21-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
|
|
// CHECK21-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32*
|
|
// CHECK21-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK21-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8
|
|
// CHECK21-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
|
|
// CHECK21-NEXT: store i16 [[TMP0]], i16* [[CONV3]], align 2
|
|
// CHECK21-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
|
|
// CHECK21-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8
|
|
// CHECK21-NEXT: [[CONV4:%.*]] = bitcast i64* [[LIN_CASTED]] to i32*
|
|
// CHECK21-NEXT: store i32 [[TMP2]], i32* [[CONV4]], align 4
|
|
// CHECK21-NEXT: [[TMP3:%.*]] = load i64, i64* [[LIN_CASTED]], align 8
|
|
// CHECK21-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV2]], align 8
|
|
// CHECK21-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
|
|
// CHECK21-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4
|
|
// CHECK21-NEXT: [[TMP5:%.*]] = load i64, i64* [[A_CASTED]], align 8
|
|
// CHECK21-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]])
|
|
// CHECK21-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK21-LABEL: define {{[^@]+}}@.omp_outlined..1
|
|
// CHECK21-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]], i64 [[LIN:%.*]], i64 [[A:%.*]]) #[[ATTR1]] {
|
|
// CHECK21-NEXT: entry:
|
|
// CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK21-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK21-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK21-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK21-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
|
|
// CHECK21-NEXT: [[TMP:%.*]] = alloca i64, align 8
|
|
// CHECK21-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4
|
|
// CHECK21-NEXT: [[DOTLINEAR_START3:%.*]] = alloca i32, align 4
|
|
// CHECK21-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8
|
|
// CHECK21-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
|
|
// CHECK21-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
|
|
// CHECK21-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
|
|
// CHECK21-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK21-NEXT: [[IT:%.*]] = alloca i64, align 8
|
|
// CHECK21-NEXT: [[LIN4:%.*]] = alloca i32, align 4
|
|
// CHECK21-NEXT: [[A5:%.*]] = alloca i32, align 4
|
|
// CHECK21-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK21-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK21-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
|
|
// CHECK21-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8
|
|
// CHECK21-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK21-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
|
|
// CHECK21-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32*
|
|
// CHECK21-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK21-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV1]], align 8
|
|
// CHECK21-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4
|
|
// CHECK21-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 8
|
|
// CHECK21-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START3]], align 4
|
|
// CHECK21-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() #[[ATTR5:[0-9]+]]
|
|
// CHECK21-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8
|
|
// CHECK21-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK21-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK21-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
|
|
// CHECK21-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK21-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK21-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
|
|
// CHECK21-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP3]])
|
|
// CHECK21-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
|
|
// CHECK21-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK21-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3
|
|
// CHECK21-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK21: cond.true:
|
|
// CHECK21-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK21: cond.false:
|
|
// CHECK21-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK21-NEXT: br label [[COND_END]]
|
|
// CHECK21: cond.end:
|
|
// CHECK21-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
|
|
// CHECK21-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
|
|
// CHECK21-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK21-NEXT: store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK21-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK21: omp.inner.for.cond:
|
|
// CHECK21-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !17
|
|
// CHECK21-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !17
|
|
// CHECK21-NEXT: [[CMP6:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]]
|
|
// CHECK21-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK21: omp.inner.for.body:
|
|
// CHECK21-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !17
|
|
// CHECK21-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400
|
|
// CHECK21-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]
|
|
// CHECK21-NEXT: store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !17
|
|
// CHECK21-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4, !llvm.access.group !17
|
|
// CHECK21-NEXT: [[CONV7:%.*]] = sext i32 [[TMP10]] to i64
|
|
// CHECK21-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !17
|
|
// CHECK21-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !17
|
|
// CHECK21-NEXT: [[MUL8:%.*]] = mul i64 [[TMP11]], [[TMP12]]
|
|
// CHECK21-NEXT: [[ADD:%.*]] = add i64 [[CONV7]], [[MUL8]]
|
|
// CHECK21-NEXT: [[CONV9:%.*]] = trunc i64 [[ADD]] to i32
|
|
// CHECK21-NEXT: store i32 [[CONV9]], i32* [[LIN4]], align 4, !llvm.access.group !17
|
|
// CHECK21-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START3]], align 4, !llvm.access.group !17
|
|
// CHECK21-NEXT: [[CONV10:%.*]] = sext i32 [[TMP13]] to i64
|
|
// CHECK21-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !17
|
|
// CHECK21-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !17
|
|
// CHECK21-NEXT: [[MUL11:%.*]] = mul i64 [[TMP14]], [[TMP15]]
|
|
// CHECK21-NEXT: [[ADD12:%.*]] = add i64 [[CONV10]], [[MUL11]]
|
|
// CHECK21-NEXT: [[CONV13:%.*]] = trunc i64 [[ADD12]] to i32
|
|
// CHECK21-NEXT: store i32 [[CONV13]], i32* [[A5]], align 4, !llvm.access.group !17
|
|
// CHECK21-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 8, !llvm.access.group !17
|
|
// CHECK21-NEXT: [[CONV14:%.*]] = sext i16 [[TMP16]] to i32
|
|
// CHECK21-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1
|
|
// CHECK21-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16
|
|
// CHECK21-NEXT: store i16 [[CONV16]], i16* [[CONV]], align 8, !llvm.access.group !17
|
|
// CHECK21-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK21: omp.body.continue:
|
|
// CHECK21-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK21: omp.inner.for.inc:
|
|
// CHECK21-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !17
|
|
// CHECK21-NEXT: [[ADD17:%.*]] = add i64 [[TMP17]], 1
|
|
// CHECK21-NEXT: store i64 [[ADD17]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !17
|
|
// CHECK21-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]]
|
|
// CHECK21: omp.inner.for.end:
|
|
// CHECK21-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK21: omp.loop.exit:
|
|
// CHECK21-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
|
|
// CHECK21-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK21-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
|
|
// CHECK21-NEXT: br i1 [[TMP19]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
|
|
// CHECK21: .omp.final.then:
|
|
// CHECK21-NEXT: store i64 400, i64* [[IT]], align 8
|
|
// CHECK21-NEXT: br label [[DOTOMP_FINAL_DONE]]
|
|
// CHECK21: .omp.final.done:
|
|
// CHECK21-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK21-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0
|
|
// CHECK21-NEXT: br i1 [[TMP21]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
|
|
// CHECK21: .omp.linear.pu:
|
|
// CHECK21-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4
|
|
// CHECK21-NEXT: [[CONV18:%.*]] = sext i32 [[TMP22]] to i64
|
|
// CHECK21-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
|
|
// CHECK21-NEXT: [[MUL19:%.*]] = mul i64 4, [[TMP23]]
|
|
// CHECK21-NEXT: [[ADD20:%.*]] = add i64 [[CONV18]], [[MUL19]]
|
|
// CHECK21-NEXT: [[CONV21:%.*]] = trunc i64 [[ADD20]] to i32
|
|
// CHECK21-NEXT: store i32 [[CONV21]], i32* [[CONV1]], align 8
|
|
// CHECK21-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTLINEAR_START3]], align 4
|
|
// CHECK21-NEXT: [[CONV22:%.*]] = sext i32 [[TMP24]] to i64
|
|
// CHECK21-NEXT: [[TMP25:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
|
|
// CHECK21-NEXT: [[MUL23:%.*]] = mul i64 4, [[TMP25]]
|
|
// CHECK21-NEXT: [[ADD24:%.*]] = add i64 [[CONV22]], [[MUL23]]
|
|
// CHECK21-NEXT: [[CONV25:%.*]] = trunc i64 [[ADD24]] to i32
|
|
// CHECK21-NEXT: store i32 [[CONV25]], i32* [[CONV2]], align 8
|
|
// CHECK21-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]]
|
|
// CHECK21: .omp.linear.pu.done:
|
|
// CHECK21-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK21-LABEL: define {{[^@]+}}@_Z7get_valv
|
|
// CHECK21-SAME: () #[[ATTR3:[0-9]+]] {
|
|
// CHECK21-NEXT: entry:
|
|
// CHECK21-NEXT: ret i64 0
|
|
//
|
|
//
|
|
// CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116
|
|
// CHECK21-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] {
|
|
// CHECK21-NEXT: entry:
|
|
// CHECK21-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK21-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK21-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK21-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK21-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK21-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
|
|
// CHECK21-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK21-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
|
|
// CHECK21-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
|
|
// CHECK21-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
|
|
// CHECK21-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4
|
|
// CHECK21-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
|
|
// CHECK21-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
|
|
// CHECK21-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
|
|
// CHECK21-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2
|
|
// CHECK21-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
|
|
// CHECK21-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
|
|
// CHECK21-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK21-LABEL: define {{[^@]+}}@.omp_outlined..2
|
|
// CHECK21-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR1]] {
|
|
// CHECK21-NEXT: entry:
|
|
// CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK21-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK21-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK21-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK21-NEXT: [[TMP:%.*]] = alloca i16, align 2
|
|
// CHECK21-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK21-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK21-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK21-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK21-NEXT: [[IT:%.*]] = alloca i16, align 2
|
|
// CHECK21-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK21-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK21-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK21-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
|
|
// CHECK21-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK21-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
|
|
// CHECK21-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK21-NEXT: store i32 3, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK21-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK21-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK21-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK21-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
|
|
// CHECK21-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
|
|
// CHECK21-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK21-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3
|
|
// CHECK21-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK21: cond.true:
|
|
// CHECK21-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK21: cond.false:
|
|
// CHECK21-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK21-NEXT: br label [[COND_END]]
|
|
// CHECK21: cond.end:
|
|
// CHECK21-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
|
|
// CHECK21-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK21-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK21-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK21-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK21: omp.inner.for.cond:
|
|
// CHECK21-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20
|
|
// CHECK21-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !20
|
|
// CHECK21-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
|
|
// CHECK21-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK21: omp.inner.for.body:
|
|
// CHECK21-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20
|
|
// CHECK21-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4
|
|
// CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]]
|
|
// CHECK21-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD]] to i16
|
|
// CHECK21-NEXT: store i16 [[CONV3]], i16* [[IT]], align 2, !llvm.access.group !20
|
|
// CHECK21-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !20
|
|
// CHECK21-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1
|
|
// CHECK21-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 8, !llvm.access.group !20
|
|
// CHECK21-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 8, !llvm.access.group !20
|
|
// CHECK21-NEXT: [[CONV5:%.*]] = sext i16 [[TMP9]] to i32
|
|
// CHECK21-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1
|
|
// CHECK21-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16
|
|
// CHECK21-NEXT: store i16 [[CONV7]], i16* [[CONV1]], align 8, !llvm.access.group !20
|
|
// CHECK21-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK21: omp.body.continue:
|
|
// CHECK21-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK21: omp.inner.for.inc:
|
|
// CHECK21-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20
|
|
// CHECK21-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP10]], 1
|
|
// CHECK21-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20
|
|
// CHECK21-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]]
|
|
// CHECK21: omp.inner.for.end:
|
|
// CHECK21-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK21: omp.loop.exit:
|
|
// CHECK21-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
|
|
// CHECK21-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK21-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
|
|
// CHECK21-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
|
|
// CHECK21: .omp.final.then:
|
|
// CHECK21-NEXT: store i16 22, i16* [[IT]], align 2
|
|
// CHECK21-NEXT: br label [[DOTOMP_FINAL_DONE]]
|
|
// CHECK21: .omp.final.done:
|
|
// CHECK21-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140
|
|
// CHECK21-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
|
|
// CHECK21-NEXT: entry:
|
|
// CHECK21-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK21-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
|
|
// CHECK21-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK21-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8
|
|
// CHECK21-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
|
|
// CHECK21-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
|
|
// CHECK21-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8
|
|
// CHECK21-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8
|
|
// CHECK21-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
|
|
// CHECK21-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK21-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK21-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK21-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK21-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
|
|
// CHECK21-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
|
|
// CHECK21-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8
|
|
// CHECK21-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
|
|
// CHECK21-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
|
|
// CHECK21-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
|
|
// CHECK21-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8
|
|
// CHECK21-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
|
|
// CHECK21-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
|
|
// CHECK21-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK21-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
|
|
// CHECK21-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
|
|
// CHECK21-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
|
|
// CHECK21-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
|
|
// CHECK21-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
|
|
// CHECK21-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
|
|
// CHECK21-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
|
|
// CHECK21-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
|
|
// CHECK21-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
|
|
// CHECK21-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
|
|
// CHECK21-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32*
|
|
// CHECK21-NEXT: store i32 [[TMP8]], i32* [[CONV6]], align 4
|
|
// CHECK21-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
|
|
// CHECK21-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 8
|
|
// CHECK21-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
|
|
// CHECK21-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4
|
|
// CHECK21-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
|
|
// CHECK21-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]])
|
|
// CHECK21-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK21-LABEL: define {{[^@]+}}@.omp_outlined..3
|
|
// CHECK21-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
|
|
// CHECK21-NEXT: entry:
|
|
// CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK21-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK21-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
|
|
// CHECK21-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK21-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8
|
|
// CHECK21-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
|
|
// CHECK21-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
|
|
// CHECK21-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8
|
|
// CHECK21-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8
|
|
// CHECK21-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
|
|
// CHECK21-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK21-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK21-NEXT: [[TMP:%.*]] = alloca i8, align 1
|
|
// CHECK21-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK21-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK21-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK21-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK21-NEXT: [[IT:%.*]] = alloca i8, align 1
|
|
// CHECK21-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK21-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK21-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK21-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
|
|
// CHECK21-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
|
|
// CHECK21-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8
|
|
// CHECK21-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
|
|
// CHECK21-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
|
|
// CHECK21-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
|
|
// CHECK21-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8
|
|
// CHECK21-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
|
|
// CHECK21-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
|
|
// CHECK21-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK21-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
|
|
// CHECK21-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
|
|
// CHECK21-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
|
|
// CHECK21-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
|
|
// CHECK21-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
|
|
// CHECK21-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
|
|
// CHECK21-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
|
|
// CHECK21-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
|
|
// CHECK21-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
|
|
// CHECK21-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK21-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK21-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK21-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK21-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 8
|
|
// CHECK21-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK21-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
|
|
// CHECK21-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
|
|
// CHECK21-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
|
|
// CHECK21: omp.dispatch.cond:
|
|
// CHECK21-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK21-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25
|
|
// CHECK21-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK21: cond.true:
|
|
// CHECK21-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK21: cond.false:
|
|
// CHECK21-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK21-NEXT: br label [[COND_END]]
|
|
// CHECK21: cond.end:
|
|
// CHECK21-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
|
|
// CHECK21-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK21-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK21-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK21-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK21-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK21-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
|
|
// CHECK21-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
|
|
// CHECK21: omp.dispatch.body:
|
|
// CHECK21-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK21: omp.inner.for.cond:
|
|
// CHECK21-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23
|
|
// CHECK21-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !23
|
|
// CHECK21-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
|
|
// CHECK21-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK21: omp.inner.for.body:
|
|
// CHECK21-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23
|
|
// CHECK21-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
|
|
// CHECK21-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]]
|
|
// CHECK21-NEXT: [[CONV8:%.*]] = trunc i32 [[SUB]] to i8
|
|
// CHECK21-NEXT: store i8 [[CONV8]], i8* [[IT]], align 1, !llvm.access.group !23
|
|
// CHECK21-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !23
|
|
// CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1
|
|
// CHECK21-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8, !llvm.access.group !23
|
|
// CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
|
|
// CHECK21-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !23
|
|
// CHECK21-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double
|
|
// CHECK21-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00
|
|
// CHECK21-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float
|
|
// CHECK21-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4, !llvm.access.group !23
|
|
// CHECK21-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3
|
|
// CHECK21-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4, !llvm.access.group !23
|
|
// CHECK21-NEXT: [[CONV13:%.*]] = fpext float [[TMP21]] to double
|
|
// CHECK21-NEXT: [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00
|
|
// CHECK21-NEXT: [[CONV15:%.*]] = fptrunc double [[ADD14]] to float
|
|
// CHECK21-NEXT: store float [[CONV15]], float* [[ARRAYIDX12]], align 4, !llvm.access.group !23
|
|
// CHECK21-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1
|
|
// CHECK21-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX16]], i64 0, i64 2
|
|
// CHECK21-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX17]], align 8, !llvm.access.group !23
|
|
// CHECK21-NEXT: [[ADD18:%.*]] = fadd double [[TMP22]], 1.000000e+00
|
|
// CHECK21-NEXT: store double [[ADD18]], double* [[ARRAYIDX17]], align 8, !llvm.access.group !23
|
|
// CHECK21-NEXT: [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]]
|
|
// CHECK21-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP23]]
|
|
// CHECK21-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX19]], i64 3
|
|
// CHECK21-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX20]], align 8, !llvm.access.group !23
|
|
// CHECK21-NEXT: [[ADD21:%.*]] = fadd double [[TMP24]], 1.000000e+00
|
|
// CHECK21-NEXT: store double [[ADD21]], double* [[ARRAYIDX20]], align 8, !llvm.access.group !23
|
|
// CHECK21-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0
|
|
// CHECK21-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 8, !llvm.access.group !23
|
|
// CHECK21-NEXT: [[ADD22:%.*]] = add nsw i64 [[TMP25]], 1
|
|
// CHECK21-NEXT: store i64 [[ADD22]], i64* [[X]], align 8, !llvm.access.group !23
|
|
// CHECK21-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1
|
|
// CHECK21-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 8, !llvm.access.group !23
|
|
// CHECK21-NEXT: [[CONV23:%.*]] = sext i8 [[TMP26]] to i32
|
|
// CHECK21-NEXT: [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1
|
|
// CHECK21-NEXT: [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8
|
|
// CHECK21-NEXT: store i8 [[CONV25]], i8* [[Y]], align 8, !llvm.access.group !23
|
|
// CHECK21-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK21: omp.body.continue:
|
|
// CHECK21-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK21: omp.inner.for.inc:
|
|
// CHECK21-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23
|
|
// CHECK21-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP27]], 1
|
|
// CHECK21-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23
|
|
// CHECK21-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP24:![0-9]+]]
|
|
// CHECK21: omp.inner.for.end:
|
|
// CHECK21-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
|
|
// CHECK21: omp.dispatch.inc:
|
|
// CHECK21-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK21-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK21-NEXT: [[ADD27:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]
|
|
// CHECK21-NEXT: store i32 [[ADD27]], i32* [[DOTOMP_LB]], align 4
|
|
// CHECK21-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK21-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK21-NEXT: [[ADD28:%.*]] = add nsw i32 [[TMP30]], [[TMP31]]
|
|
// CHECK21-NEXT: store i32 [[ADD28]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK21-NEXT: br label [[OMP_DISPATCH_COND]]
|
|
// CHECK21: omp.dispatch.end:
|
|
// CHECK21-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]])
|
|
// CHECK21-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK21-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0
|
|
// CHECK21-NEXT: br i1 [[TMP33]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
|
|
// CHECK21: .omp.final.then:
|
|
// CHECK21-NEXT: store i8 96, i8* [[IT]], align 1
|
|
// CHECK21-NEXT: br label [[DOTOMP_FINAL_DONE]]
|
|
// CHECK21: .omp.final.done:
|
|
// CHECK21-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195
|
|
// CHECK21-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
|
|
// CHECK21-NEXT: entry:
|
|
// CHECK21-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK21-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK21-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK21-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
|
|
// CHECK21-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK21-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK21-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK21-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK21-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
|
|
// CHECK21-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
|
|
// CHECK21-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
|
|
// CHECK21-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK21-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
|
|
// CHECK21-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
|
|
// CHECK21-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
|
|
// CHECK21-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
|
|
// CHECK21-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
|
|
// CHECK21-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4
|
|
// CHECK21-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
|
|
// CHECK21-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
|
|
// CHECK21-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
|
|
// CHECK21-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2
|
|
// CHECK21-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
|
|
// CHECK21-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 8
|
|
// CHECK21-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
|
|
// CHECK21-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1
|
|
// CHECK21-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
|
|
// CHECK21-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]])
|
|
// CHECK21-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK21-LABEL: define {{[^@]+}}@.omp_outlined..4
|
|
// CHECK21-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {
|
|
// CHECK21-NEXT: entry:
|
|
// CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK21-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK21-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK21-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK21-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
|
|
// CHECK21-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK21-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK21-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK21-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK21-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK21-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
|
|
// CHECK21-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
|
|
// CHECK21-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
|
|
// CHECK21-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK21-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
|
|
// CHECK21-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
|
|
// CHECK21-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
|
|
// CHECK21-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214
|
|
// CHECK21-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
|
|
// CHECK21-NEXT: entry:
|
|
// CHECK21-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
|
|
// CHECK21-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK21-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK21-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
|
|
// CHECK21-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8
|
|
// CHECK21-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK21-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK21-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK21-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
|
|
// CHECK21-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK21-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4
|
|
// CHECK21-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]])
|
|
// CHECK21-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK21-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
|
|
// CHECK21-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
|
|
// CHECK21-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
|
|
// CHECK21-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8
|
|
// CHECK21-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
|
|
// CHECK21-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK21-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
|
|
// CHECK21-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
|
|
// CHECK21-NEXT: [[TMP3:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
|
|
// CHECK21-NEXT: [[TMP4:%.*]] = load i16*, i16** [[C_ADDR]], align 8
|
|
// CHECK21-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
|
|
// CHECK21-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV]], align 8
|
|
// CHECK21-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i32*
|
|
// CHECK21-NEXT: store i32 [[TMP5]], i32* [[CONV4]], align 4
|
|
// CHECK21-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8
|
|
// CHECK21-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV3]], align 8
|
|
// CHECK21-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP7]] to i1
|
|
// CHECK21-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
|
|
// CHECK21-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
|
|
// CHECK21-NEXT: store i8 [[FROMBOOL]], i8* [[CONV5]], align 1
|
|
// CHECK21-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
|
|
// CHECK21-NEXT: [[TMP9:%.*]] = load i8, i8* [[CONV3]], align 8
|
|
// CHECK21-NEXT: [[TOBOOL6:%.*]] = trunc i8 [[TMP9]] to i1
|
|
// CHECK21-NEXT: br i1 [[TOBOOL6]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
|
|
// CHECK21: omp_if.then:
|
|
// CHECK21-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP6]], i64 [[TMP2]], i64 [[TMP3]], i16* [[TMP4]], i64 [[TMP8]])
|
|
// CHECK21-NEXT: br label [[OMP_IF_END:%.*]]
|
|
// CHECK21: omp_if.else:
|
|
// CHECK21-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]])
|
|
// CHECK21-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
|
|
// CHECK21-NEXT: call void @.omp_outlined..5(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]], i64 [[TMP6]], i64 [[TMP2]], i64 [[TMP3]], i16* [[TMP4]], i64 [[TMP8]]) #[[ATTR2:[0-9]+]]
|
|
// CHECK21-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]])
|
|
// CHECK21-NEXT: br label [[OMP_IF_END]]
|
|
// CHECK21: omp_if.end:
|
|
// CHECK21-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK21-LABEL: define {{[^@]+}}@.omp_outlined..5
|
|
// CHECK21-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
|
|
// CHECK21-NEXT: entry:
|
|
// CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK21-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
|
|
// CHECK21-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK21-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK21-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
|
|
// CHECK21-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8
|
|
// CHECK21-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK21-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
|
|
// CHECK21-NEXT: [[TMP:%.*]] = alloca i64, align 8
|
|
// CHECK21-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
|
|
// CHECK21-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
|
|
// CHECK21-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
|
|
// CHECK21-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK21-NEXT: [[IT:%.*]] = alloca i64, align 8
|
|
// CHECK21-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK21-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK21-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK21-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
|
|
// CHECK21-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
|
|
// CHECK21-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
|
|
// CHECK21-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8
|
|
// CHECK21-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
|
|
// CHECK21-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK21-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
|
|
// CHECK21-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
|
|
// CHECK21-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
|
|
// CHECK21-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
|
|
// CHECK21-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
|
|
// CHECK21-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK21-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK21-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
|
|
// CHECK21-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK21-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV3]], align 8
|
|
// CHECK21-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1
|
|
// CHECK21-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
|
|
// CHECK21: omp_if.then:
|
|
// CHECK21-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK21-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4
|
|
// CHECK21-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
|
|
// CHECK21-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK21-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP7]], 3
|
|
// CHECK21-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK21: cond.true:
|
|
// CHECK21-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK21: cond.false:
|
|
// CHECK21-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK21-NEXT: br label [[COND_END]]
|
|
// CHECK21: cond.end:
|
|
// CHECK21-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ]
|
|
// CHECK21-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
|
|
// CHECK21-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK21-NEXT: store i64 [[TMP9]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK21-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK21: omp.inner.for.cond:
|
|
// CHECK21-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !26
|
|
// CHECK21-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !26
|
|
// CHECK21-NEXT: [[CMP4:%.*]] = icmp ule i64 [[TMP10]], [[TMP11]]
|
|
// CHECK21-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK21: omp.inner.for.body:
|
|
// CHECK21-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !26
|
|
// CHECK21-NEXT: [[MUL:%.*]] = mul i64 [[TMP12]], 400
|
|
// CHECK21-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]
|
|
// CHECK21-NEXT: store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !26
|
|
// CHECK21-NEXT: [[TMP13:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !26
|
|
// CHECK21-NEXT: [[CONV5:%.*]] = sitofp i32 [[TMP13]] to double
|
|
// CHECK21-NEXT: [[ADD:%.*]] = fadd double [[CONV5]], 1.500000e+00
|
|
// CHECK21-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
|
|
// CHECK21-NEXT: store double [[ADD]], double* [[A]], align 8, !nontemporal !27, !llvm.access.group !26
|
|
// CHECK21-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
|
|
// CHECK21-NEXT: [[TMP14:%.*]] = load double, double* [[A6]], align 8, !nontemporal !27, !llvm.access.group !26
|
|
// CHECK21-NEXT: [[INC:%.*]] = fadd double [[TMP14]], 1.000000e+00
|
|
// CHECK21-NEXT: store double [[INC]], double* [[A6]], align 8, !nontemporal !27, !llvm.access.group !26
|
|
// CHECK21-NEXT: [[CONV7:%.*]] = fptosi double [[INC]] to i16
|
|
// CHECK21-NEXT: [[TMP15:%.*]] = mul nsw i64 1, [[TMP2]]
|
|
// CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP15]]
|
|
// CHECK21-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
|
|
// CHECK21-NEXT: store i16 [[CONV7]], i16* [[ARRAYIDX8]], align 2, !llvm.access.group !26
|
|
// CHECK21-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK21: omp.body.continue:
|
|
// CHECK21-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK21: omp.inner.for.inc:
|
|
// CHECK21-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !26
|
|
// CHECK21-NEXT: [[ADD9:%.*]] = add i64 [[TMP16]], 1
|
|
// CHECK21-NEXT: store i64 [[ADD9]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !26
|
|
// CHECK21-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]]
|
|
// CHECK21: omp.inner.for.end:
|
|
// CHECK21-NEXT: br label [[OMP_IF_END:%.*]]
|
|
// CHECK21: omp_if.else:
|
|
// CHECK21-NEXT: [[TMP17:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK21-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP17]], align 4
|
|
// CHECK21-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP18]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
|
|
// CHECK21-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK21-NEXT: [[CMP10:%.*]] = icmp ugt i64 [[TMP19]], 3
|
|
// CHECK21-NEXT: br i1 [[CMP10]], label [[COND_TRUE11:%.*]], label [[COND_FALSE12:%.*]]
|
|
// CHECK21: cond.true11:
|
|
// CHECK21-NEXT: br label [[COND_END13:%.*]]
|
|
// CHECK21: cond.false12:
|
|
// CHECK21-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK21-NEXT: br label [[COND_END13]]
|
|
// CHECK21: cond.end13:
|
|
// CHECK21-NEXT: [[COND14:%.*]] = phi i64 [ 3, [[COND_TRUE11]] ], [ [[TMP20]], [[COND_FALSE12]] ]
|
|
// CHECK21-NEXT: store i64 [[COND14]], i64* [[DOTOMP_UB]], align 8
|
|
// CHECK21-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK21-NEXT: store i64 [[TMP21]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK21-NEXT: br label [[OMP_INNER_FOR_COND15:%.*]]
|
|
// CHECK21: omp.inner.for.cond15:
|
|
// CHECK21-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK21-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK21-NEXT: [[CMP16:%.*]] = icmp ule i64 [[TMP22]], [[TMP23]]
|
|
// CHECK21-NEXT: br i1 [[CMP16]], label [[OMP_INNER_FOR_BODY17:%.*]], label [[OMP_INNER_FOR_END31:%.*]]
|
|
// CHECK21: omp.inner.for.body17:
|
|
// CHECK21-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK21-NEXT: [[MUL18:%.*]] = mul i64 [[TMP24]], 400
|
|
// CHECK21-NEXT: [[SUB19:%.*]] = sub i64 2000, [[MUL18]]
|
|
// CHECK21-NEXT: store i64 [[SUB19]], i64* [[IT]], align 8
|
|
// CHECK21-NEXT: [[TMP25:%.*]] = load i32, i32* [[CONV]], align 8
|
|
// CHECK21-NEXT: [[CONV20:%.*]] = sitofp i32 [[TMP25]] to double
|
|
// CHECK21-NEXT: [[ADD21:%.*]] = fadd double [[CONV20]], 1.500000e+00
|
|
// CHECK21-NEXT: [[A22:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
|
|
// CHECK21-NEXT: store double [[ADD21]], double* [[A22]], align 8
|
|
// CHECK21-NEXT: [[A23:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
|
|
// CHECK21-NEXT: [[TMP26:%.*]] = load double, double* [[A23]], align 8
|
|
// CHECK21-NEXT: [[INC24:%.*]] = fadd double [[TMP26]], 1.000000e+00
|
|
// CHECK21-NEXT: store double [[INC24]], double* [[A23]], align 8
|
|
// CHECK21-NEXT: [[CONV25:%.*]] = fptosi double [[INC24]] to i16
|
|
// CHECK21-NEXT: [[TMP27:%.*]] = mul nsw i64 1, [[TMP2]]
|
|
// CHECK21-NEXT: [[ARRAYIDX26:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP27]]
|
|
// CHECK21-NEXT: [[ARRAYIDX27:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX26]], i64 1
|
|
// CHECK21-NEXT: store i16 [[CONV25]], i16* [[ARRAYIDX27]], align 2
|
|
// CHECK21-NEXT: br label [[OMP_BODY_CONTINUE28:%.*]]
|
|
// CHECK21: omp.body.continue28:
|
|
// CHECK21-NEXT: br label [[OMP_INNER_FOR_INC29:%.*]]
|
|
// CHECK21: omp.inner.for.inc29:
|
|
// CHECK21-NEXT: [[TMP28:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK21-NEXT: [[ADD30:%.*]] = add i64 [[TMP28]], 1
|
|
// CHECK21-NEXT: store i64 [[ADD30]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK21-NEXT: br label [[OMP_INNER_FOR_COND15]], !llvm.loop [[LOOP30:![0-9]+]]
|
|
// CHECK21: omp.inner.for.end31:
|
|
// CHECK21-NEXT: br label [[OMP_IF_END]]
|
|
// CHECK21: omp_if.end:
|
|
// CHECK21-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK21: omp.loop.exit:
|
|
// CHECK21-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK21-NEXT: [[TMP30:%.*]] = load i32, i32* [[TMP29]], align 4
|
|
// CHECK21-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP30]])
|
|
// CHECK21-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK21-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0
|
|
// CHECK21-NEXT: br i1 [[TMP32]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
|
|
// CHECK21: .omp.final.then:
|
|
// CHECK21-NEXT: store i64 400, i64* [[IT]], align 8
|
|
// CHECK21-NEXT: br label [[DOTOMP_FINAL_DONE]]
|
|
// CHECK21: .omp.final.done:
|
|
// CHECK21-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178
|
|
// CHECK21-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
|
|
// CHECK21-NEXT: entry:
|
|
// CHECK21-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK21-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK21-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
|
|
// CHECK21-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK21-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK21-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK21-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
|
|
// CHECK21-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
|
|
// CHECK21-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK21-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
|
|
// CHECK21-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
|
|
// CHECK21-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
|
|
// CHECK21-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
|
|
// CHECK21-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4
|
|
// CHECK21-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
|
|
// CHECK21-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
|
|
// CHECK21-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
|
|
// CHECK21-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
|
|
// CHECK21-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
|
|
// CHECK21-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]])
|
|
// CHECK21-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK21-LABEL: define {{[^@]+}}@.omp_outlined..6
|
|
// CHECK21-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {
|
|
// CHECK21-NEXT: entry:
|
|
// CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK21-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK21-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK21-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
|
|
// CHECK21-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
|
|
// CHECK21-NEXT: [[TMP:%.*]] = alloca i64, align 8
|
|
// CHECK21-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
|
|
// CHECK21-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
|
|
// CHECK21-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
|
|
// CHECK21-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK21-NEXT: [[I:%.*]] = alloca i64, align 8
|
|
// CHECK21-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK21-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK21-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK21-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
|
|
// CHECK21-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
|
|
// CHECK21-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK21-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
|
|
// CHECK21-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
|
|
// CHECK21-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK21-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK21-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
|
|
// CHECK21-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK21-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK21-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
|
|
// CHECK21-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
|
|
// CHECK21-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK21-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6
|
|
// CHECK21-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK21: cond.true:
|
|
// CHECK21-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK21: cond.false:
|
|
// CHECK21-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK21-NEXT: br label [[COND_END]]
|
|
// CHECK21: cond.end:
|
|
// CHECK21-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
|
|
// CHECK21-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
|
|
// CHECK21-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK21-NEXT: store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK21-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK21: omp.inner.for.cond:
|
|
// CHECK21-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !32
|
|
// CHECK21-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !32
|
|
// CHECK21-NEXT: [[CMP2:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]]
|
|
// CHECK21-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK21: omp.inner.for.body:
|
|
// CHECK21-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !32
|
|
// CHECK21-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3
|
|
// CHECK21-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
|
|
// CHECK21-NEXT: store i64 [[ADD]], i64* [[I]], align 8, !llvm.access.group !32
|
|
// CHECK21-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !32
|
|
// CHECK21-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1
|
|
// CHECK21-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 8, !llvm.access.group !32
|
|
// CHECK21-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 8, !llvm.access.group !32
|
|
// CHECK21-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32
|
|
// CHECK21-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
|
|
// CHECK21-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
|
|
// CHECK21-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 8, !llvm.access.group !32
|
|
// CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
|
|
// CHECK21-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !32
|
|
// CHECK21-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1
|
|
// CHECK21-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !32
|
|
// CHECK21-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK21: omp.body.continue:
|
|
// CHECK21-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK21: omp.inner.for.inc:
|
|
// CHECK21-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !32
|
|
// CHECK21-NEXT: [[ADD8:%.*]] = add nsw i64 [[TMP12]], 1
|
|
// CHECK21-NEXT: store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !32
|
|
// CHECK21-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP33:![0-9]+]]
|
|
// CHECK21: omp.inner.for.end:
|
|
// CHECK21-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK21: omp.loop.exit:
|
|
// CHECK21-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
|
|
// CHECK21-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK21-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
|
|
// CHECK21-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
|
|
// CHECK21: .omp.final.then:
|
|
// CHECK21-NEXT: store i64 11, i64* [[I]], align 8
|
|
// CHECK21-NEXT: br label [[DOTOMP_FINAL_DONE]]
|
|
// CHECK21: .omp.final.done:
|
|
// CHECK21-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK22-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96
|
|
// CHECK22-SAME: () #[[ATTR0:[0-9]+]] {
|
|
// CHECK22-NEXT: entry:
|
|
// CHECK22-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
|
|
// CHECK22-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK22-LABEL: define {{[^@]+}}@.omp_outlined.
|
|
// CHECK22-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] {
|
|
// CHECK22-NEXT: entry:
|
|
// CHECK22-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK22-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK22-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK22-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK22-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK22-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK22-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK22-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK22-NEXT: [[I:%.*]] = alloca i32, align 4
|
|
// CHECK22-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK22-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK22-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK22-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK22-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK22-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK22-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK22-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
|
|
// CHECK22-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
|
|
// CHECK22-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK22-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5
|
|
// CHECK22-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK22: cond.true:
|
|
// CHECK22-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK22: cond.false:
|
|
// CHECK22-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK22-NEXT: br label [[COND_END]]
|
|
// CHECK22: cond.end:
|
|
// CHECK22-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
|
|
// CHECK22-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK22-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK22-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK22-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK22: omp.inner.for.cond:
|
|
// CHECK22-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
|
|
// CHECK22-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !11
|
|
// CHECK22-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
|
|
// CHECK22-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK22: omp.inner.for.body:
|
|
// CHECK22-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
|
|
// CHECK22-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5
|
|
// CHECK22-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]]
|
|
// CHECK22-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11
|
|
// CHECK22-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK22: omp.body.continue:
|
|
// CHECK22-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK22: omp.inner.for.inc:
|
|
// CHECK22-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
|
|
// CHECK22-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
|
|
// CHECK22-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
|
|
// CHECK22-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]
|
|
// CHECK22: omp.inner.for.end:
|
|
// CHECK22-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK22: omp.loop.exit:
|
|
// CHECK22-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
|
|
// CHECK22-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK22-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0
|
|
// CHECK22-NEXT: br i1 [[TMP10]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
|
|
// CHECK22: .omp.final.then:
|
|
// CHECK22-NEXT: store i32 33, i32* [[I]], align 4
|
|
// CHECK22-NEXT: br label [[DOTOMP_FINAL_DONE]]
|
|
// CHECK22: .omp.final.done:
|
|
// CHECK22-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK22-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108
|
|
// CHECK22-SAME: (i64 [[AA:%.*]], i64 [[LIN:%.*]], i64 [[A:%.*]]) #[[ATTR0]] {
|
|
// CHECK22-NEXT: entry:
|
|
// CHECK22-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK22-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK22-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK22-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK22-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK22-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK22-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
|
|
// CHECK22-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8
|
|
// CHECK22-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK22-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
|
|
// CHECK22-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32*
|
|
// CHECK22-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK22-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8
|
|
// CHECK22-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
|
|
// CHECK22-NEXT: store i16 [[TMP0]], i16* [[CONV3]], align 2
|
|
// CHECK22-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
|
|
// CHECK22-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8
|
|
// CHECK22-NEXT: [[CONV4:%.*]] = bitcast i64* [[LIN_CASTED]] to i32*
|
|
// CHECK22-NEXT: store i32 [[TMP2]], i32* [[CONV4]], align 4
|
|
// CHECK22-NEXT: [[TMP3:%.*]] = load i64, i64* [[LIN_CASTED]], align 8
|
|
// CHECK22-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV2]], align 8
|
|
// CHECK22-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
|
|
// CHECK22-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4
|
|
// CHECK22-NEXT: [[TMP5:%.*]] = load i64, i64* [[A_CASTED]], align 8
|
|
// CHECK22-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]])
|
|
// CHECK22-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK22-LABEL: define {{[^@]+}}@.omp_outlined..1
|
|
// CHECK22-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]], i64 [[LIN:%.*]], i64 [[A:%.*]]) #[[ATTR1]] {
|
|
// CHECK22-NEXT: entry:
|
|
// CHECK22-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK22-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK22-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK22-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK22-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK22-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
|
|
// CHECK22-NEXT: [[TMP:%.*]] = alloca i64, align 8
|
|
// CHECK22-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4
|
|
// CHECK22-NEXT: [[DOTLINEAR_START3:%.*]] = alloca i32, align 4
|
|
// CHECK22-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8
|
|
// CHECK22-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
|
|
// CHECK22-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
|
|
// CHECK22-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
|
|
// CHECK22-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK22-NEXT: [[IT:%.*]] = alloca i64, align 8
|
|
// CHECK22-NEXT: [[LIN4:%.*]] = alloca i32, align 4
|
|
// CHECK22-NEXT: [[A5:%.*]] = alloca i32, align 4
|
|
// CHECK22-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK22-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK22-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
|
|
// CHECK22-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8
|
|
// CHECK22-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK22-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
|
|
// CHECK22-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32*
|
|
// CHECK22-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK22-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV1]], align 8
|
|
// CHECK22-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4
|
|
// CHECK22-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 8
|
|
// CHECK22-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START3]], align 4
|
|
// CHECK22-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() #[[ATTR5:[0-9]+]]
|
|
// CHECK22-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8
|
|
// CHECK22-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK22-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK22-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
|
|
// CHECK22-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK22-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK22-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
|
|
// CHECK22-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP3]])
|
|
// CHECK22-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
|
|
// CHECK22-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK22-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3
|
|
// CHECK22-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK22: cond.true:
|
|
// CHECK22-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK22: cond.false:
|
|
// CHECK22-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK22-NEXT: br label [[COND_END]]
|
|
// CHECK22: cond.end:
|
|
// CHECK22-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
|
|
// CHECK22-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
|
|
// CHECK22-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK22-NEXT: store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK22-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK22: omp.inner.for.cond:
|
|
// CHECK22-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !17
|
|
// CHECK22-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !17
|
|
// CHECK22-NEXT: [[CMP6:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]]
|
|
// CHECK22-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK22: omp.inner.for.body:
|
|
// CHECK22-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !17
|
|
// CHECK22-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400
|
|
// CHECK22-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]
|
|
// CHECK22-NEXT: store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !17
|
|
// CHECK22-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4, !llvm.access.group !17
|
|
// CHECK22-NEXT: [[CONV7:%.*]] = sext i32 [[TMP10]] to i64
|
|
// CHECK22-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !17
|
|
// CHECK22-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !17
|
|
// CHECK22-NEXT: [[MUL8:%.*]] = mul i64 [[TMP11]], [[TMP12]]
|
|
// CHECK22-NEXT: [[ADD:%.*]] = add i64 [[CONV7]], [[MUL8]]
|
|
// CHECK22-NEXT: [[CONV9:%.*]] = trunc i64 [[ADD]] to i32
|
|
// CHECK22-NEXT: store i32 [[CONV9]], i32* [[LIN4]], align 4, !llvm.access.group !17
|
|
// CHECK22-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START3]], align 4, !llvm.access.group !17
|
|
// CHECK22-NEXT: [[CONV10:%.*]] = sext i32 [[TMP13]] to i64
|
|
// CHECK22-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !17
|
|
// CHECK22-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !17
|
|
// CHECK22-NEXT: [[MUL11:%.*]] = mul i64 [[TMP14]], [[TMP15]]
|
|
// CHECK22-NEXT: [[ADD12:%.*]] = add i64 [[CONV10]], [[MUL11]]
|
|
// CHECK22-NEXT: [[CONV13:%.*]] = trunc i64 [[ADD12]] to i32
|
|
// CHECK22-NEXT: store i32 [[CONV13]], i32* [[A5]], align 4, !llvm.access.group !17
|
|
// CHECK22-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 8, !llvm.access.group !17
|
|
// CHECK22-NEXT: [[CONV14:%.*]] = sext i16 [[TMP16]] to i32
|
|
// CHECK22-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1
|
|
// CHECK22-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16
|
|
// CHECK22-NEXT: store i16 [[CONV16]], i16* [[CONV]], align 8, !llvm.access.group !17
|
|
// CHECK22-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK22: omp.body.continue:
|
|
// CHECK22-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK22: omp.inner.for.inc:
|
|
// CHECK22-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !17
|
|
// CHECK22-NEXT: [[ADD17:%.*]] = add i64 [[TMP17]], 1
|
|
// CHECK22-NEXT: store i64 [[ADD17]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !17
|
|
// CHECK22-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]]
|
|
// CHECK22: omp.inner.for.end:
|
|
// CHECK22-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK22: omp.loop.exit:
|
|
// CHECK22-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
|
|
// CHECK22-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK22-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
|
|
// CHECK22-NEXT: br i1 [[TMP19]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
|
|
// CHECK22: .omp.final.then:
|
|
// CHECK22-NEXT: store i64 400, i64* [[IT]], align 8
|
|
// CHECK22-NEXT: br label [[DOTOMP_FINAL_DONE]]
|
|
// CHECK22: .omp.final.done:
|
|
// CHECK22-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK22-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0
|
|
// CHECK22-NEXT: br i1 [[TMP21]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
|
|
// CHECK22: .omp.linear.pu:
|
|
// CHECK22-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4
|
|
// CHECK22-NEXT: [[CONV18:%.*]] = sext i32 [[TMP22]] to i64
|
|
// CHECK22-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
|
|
// CHECK22-NEXT: [[MUL19:%.*]] = mul i64 4, [[TMP23]]
|
|
// CHECK22-NEXT: [[ADD20:%.*]] = add i64 [[CONV18]], [[MUL19]]
|
|
// CHECK22-NEXT: [[CONV21:%.*]] = trunc i64 [[ADD20]] to i32
|
|
// CHECK22-NEXT: store i32 [[CONV21]], i32* [[CONV1]], align 8
|
|
// CHECK22-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTLINEAR_START3]], align 4
|
|
// CHECK22-NEXT: [[CONV22:%.*]] = sext i32 [[TMP24]] to i64
|
|
// CHECK22-NEXT: [[TMP25:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
|
|
// CHECK22-NEXT: [[MUL23:%.*]] = mul i64 4, [[TMP25]]
|
|
// CHECK22-NEXT: [[ADD24:%.*]] = add i64 [[CONV22]], [[MUL23]]
|
|
// CHECK22-NEXT: [[CONV25:%.*]] = trunc i64 [[ADD24]] to i32
|
|
// CHECK22-NEXT: store i32 [[CONV25]], i32* [[CONV2]], align 8
|
|
// CHECK22-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]]
|
|
// CHECK22: .omp.linear.pu.done:
|
|
// CHECK22-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK22-LABEL: define {{[^@]+}}@_Z7get_valv
|
|
// CHECK22-SAME: () #[[ATTR3:[0-9]+]] {
|
|
// CHECK22-NEXT: entry:
|
|
// CHECK22-NEXT: ret i64 0
|
|
//
|
|
//
|
|
// CHECK22-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116
|
|
// CHECK22-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] {
|
|
// CHECK22-NEXT: entry:
|
|
// CHECK22-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK22-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK22-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK22-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK22-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK22-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
|
|
// CHECK22-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK22-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
|
|
// CHECK22-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
|
|
// CHECK22-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
|
|
// CHECK22-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4
|
|
// CHECK22-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
|
|
// CHECK22-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
|
|
// CHECK22-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
|
|
// CHECK22-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2
|
|
// CHECK22-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
|
|
// CHECK22-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
|
|
// CHECK22-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK22-LABEL: define {{[^@]+}}@.omp_outlined..2
|
|
// CHECK22-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR1]] {
|
|
// CHECK22-NEXT: entry:
|
|
// CHECK22-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK22-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK22-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK22-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK22-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK22-NEXT: [[TMP:%.*]] = alloca i16, align 2
|
|
// CHECK22-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK22-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK22-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK22-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK22-NEXT: [[IT:%.*]] = alloca i16, align 2
|
|
// CHECK22-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK22-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK22-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK22-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
|
|
// CHECK22-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK22-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
|
|
// CHECK22-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK22-NEXT: store i32 3, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK22-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK22-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK22-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK22-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
|
|
// CHECK22-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
|
|
// CHECK22-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK22-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3
|
|
// CHECK22-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK22: cond.true:
|
|
// CHECK22-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK22: cond.false:
|
|
// CHECK22-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK22-NEXT: br label [[COND_END]]
|
|
// CHECK22: cond.end:
|
|
// CHECK22-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
|
|
// CHECK22-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK22-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK22-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK22-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK22: omp.inner.for.cond:
|
|
// CHECK22-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20
|
|
// CHECK22-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !20
|
|
// CHECK22-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
|
|
// CHECK22-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK22: omp.inner.for.body:
|
|
// CHECK22-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20
|
|
// CHECK22-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4
|
|
// CHECK22-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]]
|
|
// CHECK22-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD]] to i16
|
|
// CHECK22-NEXT: store i16 [[CONV3]], i16* [[IT]], align 2, !llvm.access.group !20
|
|
// CHECK22-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !20
|
|
// CHECK22-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1
|
|
// CHECK22-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 8, !llvm.access.group !20
|
|
// CHECK22-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 8, !llvm.access.group !20
|
|
// CHECK22-NEXT: [[CONV5:%.*]] = sext i16 [[TMP9]] to i32
|
|
// CHECK22-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1
|
|
// CHECK22-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16
|
|
// CHECK22-NEXT: store i16 [[CONV7]], i16* [[CONV1]], align 8, !llvm.access.group !20
|
|
// CHECK22-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK22: omp.body.continue:
|
|
// CHECK22-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK22: omp.inner.for.inc:
|
|
// CHECK22-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20
|
|
// CHECK22-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP10]], 1
|
|
// CHECK22-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20
|
|
// CHECK22-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]]
|
|
// CHECK22: omp.inner.for.end:
|
|
// CHECK22-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK22: omp.loop.exit:
|
|
// CHECK22-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
|
|
// CHECK22-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK22-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
|
|
// CHECK22-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
|
|
// CHECK22: .omp.final.then:
|
|
// CHECK22-NEXT: store i16 22, i16* [[IT]], align 2
|
|
// CHECK22-NEXT: br label [[DOTOMP_FINAL_DONE]]
|
|
// CHECK22: .omp.final.done:
|
|
// CHECK22-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK22-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140
|
|
// CHECK22-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
|
|
// CHECK22-NEXT: entry:
|
|
// CHECK22-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK22-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
|
|
// CHECK22-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK22-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8
|
|
// CHECK22-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
|
|
// CHECK22-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
|
|
// CHECK22-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8
|
|
// CHECK22-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8
|
|
// CHECK22-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
|
|
// CHECK22-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK22-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK22-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK22-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK22-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
|
|
// CHECK22-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
|
|
// CHECK22-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8
|
|
// CHECK22-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
|
|
// CHECK22-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
|
|
// CHECK22-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
|
|
// CHECK22-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8
|
|
// CHECK22-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
|
|
// CHECK22-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
|
|
// CHECK22-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK22-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
|
|
// CHECK22-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
|
|
// CHECK22-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
|
|
// CHECK22-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
|
|
// CHECK22-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
|
|
// CHECK22-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
|
|
// CHECK22-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
|
|
// CHECK22-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
|
|
// CHECK22-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
|
|
// CHECK22-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
|
|
// CHECK22-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32*
|
|
// CHECK22-NEXT: store i32 [[TMP8]], i32* [[CONV6]], align 4
|
|
// CHECK22-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
|
|
// CHECK22-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 8
|
|
// CHECK22-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
|
|
// CHECK22-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4
|
|
// CHECK22-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
|
|
// CHECK22-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]])
|
|
// CHECK22-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK22-LABEL: define {{[^@]+}}@.omp_outlined..3
|
|
// CHECK22-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
|
|
// CHECK22-NEXT: entry:
|
|
// CHECK22-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK22-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK22-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK22-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
|
|
// CHECK22-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK22-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8
|
|
// CHECK22-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
|
|
// CHECK22-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
|
|
// CHECK22-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8
|
|
// CHECK22-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8
|
|
// CHECK22-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
|
|
// CHECK22-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK22-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK22-NEXT: [[TMP:%.*]] = alloca i8, align 1
|
|
// CHECK22-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK22-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK22-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK22-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK22-NEXT: [[IT:%.*]] = alloca i8, align 1
|
|
// CHECK22-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK22-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK22-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK22-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
|
|
// CHECK22-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
|
|
// CHECK22-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8
|
|
// CHECK22-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
|
|
// CHECK22-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
|
|
// CHECK22-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
|
|
// CHECK22-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8
|
|
// CHECK22-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
|
|
// CHECK22-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
|
|
// CHECK22-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK22-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
|
|
// CHECK22-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
|
|
// CHECK22-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
|
|
// CHECK22-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
|
|
// CHECK22-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
|
|
// CHECK22-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
|
|
// CHECK22-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
|
|
// CHECK22-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
|
|
// CHECK22-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
|
|
// CHECK22-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK22-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK22-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK22-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK22-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 8
|
|
// CHECK22-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK22-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
|
|
// CHECK22-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
|
|
// CHECK22-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
|
|
// CHECK22: omp.dispatch.cond:
|
|
// CHECK22-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK22-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25
|
|
// CHECK22-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK22: cond.true:
|
|
// CHECK22-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK22: cond.false:
|
|
// CHECK22-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK22-NEXT: br label [[COND_END]]
|
|
// CHECK22: cond.end:
|
|
// CHECK22-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
|
|
// CHECK22-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK22-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK22-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK22-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK22-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK22-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
|
|
// CHECK22-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
|
|
// CHECK22: omp.dispatch.body:
|
|
// CHECK22-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK22: omp.inner.for.cond:
|
|
// CHECK22-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23
|
|
// CHECK22-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !23
|
|
// CHECK22-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
|
|
// CHECK22-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK22: omp.inner.for.body:
|
|
// CHECK22-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23
|
|
// CHECK22-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
|
|
// CHECK22-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]]
|
|
// CHECK22-NEXT: [[CONV8:%.*]] = trunc i32 [[SUB]] to i8
|
|
// CHECK22-NEXT: store i8 [[CONV8]], i8* [[IT]], align 1, !llvm.access.group !23
|
|
// CHECK22-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !23
|
|
// CHECK22-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1
|
|
// CHECK22-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8, !llvm.access.group !23
|
|
// CHECK22-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
|
|
// CHECK22-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !23
|
|
// CHECK22-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double
|
|
// CHECK22-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00
|
|
// CHECK22-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float
|
|
// CHECK22-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4, !llvm.access.group !23
|
|
// CHECK22-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3
|
|
// CHECK22-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4, !llvm.access.group !23
|
|
// CHECK22-NEXT: [[CONV13:%.*]] = fpext float [[TMP21]] to double
|
|
// CHECK22-NEXT: [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00
|
|
// CHECK22-NEXT: [[CONV15:%.*]] = fptrunc double [[ADD14]] to float
|
|
// CHECK22-NEXT: store float [[CONV15]], float* [[ARRAYIDX12]], align 4, !llvm.access.group !23
|
|
// CHECK22-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1
|
|
// CHECK22-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX16]], i64 0, i64 2
|
|
// CHECK22-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX17]], align 8, !llvm.access.group !23
|
|
// CHECK22-NEXT: [[ADD18:%.*]] = fadd double [[TMP22]], 1.000000e+00
|
|
// CHECK22-NEXT: store double [[ADD18]], double* [[ARRAYIDX17]], align 8, !llvm.access.group !23
|
|
// CHECK22-NEXT: [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]]
|
|
// CHECK22-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP23]]
|
|
// CHECK22-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX19]], i64 3
|
|
// CHECK22-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX20]], align 8, !llvm.access.group !23
|
|
// CHECK22-NEXT: [[ADD21:%.*]] = fadd double [[TMP24]], 1.000000e+00
|
|
// CHECK22-NEXT: store double [[ADD21]], double* [[ARRAYIDX20]], align 8, !llvm.access.group !23
|
|
// CHECK22-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0
|
|
// CHECK22-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 8, !llvm.access.group !23
|
|
// CHECK22-NEXT: [[ADD22:%.*]] = add nsw i64 [[TMP25]], 1
|
|
// CHECK22-NEXT: store i64 [[ADD22]], i64* [[X]], align 8, !llvm.access.group !23
|
|
// CHECK22-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1
|
|
// CHECK22-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 8, !llvm.access.group !23
|
|
// CHECK22-NEXT: [[CONV23:%.*]] = sext i8 [[TMP26]] to i32
|
|
// CHECK22-NEXT: [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1
|
|
// CHECK22-NEXT: [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8
|
|
// CHECK22-NEXT: store i8 [[CONV25]], i8* [[Y]], align 8, !llvm.access.group !23
|
|
// CHECK22-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK22: omp.body.continue:
|
|
// CHECK22-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK22: omp.inner.for.inc:
|
|
// CHECK22-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23
|
|
// CHECK22-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP27]], 1
|
|
// CHECK22-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23
|
|
// CHECK22-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP24:![0-9]+]]
|
|
// CHECK22: omp.inner.for.end:
|
|
// CHECK22-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
|
|
// CHECK22: omp.dispatch.inc:
|
|
// CHECK22-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK22-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK22-NEXT: [[ADD27:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]
|
|
// CHECK22-NEXT: store i32 [[ADD27]], i32* [[DOTOMP_LB]], align 4
|
|
// CHECK22-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK22-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK22-NEXT: [[ADD28:%.*]] = add nsw i32 [[TMP30]], [[TMP31]]
|
|
// CHECK22-NEXT: store i32 [[ADD28]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK22-NEXT: br label [[OMP_DISPATCH_COND]]
|
|
// CHECK22: omp.dispatch.end:
|
|
// CHECK22-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]])
|
|
// CHECK22-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK22-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0
|
|
// CHECK22-NEXT: br i1 [[TMP33]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
|
|
// CHECK22: .omp.final.then:
|
|
// CHECK22-NEXT: store i8 96, i8* [[IT]], align 1
|
|
// CHECK22-NEXT: br label [[DOTOMP_FINAL_DONE]]
|
|
// CHECK22: .omp.final.done:
|
|
// CHECK22-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK22-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195
|
|
// CHECK22-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
|
|
// CHECK22-NEXT: entry:
|
|
// CHECK22-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK22-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK22-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK22-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
|
|
// CHECK22-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK22-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK22-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK22-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK22-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
|
|
// CHECK22-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
|
|
// CHECK22-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
|
|
// CHECK22-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK22-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
|
|
// CHECK22-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
|
|
// CHECK22-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
|
|
// CHECK22-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
|
|
// CHECK22-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
|
|
// CHECK22-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4
|
|
// CHECK22-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
|
|
// CHECK22-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
|
|
// CHECK22-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
|
|
// CHECK22-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2
|
|
// CHECK22-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
|
|
// CHECK22-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 8
|
|
// CHECK22-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
|
|
// CHECK22-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1
|
|
// CHECK22-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
|
|
// CHECK22-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]])
|
|
// CHECK22-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK22-LABEL: define {{[^@]+}}@.omp_outlined..4
|
|
// CHECK22-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {
|
|
// CHECK22-NEXT: entry:
|
|
// CHECK22-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK22-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK22-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK22-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK22-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK22-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
|
|
// CHECK22-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK22-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK22-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK22-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK22-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK22-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
|
|
// CHECK22-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
|
|
// CHECK22-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
|
|
// CHECK22-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK22-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
|
|
// CHECK22-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
|
|
// CHECK22-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
|
|
// CHECK22-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK22-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214
|
|
// CHECK22-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
|
|
// CHECK22-NEXT: entry:
|
|
// CHECK22-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
|
|
// CHECK22-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK22-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK22-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
|
|
// CHECK22-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8
|
|
// CHECK22-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK22-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK22-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK22-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
|
|
// CHECK22-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK22-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4
|
|
// CHECK22-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]])
|
|
// CHECK22-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK22-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
|
|
// CHECK22-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
|
|
// CHECK22-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
|
|
// CHECK22-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8
|
|
// CHECK22-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
|
|
// CHECK22-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK22-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
|
|
// CHECK22-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
|
|
// CHECK22-NEXT: [[TMP3:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
|
|
// CHECK22-NEXT: [[TMP4:%.*]] = load i16*, i16** [[C_ADDR]], align 8
|
|
// CHECK22-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
|
|
// CHECK22-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV]], align 8
|
|
// CHECK22-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i32*
|
|
// CHECK22-NEXT: store i32 [[TMP5]], i32* [[CONV4]], align 4
|
|
// CHECK22-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8
|
|
// CHECK22-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV3]], align 8
|
|
// CHECK22-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP7]] to i1
|
|
// CHECK22-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
|
|
// CHECK22-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
|
|
// CHECK22-NEXT: store i8 [[FROMBOOL]], i8* [[CONV5]], align 1
|
|
// CHECK22-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
|
|
// CHECK22-NEXT: [[TMP9:%.*]] = load i8, i8* [[CONV3]], align 8
|
|
// CHECK22-NEXT: [[TOBOOL6:%.*]] = trunc i8 [[TMP9]] to i1
|
|
// CHECK22-NEXT: br i1 [[TOBOOL6]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
|
|
// CHECK22: omp_if.then:
|
|
// CHECK22-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP6]], i64 [[TMP2]], i64 [[TMP3]], i16* [[TMP4]], i64 [[TMP8]])
|
|
// CHECK22-NEXT: br label [[OMP_IF_END:%.*]]
|
|
// CHECK22: omp_if.else:
|
|
// CHECK22-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]])
|
|
// CHECK22-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
|
|
// CHECK22-NEXT: call void @.omp_outlined..5(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]], i64 [[TMP6]], i64 [[TMP2]], i64 [[TMP3]], i16* [[TMP4]], i64 [[TMP8]]) #[[ATTR2:[0-9]+]]
|
|
// CHECK22-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]])
|
|
// CHECK22-NEXT: br label [[OMP_IF_END]]
|
|
// CHECK22: omp_if.end:
|
|
// CHECK22-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK22-LABEL: define {{[^@]+}}@.omp_outlined..5
|
|
// CHECK22-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
|
|
// CHECK22-NEXT: entry:
|
|
// CHECK22-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK22-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK22-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
|
|
// CHECK22-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK22-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK22-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
|
|
// CHECK22-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8
|
|
// CHECK22-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK22-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
|
|
// CHECK22-NEXT: [[TMP:%.*]] = alloca i64, align 8
|
|
// CHECK22-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
|
|
// CHECK22-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
|
|
// CHECK22-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
|
|
// CHECK22-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK22-NEXT: [[IT:%.*]] = alloca i64, align 8
|
|
// CHECK22-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK22-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK22-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK22-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
|
|
// CHECK22-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
|
|
// CHECK22-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
|
|
// CHECK22-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8
|
|
// CHECK22-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
|
|
// CHECK22-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK22-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
|
|
// CHECK22-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
|
|
// CHECK22-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
|
|
// CHECK22-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
|
|
// CHECK22-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
|
|
// CHECK22-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK22-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK22-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
|
|
// CHECK22-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK22-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV3]], align 8
|
|
// CHECK22-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1
|
|
// CHECK22-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
|
|
// CHECK22: omp_if.then:
|
|
// CHECK22-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK22-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4
|
|
// CHECK22-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
|
|
// CHECK22-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK22-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP7]], 3
|
|
// CHECK22-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK22: cond.true:
|
|
// CHECK22-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK22: cond.false:
|
|
// CHECK22-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK22-NEXT: br label [[COND_END]]
|
|
// CHECK22: cond.end:
|
|
// CHECK22-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ]
|
|
// CHECK22-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
|
|
// CHECK22-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK22-NEXT: store i64 [[TMP9]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK22-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK22: omp.inner.for.cond:
|
|
// CHECK22-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !26
|
|
// CHECK22-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !26
|
|
// CHECK22-NEXT: [[CMP4:%.*]] = icmp ule i64 [[TMP10]], [[TMP11]]
|
|
// CHECK22-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK22: omp.inner.for.body:
|
|
// CHECK22-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !26
|
|
// CHECK22-NEXT: [[MUL:%.*]] = mul i64 [[TMP12]], 400
|
|
// CHECK22-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]
|
|
// CHECK22-NEXT: store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !26
|
|
// CHECK22-NEXT: [[TMP13:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !26
|
|
// CHECK22-NEXT: [[CONV5:%.*]] = sitofp i32 [[TMP13]] to double
|
|
// CHECK22-NEXT: [[ADD:%.*]] = fadd double [[CONV5]], 1.500000e+00
|
|
// CHECK22-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
|
|
// CHECK22-NEXT: store double [[ADD]], double* [[A]], align 8, !nontemporal !27, !llvm.access.group !26
|
|
// CHECK22-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
|
|
// CHECK22-NEXT: [[TMP14:%.*]] = load double, double* [[A6]], align 8, !nontemporal !27, !llvm.access.group !26
|
|
// CHECK22-NEXT: [[INC:%.*]] = fadd double [[TMP14]], 1.000000e+00
|
|
// CHECK22-NEXT: store double [[INC]], double* [[A6]], align 8, !nontemporal !27, !llvm.access.group !26
|
|
// CHECK22-NEXT: [[CONV7:%.*]] = fptosi double [[INC]] to i16
|
|
// CHECK22-NEXT: [[TMP15:%.*]] = mul nsw i64 1, [[TMP2]]
|
|
// CHECK22-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP15]]
|
|
// CHECK22-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
|
|
// CHECK22-NEXT: store i16 [[CONV7]], i16* [[ARRAYIDX8]], align 2, !llvm.access.group !26
|
|
// CHECK22-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK22: omp.body.continue:
|
|
// CHECK22-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK22: omp.inner.for.inc:
|
|
// CHECK22-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !26
|
|
// CHECK22-NEXT: [[ADD9:%.*]] = add i64 [[TMP16]], 1
|
|
// CHECK22-NEXT: store i64 [[ADD9]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !26
|
|
// CHECK22-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]]
|
|
// CHECK22: omp.inner.for.end:
|
|
// CHECK22-NEXT: br label [[OMP_IF_END:%.*]]
|
|
// CHECK22: omp_if.else:
|
|
// CHECK22-NEXT: [[TMP17:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK22-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP17]], align 4
|
|
// CHECK22-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP18]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
|
|
// CHECK22-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK22-NEXT: [[CMP10:%.*]] = icmp ugt i64 [[TMP19]], 3
|
|
// CHECK22-NEXT: br i1 [[CMP10]], label [[COND_TRUE11:%.*]], label [[COND_FALSE12:%.*]]
|
|
// CHECK22: cond.true11:
|
|
// CHECK22-NEXT: br label [[COND_END13:%.*]]
|
|
// CHECK22: cond.false12:
|
|
// CHECK22-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK22-NEXT: br label [[COND_END13]]
|
|
// CHECK22: cond.end13:
|
|
// CHECK22-NEXT: [[COND14:%.*]] = phi i64 [ 3, [[COND_TRUE11]] ], [ [[TMP20]], [[COND_FALSE12]] ]
|
|
// CHECK22-NEXT: store i64 [[COND14]], i64* [[DOTOMP_UB]], align 8
|
|
// CHECK22-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK22-NEXT: store i64 [[TMP21]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK22-NEXT: br label [[OMP_INNER_FOR_COND15:%.*]]
|
|
// CHECK22: omp.inner.for.cond15:
|
|
// CHECK22-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK22-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK22-NEXT: [[CMP16:%.*]] = icmp ule i64 [[TMP22]], [[TMP23]]
|
|
// CHECK22-NEXT: br i1 [[CMP16]], label [[OMP_INNER_FOR_BODY17:%.*]], label [[OMP_INNER_FOR_END31:%.*]]
|
|
// CHECK22: omp.inner.for.body17:
|
|
// CHECK22-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK22-NEXT: [[MUL18:%.*]] = mul i64 [[TMP24]], 400
|
|
// CHECK22-NEXT: [[SUB19:%.*]] = sub i64 2000, [[MUL18]]
|
|
// CHECK22-NEXT: store i64 [[SUB19]], i64* [[IT]], align 8
|
|
// CHECK22-NEXT: [[TMP25:%.*]] = load i32, i32* [[CONV]], align 8
|
|
// CHECK22-NEXT: [[CONV20:%.*]] = sitofp i32 [[TMP25]] to double
|
|
// CHECK22-NEXT: [[ADD21:%.*]] = fadd double [[CONV20]], 1.500000e+00
|
|
// CHECK22-NEXT: [[A22:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
|
|
// CHECK22-NEXT: store double [[ADD21]], double* [[A22]], align 8
|
|
// CHECK22-NEXT: [[A23:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
|
|
// CHECK22-NEXT: [[TMP26:%.*]] = load double, double* [[A23]], align 8
|
|
// CHECK22-NEXT: [[INC24:%.*]] = fadd double [[TMP26]], 1.000000e+00
|
|
// CHECK22-NEXT: store double [[INC24]], double* [[A23]], align 8
|
|
// CHECK22-NEXT: [[CONV25:%.*]] = fptosi double [[INC24]] to i16
|
|
// CHECK22-NEXT: [[TMP27:%.*]] = mul nsw i64 1, [[TMP2]]
|
|
// CHECK22-NEXT: [[ARRAYIDX26:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP27]]
|
|
// CHECK22-NEXT: [[ARRAYIDX27:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX26]], i64 1
|
|
// CHECK22-NEXT: store i16 [[CONV25]], i16* [[ARRAYIDX27]], align 2
|
|
// CHECK22-NEXT: br label [[OMP_BODY_CONTINUE28:%.*]]
|
|
// CHECK22: omp.body.continue28:
|
|
// CHECK22-NEXT: br label [[OMP_INNER_FOR_INC29:%.*]]
|
|
// CHECK22: omp.inner.for.inc29:
|
|
// CHECK22-NEXT: [[TMP28:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK22-NEXT: [[ADD30:%.*]] = add i64 [[TMP28]], 1
|
|
// CHECK22-NEXT: store i64 [[ADD30]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK22-NEXT: br label [[OMP_INNER_FOR_COND15]], !llvm.loop [[LOOP30:![0-9]+]]
|
|
// CHECK22: omp.inner.for.end31:
|
|
// CHECK22-NEXT: br label [[OMP_IF_END]]
|
|
// CHECK22: omp_if.end:
|
|
// CHECK22-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK22: omp.loop.exit:
|
|
// CHECK22-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK22-NEXT: [[TMP30:%.*]] = load i32, i32* [[TMP29]], align 4
|
|
// CHECK22-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP30]])
|
|
// CHECK22-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK22-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0
|
|
// CHECK22-NEXT: br i1 [[TMP32]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
|
|
// CHECK22: .omp.final.then:
|
|
// CHECK22-NEXT: store i64 400, i64* [[IT]], align 8
|
|
// CHECK22-NEXT: br label [[DOTOMP_FINAL_DONE]]
|
|
// CHECK22: .omp.final.done:
|
|
// CHECK22-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK22-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178
|
|
// CHECK22-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
|
|
// CHECK22-NEXT: entry:
|
|
// CHECK22-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK22-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK22-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
|
|
// CHECK22-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK22-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK22-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK22-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
|
|
// CHECK22-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
|
|
// CHECK22-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK22-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
|
|
// CHECK22-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
|
|
// CHECK22-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
|
|
// CHECK22-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
|
|
// CHECK22-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4
|
|
// CHECK22-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
|
|
// CHECK22-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
|
|
// CHECK22-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
|
|
// CHECK22-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
|
|
// CHECK22-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
|
|
// CHECK22-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]])
|
|
// CHECK22-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK22-LABEL: define {{[^@]+}}@.omp_outlined..6
|
|
// CHECK22-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {
|
|
// CHECK22-NEXT: entry:
|
|
// CHECK22-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK22-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK22-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK22-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK22-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
|
|
// CHECK22-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
|
|
// CHECK22-NEXT: [[TMP:%.*]] = alloca i64, align 8
|
|
// CHECK22-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
|
|
// CHECK22-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
|
|
// CHECK22-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
|
|
// CHECK22-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK22-NEXT: [[I:%.*]] = alloca i64, align 8
|
|
// CHECK22-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK22-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK22-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK22-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
|
|
// CHECK22-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
|
|
// CHECK22-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK22-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
|
|
// CHECK22-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
|
|
// CHECK22-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK22-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK22-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
|
|
// CHECK22-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK22-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK22-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
|
|
// CHECK22-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
|
|
// CHECK22-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK22-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6
|
|
// CHECK22-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK22: cond.true:
|
|
// CHECK22-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK22: cond.false:
|
|
// CHECK22-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK22-NEXT: br label [[COND_END]]
|
|
// CHECK22: cond.end:
|
|
// CHECK22-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
|
|
// CHECK22-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
|
|
// CHECK22-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK22-NEXT: store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK22-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK22: omp.inner.for.cond:
|
|
// CHECK22-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !32
|
|
// CHECK22-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !32
|
|
// CHECK22-NEXT: [[CMP2:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]]
|
|
// CHECK22-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK22: omp.inner.for.body:
|
|
// CHECK22-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !32
|
|
// CHECK22-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3
|
|
// CHECK22-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
|
|
// CHECK22-NEXT: store i64 [[ADD]], i64* [[I]], align 8, !llvm.access.group !32
|
|
// CHECK22-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !32
|
|
// CHECK22-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1
|
|
// CHECK22-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 8, !llvm.access.group !32
|
|
// CHECK22-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 8, !llvm.access.group !32
|
|
// CHECK22-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32
|
|
// CHECK22-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
|
|
// CHECK22-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
|
|
// CHECK22-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 8, !llvm.access.group !32
|
|
// CHECK22-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
|
|
// CHECK22-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !32
|
|
// CHECK22-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1
|
|
// CHECK22-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !32
|
|
// CHECK22-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK22: omp.body.continue:
|
|
// CHECK22-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK22: omp.inner.for.inc:
|
|
// CHECK22-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !32
|
|
// CHECK22-NEXT: [[ADD8:%.*]] = add nsw i64 [[TMP12]], 1
|
|
// CHECK22-NEXT: store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !32
|
|
// CHECK22-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP33:![0-9]+]]
|
|
// CHECK22: omp.inner.for.end:
|
|
// CHECK22-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK22: omp.loop.exit:
|
|
// CHECK22-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
|
|
// CHECK22-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK22-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
|
|
// CHECK22-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
|
|
// CHECK22: .omp.final.then:
|
|
// CHECK22-NEXT: store i64 11, i64* [[I]], align 8
|
|
// CHECK22-NEXT: br label [[DOTOMP_FINAL_DONE]]
|
|
// CHECK22: .omp.final.done:
|
|
// CHECK22-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96
|
|
// CHECK23-SAME: () #[[ATTR0:[0-9]+]] {
|
|
// CHECK23-NEXT: entry:
|
|
// CHECK23-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
|
|
// CHECK23-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK23-LABEL: define {{[^@]+}}@.omp_outlined.
|
|
// CHECK23-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] {
|
|
// CHECK23-NEXT: entry:
|
|
// CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK23-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK23-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK23-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK23-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK23-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK23-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK23-NEXT: [[I:%.*]] = alloca i32, align 4
|
|
// CHECK23-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK23-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK23-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK23-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK23-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK23-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK23-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
|
|
// CHECK23-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
|
|
// CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK23-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5
|
|
// CHECK23-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK23: cond.true:
|
|
// CHECK23-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK23: cond.false:
|
|
// CHECK23-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK23-NEXT: br label [[COND_END]]
|
|
// CHECK23: cond.end:
|
|
// CHECK23-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
|
|
// CHECK23-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK23-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK23-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK23-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK23: omp.inner.for.cond:
|
|
// CHECK23-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
|
|
// CHECK23-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !12
|
|
// CHECK23-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
|
|
// CHECK23-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK23: omp.inner.for.body:
|
|
// CHECK23-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
|
|
// CHECK23-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5
|
|
// CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]]
|
|
// CHECK23-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !12
|
|
// CHECK23-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK23: omp.body.continue:
|
|
// CHECK23-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK23: omp.inner.for.inc:
|
|
// CHECK23-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
|
|
// CHECK23-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
|
|
// CHECK23-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
|
|
// CHECK23-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]
|
|
// CHECK23: omp.inner.for.end:
|
|
// CHECK23-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK23: omp.loop.exit:
|
|
// CHECK23-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
|
|
// CHECK23-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK23-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0
|
|
// CHECK23-NEXT: br i1 [[TMP10]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
|
|
// CHECK23: .omp.final.then:
|
|
// CHECK23-NEXT: store i32 33, i32* [[I]], align 4
|
|
// CHECK23-NEXT: br label [[DOTOMP_FINAL_DONE]]
|
|
// CHECK23: .omp.final.done:
|
|
// CHECK23-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108
|
|
// CHECK23-SAME: (i32 [[AA:%.*]], i32 [[LIN:%.*]], i32 [[A:%.*]]) #[[ATTR0]] {
|
|
// CHECK23-NEXT: entry:
|
|
// CHECK23-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK23-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK23-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK23-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK23-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK23-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK23-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
|
|
// CHECK23-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4
|
|
// CHECK23-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK23-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
|
|
// CHECK23-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
|
|
// CHECK23-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
|
|
// CHECK23-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
|
|
// CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
|
|
// CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[LIN_ADDR]], align 4
|
|
// CHECK23-NEXT: store i32 [[TMP2]], i32* [[LIN_CASTED]], align 4
|
|
// CHECK23-NEXT: [[TMP3:%.*]] = load i32, i32* [[LIN_CASTED]], align 4
|
|
// CHECK23-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK23-NEXT: store i32 [[TMP4]], i32* [[A_CASTED]], align 4
|
|
// CHECK23-NEXT: [[TMP5:%.*]] = load i32, i32* [[A_CASTED]], align 4
|
|
// CHECK23-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]])
|
|
// CHECK23-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK23-LABEL: define {{[^@]+}}@.omp_outlined..1
|
|
// CHECK23-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]], i32 [[LIN:%.*]], i32 [[A:%.*]]) #[[ATTR1]] {
|
|
// CHECK23-NEXT: entry:
|
|
// CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK23-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK23-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK23-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK23-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
|
|
// CHECK23-NEXT: [[TMP:%.*]] = alloca i64, align 4
|
|
// CHECK23-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4
|
|
// CHECK23-NEXT: [[DOTLINEAR_START1:%.*]] = alloca i32, align 4
|
|
// CHECK23-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8
|
|
// CHECK23-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
|
|
// CHECK23-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
|
|
// CHECK23-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
|
|
// CHECK23-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK23-NEXT: [[IT:%.*]] = alloca i64, align 8
|
|
// CHECK23-NEXT: [[LIN2:%.*]] = alloca i32, align 4
|
|
// CHECK23-NEXT: [[A3:%.*]] = alloca i32, align 4
|
|
// CHECK23-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK23-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK23-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
|
|
// CHECK23-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4
|
|
// CHECK23-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK23-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
|
|
// CHECK23-NEXT: [[TMP0:%.*]] = load i32, i32* [[LIN_ADDR]], align 4
|
|
// CHECK23-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4
|
|
// CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK23-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START1]], align 4
|
|
// CHECK23-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() #[[ATTR5:[0-9]+]]
|
|
// CHECK23-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8
|
|
// CHECK23-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK23-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK23-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
|
|
// CHECK23-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK23-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK23-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
|
|
// CHECK23-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP3]])
|
|
// CHECK23-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
|
|
// CHECK23-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK23-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3
|
|
// CHECK23-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK23: cond.true:
|
|
// CHECK23-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK23: cond.false:
|
|
// CHECK23-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK23-NEXT: br label [[COND_END]]
|
|
// CHECK23: cond.end:
|
|
// CHECK23-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
|
|
// CHECK23-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
|
|
// CHECK23-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK23-NEXT: store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK23-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK23: omp.inner.for.cond:
|
|
// CHECK23-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18
|
|
// CHECK23-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !18
|
|
// CHECK23-NEXT: [[CMP4:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]]
|
|
// CHECK23-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK23: omp.inner.for.body:
|
|
// CHECK23-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18
|
|
// CHECK23-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400
|
|
// CHECK23-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]
|
|
// CHECK23-NEXT: store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !18
|
|
// CHECK23-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4, !llvm.access.group !18
|
|
// CHECK23-NEXT: [[CONV5:%.*]] = sext i32 [[TMP10]] to i64
|
|
// CHECK23-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18
|
|
// CHECK23-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !18
|
|
// CHECK23-NEXT: [[MUL6:%.*]] = mul i64 [[TMP11]], [[TMP12]]
|
|
// CHECK23-NEXT: [[ADD:%.*]] = add i64 [[CONV5]], [[MUL6]]
|
|
// CHECK23-NEXT: [[CONV7:%.*]] = trunc i64 [[ADD]] to i32
|
|
// CHECK23-NEXT: store i32 [[CONV7]], i32* [[LIN2]], align 4, !llvm.access.group !18
|
|
// CHECK23-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START1]], align 4, !llvm.access.group !18
|
|
// CHECK23-NEXT: [[CONV8:%.*]] = sext i32 [[TMP13]] to i64
|
|
// CHECK23-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18
|
|
// CHECK23-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !18
|
|
// CHECK23-NEXT: [[MUL9:%.*]] = mul i64 [[TMP14]], [[TMP15]]
|
|
// CHECK23-NEXT: [[ADD10:%.*]] = add i64 [[CONV8]], [[MUL9]]
|
|
// CHECK23-NEXT: [[CONV11:%.*]] = trunc i64 [[ADD10]] to i32
|
|
// CHECK23-NEXT: store i32 [[CONV11]], i32* [[A3]], align 4, !llvm.access.group !18
|
|
// CHECK23-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !18
|
|
// CHECK23-NEXT: [[CONV12:%.*]] = sext i16 [[TMP16]] to i32
|
|
// CHECK23-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1
|
|
// CHECK23-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16
|
|
// CHECK23-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 4, !llvm.access.group !18
|
|
// CHECK23-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK23: omp.body.continue:
|
|
// CHECK23-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK23: omp.inner.for.inc:
|
|
// CHECK23-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18
|
|
// CHECK23-NEXT: [[ADD15:%.*]] = add i64 [[TMP17]], 1
|
|
// CHECK23-NEXT: store i64 [[ADD15]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18
|
|
// CHECK23-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]
|
|
// CHECK23: omp.inner.for.end:
|
|
// CHECK23-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK23: omp.loop.exit:
|
|
// CHECK23-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
|
|
// CHECK23-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK23-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
|
|
// CHECK23-NEXT: br i1 [[TMP19]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
|
|
// CHECK23: .omp.final.then:
|
|
// CHECK23-NEXT: store i64 400, i64* [[IT]], align 8
|
|
// CHECK23-NEXT: br label [[DOTOMP_FINAL_DONE]]
|
|
// CHECK23: .omp.final.done:
|
|
// CHECK23-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK23-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0
|
|
// CHECK23-NEXT: br i1 [[TMP21]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
|
|
// CHECK23: .omp.linear.pu:
|
|
// CHECK23-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4
|
|
// CHECK23-NEXT: [[CONV16:%.*]] = sext i32 [[TMP22]] to i64
|
|
// CHECK23-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
|
|
// CHECK23-NEXT: [[MUL17:%.*]] = mul i64 4, [[TMP23]]
|
|
// CHECK23-NEXT: [[ADD18:%.*]] = add i64 [[CONV16]], [[MUL17]]
|
|
// CHECK23-NEXT: [[CONV19:%.*]] = trunc i64 [[ADD18]] to i32
|
|
// CHECK23-NEXT: store i32 [[CONV19]], i32* [[LIN_ADDR]], align 4
|
|
// CHECK23-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTLINEAR_START1]], align 4
|
|
// CHECK23-NEXT: [[CONV20:%.*]] = sext i32 [[TMP24]] to i64
|
|
// CHECK23-NEXT: [[TMP25:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
|
|
// CHECK23-NEXT: [[MUL21:%.*]] = mul i64 4, [[TMP25]]
|
|
// CHECK23-NEXT: [[ADD22:%.*]] = add i64 [[CONV20]], [[MUL21]]
|
|
// CHECK23-NEXT: [[CONV23:%.*]] = trunc i64 [[ADD22]] to i32
|
|
// CHECK23-NEXT: store i32 [[CONV23]], i32* [[A_ADDR]], align 4
|
|
// CHECK23-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]]
|
|
// CHECK23: .omp.linear.pu.done:
|
|
// CHECK23-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK23-LABEL: define {{[^@]+}}@_Z7get_valv
|
|
// CHECK23-SAME: () #[[ATTR3:[0-9]+]] {
|
|
// CHECK23-NEXT: entry:
|
|
// CHECK23-NEXT: ret i64 0
|
|
//
|
|
//
|
|
// CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116
|
|
// CHECK23-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] {
|
|
// CHECK23-NEXT: entry:
|
|
// CHECK23-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK23-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK23-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK23-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK23-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK23-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
|
|
// CHECK23-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
|
|
// CHECK23-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK23-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
|
|
// CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
|
|
// CHECK23-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
|
|
// CHECK23-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
|
|
// CHECK23-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
|
|
// CHECK23-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
|
|
// CHECK23-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]])
|
|
// CHECK23-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK23-LABEL: define {{[^@]+}}@.omp_outlined..2
|
|
// CHECK23-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR1]] {
|
|
// CHECK23-NEXT: entry:
|
|
// CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK23-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK23-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK23-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK23-NEXT: [[TMP:%.*]] = alloca i16, align 2
|
|
// CHECK23-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK23-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK23-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK23-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK23-NEXT: [[IT:%.*]] = alloca i16, align 2
|
|
// CHECK23-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK23-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK23-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK23-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
|
|
// CHECK23-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
|
|
// CHECK23-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK23-NEXT: store i32 3, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK23-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK23-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK23-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
|
|
// CHECK23-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
|
|
// CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK23-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3
|
|
// CHECK23-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK23: cond.true:
|
|
// CHECK23-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK23: cond.false:
|
|
// CHECK23-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK23-NEXT: br label [[COND_END]]
|
|
// CHECK23: cond.end:
|
|
// CHECK23-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
|
|
// CHECK23-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK23-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK23-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK23-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK23: omp.inner.for.cond:
|
|
// CHECK23-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
|
|
// CHECK23-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !21
|
|
// CHECK23-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
|
|
// CHECK23-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK23: omp.inner.for.body:
|
|
// CHECK23-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
|
|
// CHECK23-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4
|
|
// CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]]
|
|
// CHECK23-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
|
|
// CHECK23-NEXT: store i16 [[CONV2]], i16* [[IT]], align 2, !llvm.access.group !21
|
|
// CHECK23-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !21
|
|
// CHECK23-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1
|
|
// CHECK23-NEXT: store i32 [[ADD3]], i32* [[A_ADDR]], align 4, !llvm.access.group !21
|
|
// CHECK23-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !21
|
|
// CHECK23-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32
|
|
// CHECK23-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
|
|
// CHECK23-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
|
|
// CHECK23-NEXT: store i16 [[CONV6]], i16* [[CONV]], align 4, !llvm.access.group !21
|
|
// CHECK23-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK23: omp.body.continue:
|
|
// CHECK23-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK23: omp.inner.for.inc:
|
|
// CHECK23-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
|
|
// CHECK23-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1
|
|
// CHECK23-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
|
|
// CHECK23-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]]
|
|
// CHECK23: omp.inner.for.end:
|
|
// CHECK23-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK23: omp.loop.exit:
|
|
// CHECK23-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
|
|
// CHECK23-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK23-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
|
|
// CHECK23-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
|
|
// CHECK23: .omp.final.then:
|
|
// CHECK23-NEXT: store i16 22, i16* [[IT]], align 2
|
|
// CHECK23-NEXT: br label [[DOTOMP_FINAL_DONE]]
|
|
// CHECK23: .omp.final.done:
|
|
// CHECK23-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140
|
|
// CHECK23-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
|
|
// CHECK23-NEXT: entry:
|
|
// CHECK23-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK23-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
|
|
// CHECK23-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK23-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4
|
|
// CHECK23-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
|
|
// CHECK23-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
|
|
// CHECK23-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4
|
|
// CHECK23-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4
|
|
// CHECK23-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
|
|
// CHECK23-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK23-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK23-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK23-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK23-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
|
|
// CHECK23-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
|
|
// CHECK23-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4
|
|
// CHECK23-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
|
|
// CHECK23-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
|
|
// CHECK23-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
|
|
// CHECK23-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4
|
|
// CHECK23-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
|
|
// CHECK23-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK23-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
|
|
// CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
|
|
// CHECK23-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
|
|
// CHECK23-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
|
|
// CHECK23-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
|
|
// CHECK23-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
|
|
// CHECK23-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
|
|
// CHECK23-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
|
|
// CHECK23-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK23-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4
|
|
// CHECK23-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4
|
|
// CHECK23-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK23-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
|
|
// CHECK23-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
|
|
// CHECK23-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i32 [[TMP11]])
|
|
// CHECK23-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK23-LABEL: define {{[^@]+}}@.omp_outlined..3
|
|
// CHECK23-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
|
|
// CHECK23-NEXT: entry:
|
|
// CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK23-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK23-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
|
|
// CHECK23-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK23-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4
|
|
// CHECK23-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
|
|
// CHECK23-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
|
|
// CHECK23-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4
|
|
// CHECK23-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4
|
|
// CHECK23-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
|
|
// CHECK23-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK23-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK23-NEXT: [[TMP:%.*]] = alloca i8, align 1
|
|
// CHECK23-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK23-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK23-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK23-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK23-NEXT: [[IT:%.*]] = alloca i8, align 1
|
|
// CHECK23-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK23-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK23-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK23-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
|
|
// CHECK23-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
|
|
// CHECK23-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4
|
|
// CHECK23-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
|
|
// CHECK23-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
|
|
// CHECK23-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
|
|
// CHECK23-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4
|
|
// CHECK23-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
|
|
// CHECK23-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK23-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
|
|
// CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
|
|
// CHECK23-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
|
|
// CHECK23-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
|
|
// CHECK23-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
|
|
// CHECK23-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
|
|
// CHECK23-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
|
|
// CHECK23-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
|
|
// CHECK23-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK23-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK23-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK23-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK23-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK23-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK23-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
|
|
// CHECK23-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
|
|
// CHECK23-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
|
|
// CHECK23: omp.dispatch.cond:
|
|
// CHECK23-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK23-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25
|
|
// CHECK23-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK23: cond.true:
|
|
// CHECK23-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK23: cond.false:
|
|
// CHECK23-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK23-NEXT: br label [[COND_END]]
|
|
// CHECK23: cond.end:
|
|
// CHECK23-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
|
|
// CHECK23-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK23-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK23-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK23-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK23-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK23-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
|
|
// CHECK23-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
|
|
// CHECK23: omp.dispatch.body:
|
|
// CHECK23-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK23: omp.inner.for.cond:
|
|
// CHECK23-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
|
|
// CHECK23-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !24
|
|
// CHECK23-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
|
|
// CHECK23-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK23: omp.inner.for.body:
|
|
// CHECK23-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
|
|
// CHECK23-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
|
|
// CHECK23-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]]
|
|
// CHECK23-NEXT: [[CONV:%.*]] = trunc i32 [[SUB]] to i8
|
|
// CHECK23-NEXT: store i8 [[CONV]], i8* [[IT]], align 1, !llvm.access.group !24
|
|
// CHECK23-NEXT: [[TMP19:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !24
|
|
// CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1
|
|
// CHECK23-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4, !llvm.access.group !24
|
|
// CHECK23-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2
|
|
// CHECK23-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !24
|
|
// CHECK23-NEXT: [[CONV7:%.*]] = fpext float [[TMP20]] to double
|
|
// CHECK23-NEXT: [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00
|
|
// CHECK23-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float
|
|
// CHECK23-NEXT: store float [[CONV9]], float* [[ARRAYIDX]], align 4, !llvm.access.group !24
|
|
// CHECK23-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3
|
|
// CHECK23-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX10]], align 4, !llvm.access.group !24
|
|
// CHECK23-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double
|
|
// CHECK23-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00
|
|
// CHECK23-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float
|
|
// CHECK23-NEXT: store float [[CONV13]], float* [[ARRAYIDX10]], align 4, !llvm.access.group !24
|
|
// CHECK23-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1
|
|
// CHECK23-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX14]], i32 0, i32 2
|
|
// CHECK23-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX15]], align 8, !llvm.access.group !24
|
|
// CHECK23-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00
|
|
// CHECK23-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8, !llvm.access.group !24
|
|
// CHECK23-NEXT: [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]]
|
|
// CHECK23-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP23]]
|
|
// CHECK23-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX17]], i32 3
|
|
// CHECK23-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX18]], align 8, !llvm.access.group !24
|
|
// CHECK23-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00
|
|
// CHECK23-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8, !llvm.access.group !24
|
|
// CHECK23-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0
|
|
// CHECK23-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 4, !llvm.access.group !24
|
|
// CHECK23-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1
|
|
// CHECK23-NEXT: store i64 [[ADD20]], i64* [[X]], align 4, !llvm.access.group !24
|
|
// CHECK23-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1
|
|
// CHECK23-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 4, !llvm.access.group !24
|
|
// CHECK23-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i32
|
|
// CHECK23-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1
|
|
// CHECK23-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8
|
|
// CHECK23-NEXT: store i8 [[CONV23]], i8* [[Y]], align 4, !llvm.access.group !24
|
|
// CHECK23-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK23: omp.body.continue:
|
|
// CHECK23-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK23: omp.inner.for.inc:
|
|
// CHECK23-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
|
|
// CHECK23-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1
|
|
// CHECK23-NEXT: store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
|
|
// CHECK23-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]]
|
|
// CHECK23: omp.inner.for.end:
|
|
// CHECK23-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
|
|
// CHECK23: omp.dispatch.inc:
|
|
// CHECK23-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK23-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK23-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]
|
|
// CHECK23-NEXT: store i32 [[ADD25]], i32* [[DOTOMP_LB]], align 4
|
|
// CHECK23-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK23-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK23-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]]
|
|
// CHECK23-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK23-NEXT: br label [[OMP_DISPATCH_COND]]
|
|
// CHECK23: omp.dispatch.end:
|
|
// CHECK23-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]])
|
|
// CHECK23-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK23-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0
|
|
// CHECK23-NEXT: br i1 [[TMP33]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
|
|
// CHECK23: .omp.final.then:
|
|
// CHECK23-NEXT: store i8 96, i8* [[IT]], align 1
|
|
// CHECK23-NEXT: br label [[DOTOMP_FINAL_DONE]]
|
|
// CHECK23: .omp.final.done:
|
|
// CHECK23-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195
|
|
// CHECK23-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
|
|
// CHECK23-NEXT: entry:
|
|
// CHECK23-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK23-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK23-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK23-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
|
|
// CHECK23-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK23-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK23-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK23-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK23-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
|
|
// CHECK23-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
|
|
// CHECK23-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
|
|
// CHECK23-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
|
|
// CHECK23-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
|
|
// CHECK23-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
|
|
// CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK23-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
|
|
// CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
|
|
// CHECK23-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
|
|
// CHECK23-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
|
|
// CHECK23-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2
|
|
// CHECK23-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
|
|
// CHECK23-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 4
|
|
// CHECK23-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
|
|
// CHECK23-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1
|
|
// CHECK23-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
|
|
// CHECK23-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]])
|
|
// CHECK23-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK23-LABEL: define {{[^@]+}}@.omp_outlined..4
|
|
// CHECK23-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {
|
|
// CHECK23-NEXT: entry:
|
|
// CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK23-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK23-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK23-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK23-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
|
|
// CHECK23-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK23-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK23-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK23-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK23-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK23-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
|
|
// CHECK23-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
|
|
// CHECK23-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
|
|
// CHECK23-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
|
|
// CHECK23-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
|
|
// CHECK23-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
|
|
// CHECK23-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214
|
|
// CHECK23-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
|
|
// CHECK23-NEXT: entry:
|
|
// CHECK23-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
|
|
// CHECK23-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK23-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK23-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
|
|
// CHECK23-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4
|
|
// CHECK23-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK23-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK23-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK23-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
|
|
// CHECK23-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK23-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4
|
|
// CHECK23-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]])
|
|
// CHECK23-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK23-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
|
|
// CHECK23-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
|
|
// CHECK23-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
|
|
// CHECK23-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4
|
|
// CHECK23-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK23-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
|
|
// CHECK23-NEXT: [[TMP3:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
|
|
// CHECK23-NEXT: [[TMP4:%.*]] = load i16*, i16** [[C_ADDR]], align 4
|
|
// CHECK23-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8*
|
|
// CHECK23-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_ADDR]], align 4
|
|
// CHECK23-NEXT: store i32 [[TMP5]], i32* [[B_CASTED]], align 4
|
|
// CHECK23-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4
|
|
// CHECK23-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV]], align 4
|
|
// CHECK23-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP7]] to i1
|
|
// CHECK23-NEXT: [[CONV3:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__CASTED]] to i8*
|
|
// CHECK23-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
|
|
// CHECK23-NEXT: store i8 [[FROMBOOL]], i8* [[CONV3]], align 1
|
|
// CHECK23-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
|
|
// CHECK23-NEXT: [[TMP9:%.*]] = load i8, i8* [[CONV]], align 4
|
|
// CHECK23-NEXT: [[TOBOOL4:%.*]] = trunc i8 [[TMP9]] to i1
|
|
// CHECK23-NEXT: br i1 [[TOBOOL4]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
|
|
// CHECK23: omp_if.then:
|
|
// CHECK23-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP6]], i32 [[TMP2]], i32 [[TMP3]], i16* [[TMP4]], i32 [[TMP8]])
|
|
// CHECK23-NEXT: br label [[OMP_IF_END:%.*]]
|
|
// CHECK23: omp_if.else:
|
|
// CHECK23-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]])
|
|
// CHECK23-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
|
|
// CHECK23-NEXT: call void @.omp_outlined..5(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]], i32 [[TMP6]], i32 [[TMP2]], i32 [[TMP3]], i16* [[TMP4]], i32 [[TMP8]]) #[[ATTR2:[0-9]+]]
|
|
// CHECK23-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]])
|
|
// CHECK23-NEXT: br label [[OMP_IF_END]]
|
|
// CHECK23: omp_if.end:
|
|
// CHECK23-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK23-LABEL: define {{[^@]+}}@.omp_outlined..5
|
|
// CHECK23-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
|
|
// CHECK23-NEXT: entry:
|
|
// CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK23-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
|
|
// CHECK23-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK23-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK23-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
|
|
// CHECK23-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4
|
|
// CHECK23-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK23-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
|
|
// CHECK23-NEXT: [[TMP:%.*]] = alloca i64, align 4
|
|
// CHECK23-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
|
|
// CHECK23-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
|
|
// CHECK23-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
|
|
// CHECK23-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK23-NEXT: [[IT:%.*]] = alloca i64, align 8
|
|
// CHECK23-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK23-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK23-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK23-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
|
|
// CHECK23-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
|
|
// CHECK23-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
|
|
// CHECK23-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4
|
|
// CHECK23-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK23-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
|
|
// CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
|
|
// CHECK23-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
|
|
// CHECK23-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8*
|
|
// CHECK23-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK23-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK23-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
|
|
// CHECK23-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK23-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV]], align 4
|
|
// CHECK23-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1
|
|
// CHECK23-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
|
|
// CHECK23: omp_if.then:
|
|
// CHECK23-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK23-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4
|
|
// CHECK23-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
|
|
// CHECK23-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK23-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP7]], 3
|
|
// CHECK23-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK23: cond.true:
|
|
// CHECK23-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK23: cond.false:
|
|
// CHECK23-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK23-NEXT: br label [[COND_END]]
|
|
// CHECK23: cond.end:
|
|
// CHECK23-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ]
|
|
// CHECK23-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
|
|
// CHECK23-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK23-NEXT: store i64 [[TMP9]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK23-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK23: omp.inner.for.cond:
|
|
// CHECK23-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !27
|
|
// CHECK23-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !27
|
|
// CHECK23-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP10]], [[TMP11]]
|
|
// CHECK23-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK23: omp.inner.for.body:
|
|
// CHECK23-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !27
|
|
// CHECK23-NEXT: [[MUL:%.*]] = mul i64 [[TMP12]], 400
|
|
// CHECK23-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]
|
|
// CHECK23-NEXT: store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !27
|
|
// CHECK23-NEXT: [[TMP13:%.*]] = load i32, i32* [[B_ADDR]], align 4, !llvm.access.group !27
|
|
// CHECK23-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP13]] to double
|
|
// CHECK23-NEXT: [[ADD:%.*]] = fadd double [[CONV4]], 1.500000e+00
|
|
// CHECK23-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
|
|
// CHECK23-NEXT: store double [[ADD]], double* [[A]], align 4, !nontemporal !28, !llvm.access.group !27
|
|
// CHECK23-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
|
|
// CHECK23-NEXT: [[TMP14:%.*]] = load double, double* [[A5]], align 4, !nontemporal !28, !llvm.access.group !27
|
|
// CHECK23-NEXT: [[INC:%.*]] = fadd double [[TMP14]], 1.000000e+00
|
|
// CHECK23-NEXT: store double [[INC]], double* [[A5]], align 4, !nontemporal !28, !llvm.access.group !27
|
|
// CHECK23-NEXT: [[CONV6:%.*]] = fptosi double [[INC]] to i16
|
|
// CHECK23-NEXT: [[TMP15:%.*]] = mul nsw i32 1, [[TMP2]]
|
|
// CHECK23-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP15]]
|
|
// CHECK23-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
|
|
// CHECK23-NEXT: store i16 [[CONV6]], i16* [[ARRAYIDX7]], align 2, !llvm.access.group !27
|
|
// CHECK23-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK23: omp.body.continue:
|
|
// CHECK23-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK23: omp.inner.for.inc:
|
|
// CHECK23-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !27
|
|
// CHECK23-NEXT: [[ADD8:%.*]] = add i64 [[TMP16]], 1
|
|
// CHECK23-NEXT: store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !27
|
|
// CHECK23-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP29:![0-9]+]]
|
|
// CHECK23: omp.inner.for.end:
|
|
// CHECK23-NEXT: br label [[OMP_IF_END:%.*]]
|
|
// CHECK23: omp_if.else:
|
|
// CHECK23-NEXT: [[TMP17:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK23-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP17]], align 4
|
|
// CHECK23-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP18]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
|
|
// CHECK23-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK23-NEXT: [[CMP9:%.*]] = icmp ugt i64 [[TMP19]], 3
|
|
// CHECK23-NEXT: br i1 [[CMP9]], label [[COND_TRUE10:%.*]], label [[COND_FALSE11:%.*]]
|
|
// CHECK23: cond.true10:
|
|
// CHECK23-NEXT: br label [[COND_END12:%.*]]
|
|
// CHECK23: cond.false11:
|
|
// CHECK23-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK23-NEXT: br label [[COND_END12]]
|
|
// CHECK23: cond.end12:
|
|
// CHECK23-NEXT: [[COND13:%.*]] = phi i64 [ 3, [[COND_TRUE10]] ], [ [[TMP20]], [[COND_FALSE11]] ]
|
|
// CHECK23-NEXT: store i64 [[COND13]], i64* [[DOTOMP_UB]], align 8
|
|
// CHECK23-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK23-NEXT: store i64 [[TMP21]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK23-NEXT: br label [[OMP_INNER_FOR_COND14:%.*]]
|
|
// CHECK23: omp.inner.for.cond14:
|
|
// CHECK23-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK23-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK23-NEXT: [[CMP15:%.*]] = icmp ule i64 [[TMP22]], [[TMP23]]
|
|
// CHECK23-NEXT: br i1 [[CMP15]], label [[OMP_INNER_FOR_BODY16:%.*]], label [[OMP_INNER_FOR_END30:%.*]]
|
|
// CHECK23: omp.inner.for.body16:
|
|
// CHECK23-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK23-NEXT: [[MUL17:%.*]] = mul i64 [[TMP24]], 400
|
|
// CHECK23-NEXT: [[SUB18:%.*]] = sub i64 2000, [[MUL17]]
|
|
// CHECK23-NEXT: store i64 [[SUB18]], i64* [[IT]], align 8
|
|
// CHECK23-NEXT: [[TMP25:%.*]] = load i32, i32* [[B_ADDR]], align 4
|
|
// CHECK23-NEXT: [[CONV19:%.*]] = sitofp i32 [[TMP25]] to double
|
|
// CHECK23-NEXT: [[ADD20:%.*]] = fadd double [[CONV19]], 1.500000e+00
|
|
// CHECK23-NEXT: [[A21:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
|
|
// CHECK23-NEXT: store double [[ADD20]], double* [[A21]], align 4
|
|
// CHECK23-NEXT: [[A22:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
|
|
// CHECK23-NEXT: [[TMP26:%.*]] = load double, double* [[A22]], align 4
|
|
// CHECK23-NEXT: [[INC23:%.*]] = fadd double [[TMP26]], 1.000000e+00
|
|
// CHECK23-NEXT: store double [[INC23]], double* [[A22]], align 4
|
|
// CHECK23-NEXT: [[CONV24:%.*]] = fptosi double [[INC23]] to i16
|
|
// CHECK23-NEXT: [[TMP27:%.*]] = mul nsw i32 1, [[TMP2]]
|
|
// CHECK23-NEXT: [[ARRAYIDX25:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP27]]
|
|
// CHECK23-NEXT: [[ARRAYIDX26:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX25]], i32 1
|
|
// CHECK23-NEXT: store i16 [[CONV24]], i16* [[ARRAYIDX26]], align 2
|
|
// CHECK23-NEXT: br label [[OMP_BODY_CONTINUE27:%.*]]
|
|
// CHECK23: omp.body.continue27:
|
|
// CHECK23-NEXT: br label [[OMP_INNER_FOR_INC28:%.*]]
|
|
// CHECK23: omp.inner.for.inc28:
|
|
// CHECK23-NEXT: [[TMP28:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK23-NEXT: [[ADD29:%.*]] = add i64 [[TMP28]], 1
|
|
// CHECK23-NEXT: store i64 [[ADD29]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK23-NEXT: br label [[OMP_INNER_FOR_COND14]], !llvm.loop [[LOOP31:![0-9]+]]
|
|
// CHECK23: omp.inner.for.end30:
|
|
// CHECK23-NEXT: br label [[OMP_IF_END]]
|
|
// CHECK23: omp_if.end:
|
|
// CHECK23-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK23: omp.loop.exit:
|
|
// CHECK23-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK23-NEXT: [[TMP30:%.*]] = load i32, i32* [[TMP29]], align 4
|
|
// CHECK23-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP30]])
|
|
// CHECK23-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK23-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0
|
|
// CHECK23-NEXT: br i1 [[TMP32]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
|
|
// CHECK23: .omp.final.then:
|
|
// CHECK23-NEXT: store i64 400, i64* [[IT]], align 8
|
|
// CHECK23-NEXT: br label [[DOTOMP_FINAL_DONE]]
|
|
// CHECK23: .omp.final.done:
|
|
// CHECK23-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178
|
|
// CHECK23-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
|
|
// CHECK23-NEXT: entry:
|
|
// CHECK23-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK23-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK23-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
|
|
// CHECK23-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK23-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK23-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK23-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
|
|
// CHECK23-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
|
|
// CHECK23-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
|
|
// CHECK23-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
|
|
// CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK23-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
|
|
// CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
|
|
// CHECK23-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
|
|
// CHECK23-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
|
|
// CHECK23-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2
|
|
// CHECK23-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
|
|
// CHECK23-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]])
|
|
// CHECK23-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK23-LABEL: define {{[^@]+}}@.omp_outlined..6
|
|
// CHECK23-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {
|
|
// CHECK23-NEXT: entry:
|
|
// CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK23-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK23-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK23-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
|
|
// CHECK23-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
|
|
// CHECK23-NEXT: [[TMP:%.*]] = alloca i64, align 4
|
|
// CHECK23-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
|
|
// CHECK23-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
|
|
// CHECK23-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
|
|
// CHECK23-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK23-NEXT: [[I:%.*]] = alloca i64, align 8
|
|
// CHECK23-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK23-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK23-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK23-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
|
|
// CHECK23-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
|
|
// CHECK23-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
|
|
// CHECK23-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
|
|
// CHECK23-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK23-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK23-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
|
|
// CHECK23-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK23-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
|
|
// CHECK23-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
|
|
// CHECK23-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK23-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6
|
|
// CHECK23-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK23: cond.true:
|
|
// CHECK23-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK23: cond.false:
|
|
// CHECK23-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK23-NEXT: br label [[COND_END]]
|
|
// CHECK23: cond.end:
|
|
// CHECK23-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
|
|
// CHECK23-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
|
|
// CHECK23-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK23-NEXT: store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK23-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK23: omp.inner.for.cond:
|
|
// CHECK23-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !33
|
|
// CHECK23-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !33
|
|
// CHECK23-NEXT: [[CMP1:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]]
|
|
// CHECK23-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK23: omp.inner.for.body:
|
|
// CHECK23-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !33
|
|
// CHECK23-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3
|
|
// CHECK23-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
|
|
// CHECK23-NEXT: store i64 [[ADD]], i64* [[I]], align 8, !llvm.access.group !33
|
|
// CHECK23-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !33
|
|
// CHECK23-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
|
|
// CHECK23-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4, !llvm.access.group !33
|
|
// CHECK23-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !33
|
|
// CHECK23-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32
|
|
// CHECK23-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
|
|
// CHECK23-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
|
|
// CHECK23-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 4, !llvm.access.group !33
|
|
// CHECK23-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
|
|
// CHECK23-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !33
|
|
// CHECK23-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1
|
|
// CHECK23-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !33
|
|
// CHECK23-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK23: omp.body.continue:
|
|
// CHECK23-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK23: omp.inner.for.inc:
|
|
// CHECK23-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !33
|
|
// CHECK23-NEXT: [[ADD7:%.*]] = add nsw i64 [[TMP12]], 1
|
|
// CHECK23-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !33
|
|
// CHECK23-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP34:![0-9]+]]
|
|
// CHECK23: omp.inner.for.end:
|
|
// CHECK23-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK23: omp.loop.exit:
|
|
// CHECK23-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
|
|
// CHECK23-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK23-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
|
|
// CHECK23-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
|
|
// CHECK23: .omp.final.then:
|
|
// CHECK23-NEXT: store i64 11, i64* [[I]], align 8
|
|
// CHECK23-NEXT: br label [[DOTOMP_FINAL_DONE]]
|
|
// CHECK23: .omp.final.done:
|
|
// CHECK23-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK24-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96
|
|
// CHECK24-SAME: () #[[ATTR0:[0-9]+]] {
|
|
// CHECK24-NEXT: entry:
|
|
// CHECK24-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
|
|
// CHECK24-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK24-LABEL: define {{[^@]+}}@.omp_outlined.
|
|
// CHECK24-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] {
|
|
// CHECK24-NEXT: entry:
|
|
// CHECK24-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK24-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK24-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK24-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK24-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK24-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK24-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK24-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK24-NEXT: [[I:%.*]] = alloca i32, align 4
|
|
// CHECK24-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK24-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK24-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK24-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK24-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK24-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK24-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK24-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
|
|
// CHECK24-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
|
|
// CHECK24-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK24-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5
|
|
// CHECK24-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK24: cond.true:
|
|
// CHECK24-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK24: cond.false:
|
|
// CHECK24-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK24-NEXT: br label [[COND_END]]
|
|
// CHECK24: cond.end:
|
|
// CHECK24-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
|
|
// CHECK24-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK24-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK24-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK24-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK24: omp.inner.for.cond:
|
|
// CHECK24-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
|
|
// CHECK24-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !12
|
|
// CHECK24-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
|
|
// CHECK24-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK24: omp.inner.for.body:
|
|
// CHECK24-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
|
|
// CHECK24-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5
|
|
// CHECK24-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]]
|
|
// CHECK24-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !12
|
|
// CHECK24-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK24: omp.body.continue:
|
|
// CHECK24-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK24: omp.inner.for.inc:
|
|
// CHECK24-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
|
|
// CHECK24-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
|
|
// CHECK24-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
|
|
// CHECK24-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]
|
|
// CHECK24: omp.inner.for.end:
|
|
// CHECK24-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK24: omp.loop.exit:
|
|
// CHECK24-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
|
|
// CHECK24-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK24-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0
|
|
// CHECK24-NEXT: br i1 [[TMP10]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
|
|
// CHECK24: .omp.final.then:
|
|
// CHECK24-NEXT: store i32 33, i32* [[I]], align 4
|
|
// CHECK24-NEXT: br label [[DOTOMP_FINAL_DONE]]
|
|
// CHECK24: .omp.final.done:
|
|
// CHECK24-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK24-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108
|
|
// CHECK24-SAME: (i32 [[AA:%.*]], i32 [[LIN:%.*]], i32 [[A:%.*]]) #[[ATTR0]] {
|
|
// CHECK24-NEXT: entry:
|
|
// CHECK24-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK24-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK24-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK24-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK24-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK24-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK24-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
|
|
// CHECK24-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4
|
|
// CHECK24-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK24-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
|
|
// CHECK24-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
|
|
// CHECK24-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
|
|
// CHECK24-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
|
|
// CHECK24-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
|
|
// CHECK24-NEXT: [[TMP2:%.*]] = load i32, i32* [[LIN_ADDR]], align 4
|
|
// CHECK24-NEXT: store i32 [[TMP2]], i32* [[LIN_CASTED]], align 4
|
|
// CHECK24-NEXT: [[TMP3:%.*]] = load i32, i32* [[LIN_CASTED]], align 4
|
|
// CHECK24-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK24-NEXT: store i32 [[TMP4]], i32* [[A_CASTED]], align 4
|
|
// CHECK24-NEXT: [[TMP5:%.*]] = load i32, i32* [[A_CASTED]], align 4
|
|
// CHECK24-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]])
|
|
// CHECK24-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK24-LABEL: define {{[^@]+}}@.omp_outlined..1
|
|
// CHECK24-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]], i32 [[LIN:%.*]], i32 [[A:%.*]]) #[[ATTR1]] {
|
|
// CHECK24-NEXT: entry:
|
|
// CHECK24-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK24-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK24-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK24-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK24-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK24-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
|
|
// CHECK24-NEXT: [[TMP:%.*]] = alloca i64, align 4
|
|
// CHECK24-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4
|
|
// CHECK24-NEXT: [[DOTLINEAR_START1:%.*]] = alloca i32, align 4
|
|
// CHECK24-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8
|
|
// CHECK24-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
|
|
// CHECK24-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
|
|
// CHECK24-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
|
|
// CHECK24-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK24-NEXT: [[IT:%.*]] = alloca i64, align 8
|
|
// CHECK24-NEXT: [[LIN2:%.*]] = alloca i32, align 4
|
|
// CHECK24-NEXT: [[A3:%.*]] = alloca i32, align 4
|
|
// CHECK24-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK24-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK24-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
|
|
// CHECK24-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4
|
|
// CHECK24-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK24-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
|
|
// CHECK24-NEXT: [[TMP0:%.*]] = load i32, i32* [[LIN_ADDR]], align 4
|
|
// CHECK24-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4
|
|
// CHECK24-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK24-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START1]], align 4
|
|
// CHECK24-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() #[[ATTR5:[0-9]+]]
|
|
// CHECK24-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8
|
|
// CHECK24-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK24-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK24-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
|
|
// CHECK24-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK24-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK24-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
|
|
// CHECK24-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP3]])
|
|
// CHECK24-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
|
|
// CHECK24-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK24-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3
|
|
// CHECK24-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK24: cond.true:
|
|
// CHECK24-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK24: cond.false:
|
|
// CHECK24-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK24-NEXT: br label [[COND_END]]
|
|
// CHECK24: cond.end:
|
|
// CHECK24-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
|
|
// CHECK24-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
|
|
// CHECK24-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK24-NEXT: store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK24-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK24: omp.inner.for.cond:
|
|
// CHECK24-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18
|
|
// CHECK24-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !18
|
|
// CHECK24-NEXT: [[CMP4:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]]
|
|
// CHECK24-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK24: omp.inner.for.body:
|
|
// CHECK24-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18
|
|
// CHECK24-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400
|
|
// CHECK24-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]
|
|
// CHECK24-NEXT: store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !18
|
|
// CHECK24-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4, !llvm.access.group !18
|
|
// CHECK24-NEXT: [[CONV5:%.*]] = sext i32 [[TMP10]] to i64
|
|
// CHECK24-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18
|
|
// CHECK24-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !18
|
|
// CHECK24-NEXT: [[MUL6:%.*]] = mul i64 [[TMP11]], [[TMP12]]
|
|
// CHECK24-NEXT: [[ADD:%.*]] = add i64 [[CONV5]], [[MUL6]]
|
|
// CHECK24-NEXT: [[CONV7:%.*]] = trunc i64 [[ADD]] to i32
|
|
// CHECK24-NEXT: store i32 [[CONV7]], i32* [[LIN2]], align 4, !llvm.access.group !18
|
|
// CHECK24-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START1]], align 4, !llvm.access.group !18
|
|
// CHECK24-NEXT: [[CONV8:%.*]] = sext i32 [[TMP13]] to i64
|
|
// CHECK24-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18
|
|
// CHECK24-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !18
|
|
// CHECK24-NEXT: [[MUL9:%.*]] = mul i64 [[TMP14]], [[TMP15]]
|
|
// CHECK24-NEXT: [[ADD10:%.*]] = add i64 [[CONV8]], [[MUL9]]
|
|
// CHECK24-NEXT: [[CONV11:%.*]] = trunc i64 [[ADD10]] to i32
|
|
// CHECK24-NEXT: store i32 [[CONV11]], i32* [[A3]], align 4, !llvm.access.group !18
|
|
// CHECK24-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !18
|
|
// CHECK24-NEXT: [[CONV12:%.*]] = sext i16 [[TMP16]] to i32
|
|
// CHECK24-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1
|
|
// CHECK24-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16
|
|
// CHECK24-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 4, !llvm.access.group !18
|
|
// CHECK24-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK24: omp.body.continue:
|
|
// CHECK24-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK24: omp.inner.for.inc:
|
|
// CHECK24-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18
|
|
// CHECK24-NEXT: [[ADD15:%.*]] = add i64 [[TMP17]], 1
|
|
// CHECK24-NEXT: store i64 [[ADD15]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18
|
|
// CHECK24-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]
|
|
// CHECK24: omp.inner.for.end:
|
|
// CHECK24-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK24: omp.loop.exit:
|
|
// CHECK24-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
|
|
// CHECK24-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK24-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
|
|
// CHECK24-NEXT: br i1 [[TMP19]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
|
|
// CHECK24: .omp.final.then:
|
|
// CHECK24-NEXT: store i64 400, i64* [[IT]], align 8
|
|
// CHECK24-NEXT: br label [[DOTOMP_FINAL_DONE]]
|
|
// CHECK24: .omp.final.done:
|
|
// CHECK24-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK24-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0
|
|
// CHECK24-NEXT: br i1 [[TMP21]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
|
|
// CHECK24: .omp.linear.pu:
|
|
// CHECK24-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4
|
|
// CHECK24-NEXT: [[CONV16:%.*]] = sext i32 [[TMP22]] to i64
|
|
// CHECK24-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
|
|
// CHECK24-NEXT: [[MUL17:%.*]] = mul i64 4, [[TMP23]]
|
|
// CHECK24-NEXT: [[ADD18:%.*]] = add i64 [[CONV16]], [[MUL17]]
|
|
// CHECK24-NEXT: [[CONV19:%.*]] = trunc i64 [[ADD18]] to i32
|
|
// CHECK24-NEXT: store i32 [[CONV19]], i32* [[LIN_ADDR]], align 4
|
|
// CHECK24-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTLINEAR_START1]], align 4
|
|
// CHECK24-NEXT: [[CONV20:%.*]] = sext i32 [[TMP24]] to i64
|
|
// CHECK24-NEXT: [[TMP25:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
|
|
// CHECK24-NEXT: [[MUL21:%.*]] = mul i64 4, [[TMP25]]
|
|
// CHECK24-NEXT: [[ADD22:%.*]] = add i64 [[CONV20]], [[MUL21]]
|
|
// CHECK24-NEXT: [[CONV23:%.*]] = trunc i64 [[ADD22]] to i32
|
|
// CHECK24-NEXT: store i32 [[CONV23]], i32* [[A_ADDR]], align 4
|
|
// CHECK24-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]]
|
|
// CHECK24: .omp.linear.pu.done:
|
|
// CHECK24-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK24-LABEL: define {{[^@]+}}@_Z7get_valv
|
|
// CHECK24-SAME: () #[[ATTR3:[0-9]+]] {
|
|
// CHECK24-NEXT: entry:
|
|
// CHECK24-NEXT: ret i64 0
|
|
//
|
|
//
|
|
// CHECK24-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116
|
|
// CHECK24-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] {
|
|
// CHECK24-NEXT: entry:
|
|
// CHECK24-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK24-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK24-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK24-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK24-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK24-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
|
|
// CHECK24-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
|
|
// CHECK24-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK24-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
|
|
// CHECK24-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
|
|
// CHECK24-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
|
|
// CHECK24-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
|
|
// CHECK24-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
|
|
// CHECK24-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
|
|
// CHECK24-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]])
|
|
// CHECK24-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK24-LABEL: define {{[^@]+}}@.omp_outlined..2
|
|
// CHECK24-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR1]] {
|
|
// CHECK24-NEXT: entry:
|
|
// CHECK24-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK24-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK24-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK24-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK24-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK24-NEXT: [[TMP:%.*]] = alloca i16, align 2
|
|
// CHECK24-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK24-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK24-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK24-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK24-NEXT: [[IT:%.*]] = alloca i16, align 2
|
|
// CHECK24-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK24-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK24-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK24-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
|
|
// CHECK24-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
|
|
// CHECK24-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK24-NEXT: store i32 3, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK24-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK24-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK24-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK24-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
|
|
// CHECK24-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
|
|
// CHECK24-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK24-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3
|
|
// CHECK24-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK24: cond.true:
|
|
// CHECK24-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK24: cond.false:
|
|
// CHECK24-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK24-NEXT: br label [[COND_END]]
|
|
// CHECK24: cond.end:
|
|
// CHECK24-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
|
|
// CHECK24-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK24-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK24-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK24-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK24: omp.inner.for.cond:
|
|
// CHECK24-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
|
|
// CHECK24-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !21
|
|
// CHECK24-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
|
|
// CHECK24-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK24: omp.inner.for.body:
|
|
// CHECK24-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
|
|
// CHECK24-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4
|
|
// CHECK24-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]]
|
|
// CHECK24-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
|
|
// CHECK24-NEXT: store i16 [[CONV2]], i16* [[IT]], align 2, !llvm.access.group !21
|
|
// CHECK24-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !21
|
|
// CHECK24-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1
|
|
// CHECK24-NEXT: store i32 [[ADD3]], i32* [[A_ADDR]], align 4, !llvm.access.group !21
|
|
// CHECK24-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !21
|
|
// CHECK24-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32
|
|
// CHECK24-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
|
|
// CHECK24-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
|
|
// CHECK24-NEXT: store i16 [[CONV6]], i16* [[CONV]], align 4, !llvm.access.group !21
|
|
// CHECK24-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK24: omp.body.continue:
|
|
// CHECK24-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK24: omp.inner.for.inc:
|
|
// CHECK24-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
|
|
// CHECK24-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1
|
|
// CHECK24-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
|
|
// CHECK24-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]]
|
|
// CHECK24: omp.inner.for.end:
|
|
// CHECK24-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK24: omp.loop.exit:
|
|
// CHECK24-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
|
|
// CHECK24-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK24-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
|
|
// CHECK24-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
|
|
// CHECK24: .omp.final.then:
|
|
// CHECK24-NEXT: store i16 22, i16* [[IT]], align 2
|
|
// CHECK24-NEXT: br label [[DOTOMP_FINAL_DONE]]
|
|
// CHECK24: .omp.final.done:
|
|
// CHECK24-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK24-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140
|
|
// CHECK24-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
|
|
// CHECK24-NEXT: entry:
|
|
// CHECK24-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK24-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
|
|
// CHECK24-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK24-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4
|
|
// CHECK24-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
|
|
// CHECK24-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
|
|
// CHECK24-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4
|
|
// CHECK24-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4
|
|
// CHECK24-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
|
|
// CHECK24-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK24-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK24-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK24-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK24-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
|
|
// CHECK24-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
|
|
// CHECK24-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4
|
|
// CHECK24-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
|
|
// CHECK24-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
|
|
// CHECK24-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
|
|
// CHECK24-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4
|
|
// CHECK24-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
|
|
// CHECK24-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK24-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
|
|
// CHECK24-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
|
|
// CHECK24-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
|
|
// CHECK24-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
|
|
// CHECK24-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
|
|
// CHECK24-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
|
|
// CHECK24-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
|
|
// CHECK24-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
|
|
// CHECK24-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK24-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4
|
|
// CHECK24-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4
|
|
// CHECK24-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK24-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
|
|
// CHECK24-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
|
|
// CHECK24-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i32 [[TMP11]])
|
|
// CHECK24-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK24-LABEL: define {{[^@]+}}@.omp_outlined..3
|
|
// CHECK24-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
|
|
// CHECK24-NEXT: entry:
|
|
// CHECK24-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK24-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK24-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK24-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
|
|
// CHECK24-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK24-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4
|
|
// CHECK24-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
|
|
// CHECK24-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
|
|
// CHECK24-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4
|
|
// CHECK24-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4
|
|
// CHECK24-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
|
|
// CHECK24-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK24-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK24-NEXT: [[TMP:%.*]] = alloca i8, align 1
|
|
// CHECK24-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK24-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK24-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK24-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK24-NEXT: [[IT:%.*]] = alloca i8, align 1
|
|
// CHECK24-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK24-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK24-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK24-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
|
|
// CHECK24-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
|
|
// CHECK24-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4
|
|
// CHECK24-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
|
|
// CHECK24-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
|
|
// CHECK24-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
|
|
// CHECK24-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4
|
|
// CHECK24-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
|
|
// CHECK24-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK24-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
|
|
// CHECK24-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
|
|
// CHECK24-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
|
|
// CHECK24-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
|
|
// CHECK24-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
|
|
// CHECK24-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
|
|
// CHECK24-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
|
|
// CHECK24-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
|
|
// CHECK24-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK24-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK24-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK24-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK24-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK24-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK24-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
|
|
// CHECK24-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
|
|
// CHECK24-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
|
|
// CHECK24: omp.dispatch.cond:
|
|
// CHECK24-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK24-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25
|
|
// CHECK24-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK24: cond.true:
|
|
// CHECK24-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK24: cond.false:
|
|
// CHECK24-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK24-NEXT: br label [[COND_END]]
|
|
// CHECK24: cond.end:
|
|
// CHECK24-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
|
|
// CHECK24-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK24-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK24-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK24-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK24-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK24-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
|
|
// CHECK24-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
|
|
// CHECK24: omp.dispatch.body:
|
|
// CHECK24-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK24: omp.inner.for.cond:
|
|
// CHECK24-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
|
|
// CHECK24-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !24
|
|
// CHECK24-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
|
|
// CHECK24-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK24: omp.inner.for.body:
|
|
// CHECK24-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
|
|
// CHECK24-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
|
|
// CHECK24-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]]
|
|
// CHECK24-NEXT: [[CONV:%.*]] = trunc i32 [[SUB]] to i8
|
|
// CHECK24-NEXT: store i8 [[CONV]], i8* [[IT]], align 1, !llvm.access.group !24
|
|
// CHECK24-NEXT: [[TMP19:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !24
|
|
// CHECK24-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1
|
|
// CHECK24-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4, !llvm.access.group !24
|
|
// CHECK24-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2
|
|
// CHECK24-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !24
|
|
// CHECK24-NEXT: [[CONV7:%.*]] = fpext float [[TMP20]] to double
|
|
// CHECK24-NEXT: [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00
|
|
// CHECK24-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float
|
|
// CHECK24-NEXT: store float [[CONV9]], float* [[ARRAYIDX]], align 4, !llvm.access.group !24
|
|
// CHECK24-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3
|
|
// CHECK24-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX10]], align 4, !llvm.access.group !24
|
|
// CHECK24-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double
|
|
// CHECK24-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00
|
|
// CHECK24-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float
|
|
// CHECK24-NEXT: store float [[CONV13]], float* [[ARRAYIDX10]], align 4, !llvm.access.group !24
|
|
// CHECK24-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1
|
|
// CHECK24-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX14]], i32 0, i32 2
|
|
// CHECK24-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX15]], align 8, !llvm.access.group !24
|
|
// CHECK24-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00
|
|
// CHECK24-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8, !llvm.access.group !24
|
|
// CHECK24-NEXT: [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]]
|
|
// CHECK24-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP23]]
|
|
// CHECK24-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX17]], i32 3
|
|
// CHECK24-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX18]], align 8, !llvm.access.group !24
|
|
// CHECK24-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00
|
|
// CHECK24-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8, !llvm.access.group !24
|
|
// CHECK24-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0
|
|
// CHECK24-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 4, !llvm.access.group !24
|
|
// CHECK24-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1
|
|
// CHECK24-NEXT: store i64 [[ADD20]], i64* [[X]], align 4, !llvm.access.group !24
|
|
// CHECK24-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1
|
|
// CHECK24-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 4, !llvm.access.group !24
|
|
// CHECK24-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i32
|
|
// CHECK24-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1
|
|
// CHECK24-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8
|
|
// CHECK24-NEXT: store i8 [[CONV23]], i8* [[Y]], align 4, !llvm.access.group !24
|
|
// CHECK24-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK24: omp.body.continue:
|
|
// CHECK24-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK24: omp.inner.for.inc:
|
|
// CHECK24-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
|
|
// CHECK24-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1
|
|
// CHECK24-NEXT: store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
|
|
// CHECK24-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]]
|
|
// CHECK24: omp.inner.for.end:
|
|
// CHECK24-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
|
|
// CHECK24: omp.dispatch.inc:
|
|
// CHECK24-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK24-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK24-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]
|
|
// CHECK24-NEXT: store i32 [[ADD25]], i32* [[DOTOMP_LB]], align 4
|
|
// CHECK24-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK24-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK24-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]]
|
|
// CHECK24-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK24-NEXT: br label [[OMP_DISPATCH_COND]]
|
|
// CHECK24: omp.dispatch.end:
|
|
// CHECK24-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]])
|
|
// CHECK24-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK24-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0
|
|
// CHECK24-NEXT: br i1 [[TMP33]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
|
|
// CHECK24: .omp.final.then:
|
|
// CHECK24-NEXT: store i8 96, i8* [[IT]], align 1
|
|
// CHECK24-NEXT: br label [[DOTOMP_FINAL_DONE]]
|
|
// CHECK24: .omp.final.done:
|
|
// CHECK24-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK24-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195
|
|
// CHECK24-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
|
|
// CHECK24-NEXT: entry:
|
|
// CHECK24-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK24-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK24-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK24-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
|
|
// CHECK24-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK24-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK24-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK24-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK24-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
|
|
// CHECK24-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
|
|
// CHECK24-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
|
|
// CHECK24-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
|
|
// CHECK24-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
|
|
// CHECK24-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
|
|
// CHECK24-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK24-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
|
|
// CHECK24-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
|
|
// CHECK24-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
|
|
// CHECK24-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
|
|
// CHECK24-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2
|
|
// CHECK24-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
|
|
// CHECK24-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 4
|
|
// CHECK24-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
|
|
// CHECK24-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1
|
|
// CHECK24-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
|
|
// CHECK24-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]])
|
|
// CHECK24-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK24-LABEL: define {{[^@]+}}@.omp_outlined..4
|
|
// CHECK24-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {
|
|
// CHECK24-NEXT: entry:
|
|
// CHECK24-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK24-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK24-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK24-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK24-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK24-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
|
|
// CHECK24-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK24-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK24-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK24-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK24-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK24-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
|
|
// CHECK24-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
|
|
// CHECK24-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
|
|
// CHECK24-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
|
|
// CHECK24-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
|
|
// CHECK24-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
|
|
// CHECK24-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK24-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214
|
|
// CHECK24-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
|
|
// CHECK24-NEXT: entry:
|
|
// CHECK24-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
|
|
// CHECK24-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK24-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK24-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
|
|
// CHECK24-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4
|
|
// CHECK24-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK24-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK24-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK24-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
|
|
// CHECK24-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK24-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4
|
|
// CHECK24-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]])
|
|
// CHECK24-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK24-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
|
|
// CHECK24-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
|
|
// CHECK24-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
|
|
// CHECK24-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4
|
|
// CHECK24-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK24-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK24-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
|
|
// CHECK24-NEXT: [[TMP3:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
|
|
// CHECK24-NEXT: [[TMP4:%.*]] = load i16*, i16** [[C_ADDR]], align 4
|
|
// CHECK24-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8*
|
|
// CHECK24-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_ADDR]], align 4
|
|
// CHECK24-NEXT: store i32 [[TMP5]], i32* [[B_CASTED]], align 4
|
|
// CHECK24-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4
|
|
// CHECK24-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV]], align 4
|
|
// CHECK24-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP7]] to i1
|
|
// CHECK24-NEXT: [[CONV3:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__CASTED]] to i8*
|
|
// CHECK24-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
|
|
// CHECK24-NEXT: store i8 [[FROMBOOL]], i8* [[CONV3]], align 1
|
|
// CHECK24-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
|
|
// CHECK24-NEXT: [[TMP9:%.*]] = load i8, i8* [[CONV]], align 4
|
|
// CHECK24-NEXT: [[TOBOOL4:%.*]] = trunc i8 [[TMP9]] to i1
|
|
// CHECK24-NEXT: br i1 [[TOBOOL4]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
|
|
// CHECK24: omp_if.then:
|
|
// CHECK24-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP6]], i32 [[TMP2]], i32 [[TMP3]], i16* [[TMP4]], i32 [[TMP8]])
|
|
// CHECK24-NEXT: br label [[OMP_IF_END:%.*]]
|
|
// CHECK24: omp_if.else:
|
|
// CHECK24-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]])
|
|
// CHECK24-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
|
|
// CHECK24-NEXT: call void @.omp_outlined..5(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]], i32 [[TMP6]], i32 [[TMP2]], i32 [[TMP3]], i16* [[TMP4]], i32 [[TMP8]]) #[[ATTR2:[0-9]+]]
|
|
// CHECK24-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]])
|
|
// CHECK24-NEXT: br label [[OMP_IF_END]]
|
|
// CHECK24: omp_if.end:
|
|
// CHECK24-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK24-LABEL: define {{[^@]+}}@.omp_outlined..5
|
|
// CHECK24-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
|
|
// CHECK24-NEXT: entry:
|
|
// CHECK24-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK24-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK24-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
|
|
// CHECK24-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK24-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK24-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
|
|
// CHECK24-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4
|
|
// CHECK24-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK24-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
|
|
// CHECK24-NEXT: [[TMP:%.*]] = alloca i64, align 4
|
|
// CHECK24-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
|
|
// CHECK24-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
|
|
// CHECK24-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
|
|
// CHECK24-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK24-NEXT: [[IT:%.*]] = alloca i64, align 8
|
|
// CHECK24-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK24-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK24-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK24-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
|
|
// CHECK24-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
|
|
// CHECK24-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
|
|
// CHECK24-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4
|
|
// CHECK24-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK24-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK24-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
|
|
// CHECK24-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
|
|
// CHECK24-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
|
|
// CHECK24-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8*
|
|
// CHECK24-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK24-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK24-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
|
|
// CHECK24-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK24-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV]], align 4
|
|
// CHECK24-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1
|
|
// CHECK24-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
|
|
// CHECK24: omp_if.then:
|
|
// CHECK24-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK24-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4
|
|
// CHECK24-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
|
|
// CHECK24-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK24-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP7]], 3
|
|
// CHECK24-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK24: cond.true:
|
|
// CHECK24-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK24: cond.false:
|
|
// CHECK24-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK24-NEXT: br label [[COND_END]]
|
|
// CHECK24: cond.end:
|
|
// CHECK24-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ]
|
|
// CHECK24-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
|
|
// CHECK24-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK24-NEXT: store i64 [[TMP9]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK24-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK24: omp.inner.for.cond:
|
|
// CHECK24-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !27
|
|
// CHECK24-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !27
|
|
// CHECK24-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP10]], [[TMP11]]
|
|
// CHECK24-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK24: omp.inner.for.body:
|
|
// CHECK24-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !27
|
|
// CHECK24-NEXT: [[MUL:%.*]] = mul i64 [[TMP12]], 400
|
|
// CHECK24-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]
|
|
// CHECK24-NEXT: store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !27
|
|
// CHECK24-NEXT: [[TMP13:%.*]] = load i32, i32* [[B_ADDR]], align 4, !llvm.access.group !27
|
|
// CHECK24-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP13]] to double
|
|
// CHECK24-NEXT: [[ADD:%.*]] = fadd double [[CONV4]], 1.500000e+00
|
|
// CHECK24-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
|
|
// CHECK24-NEXT: store double [[ADD]], double* [[A]], align 4, !nontemporal !28, !llvm.access.group !27
|
|
// CHECK24-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
|
|
// CHECK24-NEXT: [[TMP14:%.*]] = load double, double* [[A5]], align 4, !nontemporal !28, !llvm.access.group !27
|
|
// CHECK24-NEXT: [[INC:%.*]] = fadd double [[TMP14]], 1.000000e+00
|
|
// CHECK24-NEXT: store double [[INC]], double* [[A5]], align 4, !nontemporal !28, !llvm.access.group !27
|
|
// CHECK24-NEXT: [[CONV6:%.*]] = fptosi double [[INC]] to i16
|
|
// CHECK24-NEXT: [[TMP15:%.*]] = mul nsw i32 1, [[TMP2]]
|
|
// CHECK24-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP15]]
|
|
// CHECK24-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
|
|
// CHECK24-NEXT: store i16 [[CONV6]], i16* [[ARRAYIDX7]], align 2, !llvm.access.group !27
|
|
// CHECK24-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK24: omp.body.continue:
|
|
// CHECK24-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK24: omp.inner.for.inc:
|
|
// CHECK24-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !27
|
|
// CHECK24-NEXT: [[ADD8:%.*]] = add i64 [[TMP16]], 1
|
|
// CHECK24-NEXT: store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !27
|
|
// CHECK24-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP29:![0-9]+]]
|
|
// CHECK24: omp.inner.for.end:
|
|
// CHECK24-NEXT: br label [[OMP_IF_END:%.*]]
|
|
// CHECK24: omp_if.else:
|
|
// CHECK24-NEXT: [[TMP17:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK24-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP17]], align 4
|
|
// CHECK24-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP18]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
|
|
// CHECK24-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK24-NEXT: [[CMP9:%.*]] = icmp ugt i64 [[TMP19]], 3
|
|
// CHECK24-NEXT: br i1 [[CMP9]], label [[COND_TRUE10:%.*]], label [[COND_FALSE11:%.*]]
|
|
// CHECK24: cond.true10:
|
|
// CHECK24-NEXT: br label [[COND_END12:%.*]]
|
|
// CHECK24: cond.false11:
|
|
// CHECK24-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK24-NEXT: br label [[COND_END12]]
|
|
// CHECK24: cond.end12:
|
|
// CHECK24-NEXT: [[COND13:%.*]] = phi i64 [ 3, [[COND_TRUE10]] ], [ [[TMP20]], [[COND_FALSE11]] ]
|
|
// CHECK24-NEXT: store i64 [[COND13]], i64* [[DOTOMP_UB]], align 8
|
|
// CHECK24-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK24-NEXT: store i64 [[TMP21]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK24-NEXT: br label [[OMP_INNER_FOR_COND14:%.*]]
|
|
// CHECK24: omp.inner.for.cond14:
|
|
// CHECK24-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK24-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK24-NEXT: [[CMP15:%.*]] = icmp ule i64 [[TMP22]], [[TMP23]]
|
|
// CHECK24-NEXT: br i1 [[CMP15]], label [[OMP_INNER_FOR_BODY16:%.*]], label [[OMP_INNER_FOR_END30:%.*]]
|
|
// CHECK24: omp.inner.for.body16:
|
|
// CHECK24-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK24-NEXT: [[MUL17:%.*]] = mul i64 [[TMP24]], 400
|
|
// CHECK24-NEXT: [[SUB18:%.*]] = sub i64 2000, [[MUL17]]
|
|
// CHECK24-NEXT: store i64 [[SUB18]], i64* [[IT]], align 8
|
|
// CHECK24-NEXT: [[TMP25:%.*]] = load i32, i32* [[B_ADDR]], align 4
|
|
// CHECK24-NEXT: [[CONV19:%.*]] = sitofp i32 [[TMP25]] to double
|
|
// CHECK24-NEXT: [[ADD20:%.*]] = fadd double [[CONV19]], 1.500000e+00
|
|
// CHECK24-NEXT: [[A21:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
|
|
// CHECK24-NEXT: store double [[ADD20]], double* [[A21]], align 4
|
|
// CHECK24-NEXT: [[A22:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
|
|
// CHECK24-NEXT: [[TMP26:%.*]] = load double, double* [[A22]], align 4
|
|
// CHECK24-NEXT: [[INC23:%.*]] = fadd double [[TMP26]], 1.000000e+00
|
|
// CHECK24-NEXT: store double [[INC23]], double* [[A22]], align 4
|
|
// CHECK24-NEXT: [[CONV24:%.*]] = fptosi double [[INC23]] to i16
|
|
// CHECK24-NEXT: [[TMP27:%.*]] = mul nsw i32 1, [[TMP2]]
|
|
// CHECK24-NEXT: [[ARRAYIDX25:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP27]]
|
|
// CHECK24-NEXT: [[ARRAYIDX26:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX25]], i32 1
|
|
// CHECK24-NEXT: store i16 [[CONV24]], i16* [[ARRAYIDX26]], align 2
|
|
// CHECK24-NEXT: br label [[OMP_BODY_CONTINUE27:%.*]]
|
|
// CHECK24: omp.body.continue27:
|
|
// CHECK24-NEXT: br label [[OMP_INNER_FOR_INC28:%.*]]
|
|
// CHECK24: omp.inner.for.inc28:
|
|
// CHECK24-NEXT: [[TMP28:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK24-NEXT: [[ADD29:%.*]] = add i64 [[TMP28]], 1
|
|
// CHECK24-NEXT: store i64 [[ADD29]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK24-NEXT: br label [[OMP_INNER_FOR_COND14]], !llvm.loop [[LOOP31:![0-9]+]]
|
|
// CHECK24: omp.inner.for.end30:
|
|
// CHECK24-NEXT: br label [[OMP_IF_END]]
|
|
// CHECK24: omp_if.end:
|
|
// CHECK24-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK24: omp.loop.exit:
|
|
// CHECK24-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK24-NEXT: [[TMP30:%.*]] = load i32, i32* [[TMP29]], align 4
|
|
// CHECK24-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP30]])
|
|
// CHECK24-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK24-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0
|
|
// CHECK24-NEXT: br i1 [[TMP32]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
|
|
// CHECK24: .omp.final.then:
|
|
// CHECK24-NEXT: store i64 400, i64* [[IT]], align 8
|
|
// CHECK24-NEXT: br label [[DOTOMP_FINAL_DONE]]
|
|
// CHECK24: .omp.final.done:
|
|
// CHECK24-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK24-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178
|
|
// CHECK24-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
|
|
// CHECK24-NEXT: entry:
|
|
// CHECK24-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK24-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK24-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
|
|
// CHECK24-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK24-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK24-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK24-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
|
|
// CHECK24-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
|
|
// CHECK24-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
|
|
// CHECK24-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
|
|
// CHECK24-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK24-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
|
|
// CHECK24-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
|
|
// CHECK24-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
|
|
// CHECK24-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
|
|
// CHECK24-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2
|
|
// CHECK24-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
|
|
// CHECK24-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]])
|
|
// CHECK24-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK24-LABEL: define {{[^@]+}}@.omp_outlined..6
|
|
// CHECK24-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {
|
|
// CHECK24-NEXT: entry:
|
|
// CHECK24-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK24-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK24-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK24-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK24-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
|
|
// CHECK24-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
|
|
// CHECK24-NEXT: [[TMP:%.*]] = alloca i64, align 4
|
|
// CHECK24-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
|
|
// CHECK24-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
|
|
// CHECK24-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
|
|
// CHECK24-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK24-NEXT: [[I:%.*]] = alloca i64, align 8
|
|
// CHECK24-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK24-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK24-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK24-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
|
|
// CHECK24-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
|
|
// CHECK24-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
|
|
// CHECK24-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
|
|
// CHECK24-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK24-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK24-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
|
|
// CHECK24-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK24-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK24-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
|
|
// CHECK24-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
|
|
// CHECK24-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK24-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6
|
|
// CHECK24-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK24: cond.true:
|
|
// CHECK24-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK24: cond.false:
|
|
// CHECK24-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK24-NEXT: br label [[COND_END]]
|
|
// CHECK24: cond.end:
|
|
// CHECK24-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
|
|
// CHECK24-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
|
|
// CHECK24-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK24-NEXT: store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK24-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK24: omp.inner.for.cond:
|
|
// CHECK24-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !33
|
|
// CHECK24-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !33
|
|
// CHECK24-NEXT: [[CMP1:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]]
|
|
// CHECK24-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK24: omp.inner.for.body:
|
|
// CHECK24-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !33
|
|
// CHECK24-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3
|
|
// CHECK24-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
|
|
// CHECK24-NEXT: store i64 [[ADD]], i64* [[I]], align 8, !llvm.access.group !33
|
|
// CHECK24-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !33
|
|
// CHECK24-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
|
|
// CHECK24-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4, !llvm.access.group !33
|
|
// CHECK24-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !33
|
|
// CHECK24-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32
|
|
// CHECK24-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
|
|
// CHECK24-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
|
|
// CHECK24-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 4, !llvm.access.group !33
|
|
// CHECK24-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
|
|
// CHECK24-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !33
|
|
// CHECK24-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1
|
|
// CHECK24-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !33
|
|
// CHECK24-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK24: omp.body.continue:
|
|
// CHECK24-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK24: omp.inner.for.inc:
|
|
// CHECK24-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !33
|
|
// CHECK24-NEXT: [[ADD7:%.*]] = add nsw i64 [[TMP12]], 1
|
|
// CHECK24-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !33
|
|
// CHECK24-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP34:![0-9]+]]
|
|
// CHECK24: omp.inner.for.end:
|
|
// CHECK24-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK24: omp.loop.exit:
|
|
// CHECK24-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
|
|
// CHECK24-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK24-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
|
|
// CHECK24-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
|
|
// CHECK24: .omp.final.then:
|
|
// CHECK24-NEXT: store i64 11, i64* [[I]], align 8
|
|
// CHECK24-NEXT: br label [[DOTOMP_FINAL_DONE]]
|
|
// CHECK24: .omp.final.done:
|
|
// CHECK24-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK25-LABEL: define {{[^@]+}}@_Z7get_valv
|
|
// CHECK25-SAME: () #[[ATTR0:[0-9]+]] {
|
|
// CHECK25-NEXT: entry:
|
|
// CHECK25-NEXT: ret i64 0
|
|
//
|
|
//
|
|
// CHECK25-LABEL: define {{[^@]+}}@_Z3fooi
|
|
// CHECK25-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
|
|
// CHECK25-NEXT: entry:
|
|
// CHECK25-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK25-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK25-NEXT: [[AA:%.*]] = alloca i16, align 2
|
|
// CHECK25-NEXT: [[B:%.*]] = alloca [10 x float], align 4
|
|
// CHECK25-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8
|
|
// CHECK25-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8
|
|
// CHECK25-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8
|
|
// CHECK25-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8
|
|
// CHECK25-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8
|
|
// CHECK25-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK25-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK25-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK25-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK25-NEXT: [[I:%.*]] = alloca i32, align 4
|
|
// CHECK25-NEXT: [[K:%.*]] = alloca i64, align 8
|
|
// CHECK25-NEXT: [[_TMP3:%.*]] = alloca i32, align 4
|
|
// CHECK25-NEXT: [[DOTOMP_LB4:%.*]] = alloca i32, align 4
|
|
// CHECK25-NEXT: [[DOTOMP_UB5:%.*]] = alloca i32, align 4
|
|
// CHECK25-NEXT: [[DOTOMP_IV6:%.*]] = alloca i32, align 4
|
|
// CHECK25-NEXT: [[DOTLINEAR_START:%.*]] = alloca i64, align 8
|
|
// CHECK25-NEXT: [[I7:%.*]] = alloca i32, align 4
|
|
// CHECK25-NEXT: [[K8:%.*]] = alloca i64, align 8
|
|
// CHECK25-NEXT: [[LIN:%.*]] = alloca i32, align 4
|
|
// CHECK25-NEXT: [[_TMP21:%.*]] = alloca i64, align 8
|
|
// CHECK25-NEXT: [[DOTOMP_LB22:%.*]] = alloca i64, align 8
|
|
// CHECK25-NEXT: [[DOTOMP_UB23:%.*]] = alloca i64, align 8
|
|
// CHECK25-NEXT: [[DOTOMP_IV24:%.*]] = alloca i64, align 8
|
|
// CHECK25-NEXT: [[DOTLINEAR_START25:%.*]] = alloca i32, align 4
|
|
// CHECK25-NEXT: [[DOTLINEAR_START26:%.*]] = alloca i32, align 4
|
|
// CHECK25-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8
|
|
// CHECK25-NEXT: [[IT:%.*]] = alloca i64, align 8
|
|
// CHECK25-NEXT: [[LIN28:%.*]] = alloca i32, align 4
|
|
// CHECK25-NEXT: [[A29:%.*]] = alloca i32, align 4
|
|
// CHECK25-NEXT: [[_TMP58:%.*]] = alloca i16, align 2
|
|
// CHECK25-NEXT: [[DOTOMP_LB59:%.*]] = alloca i32, align 4
|
|
// CHECK25-NEXT: [[DOTOMP_UB60:%.*]] = alloca i32, align 4
|
|
// CHECK25-NEXT: [[DOTOMP_IV61:%.*]] = alloca i32, align 4
|
|
// CHECK25-NEXT: [[IT62:%.*]] = alloca i16, align 2
|
|
// CHECK25-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
|
// CHECK25-NEXT: [[_TMP77:%.*]] = alloca i8, align 1
|
|
// CHECK25-NEXT: [[DOTOMP_LB78:%.*]] = alloca i32, align 4
|
|
// CHECK25-NEXT: [[DOTOMP_UB79:%.*]] = alloca i32, align 4
|
|
// CHECK25-NEXT: [[DOTOMP_IV80:%.*]] = alloca i32, align 4
|
|
// CHECK25-NEXT: [[IT81:%.*]] = alloca i8, align 1
|
|
// CHECK25-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK25-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK25-NEXT: store i16 0, i16* [[AA]], align 2
|
|
// CHECK25-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK25-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
|
|
// CHECK25-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave()
|
|
// CHECK25-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8
|
|
// CHECK25-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4
|
|
// CHECK25-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8
|
|
// CHECK25-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK25-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64
|
|
// CHECK25-NEXT: [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]]
|
|
// CHECK25-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8
|
|
// CHECK25-NEXT: store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8
|
|
// CHECK25-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK25-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK25-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK25-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK25: omp.inner.for.cond:
|
|
// CHECK25-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
|
|
// CHECK25-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !2
|
|
// CHECK25-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
|
|
// CHECK25-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK25: omp.inner.for.body:
|
|
// CHECK25-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
|
|
// CHECK25-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 5
|
|
// CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]]
|
|
// CHECK25-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !2
|
|
// CHECK25-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK25: omp.body.continue:
|
|
// CHECK25-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK25: omp.inner.for.inc:
|
|
// CHECK25-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
|
|
// CHECK25-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1
|
|
// CHECK25-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
|
|
// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]
|
|
// CHECK25: omp.inner.for.end:
|
|
// CHECK25-NEXT: store i32 33, i32* [[I]], align 4
|
|
// CHECK25-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv()
|
|
// CHECK25-NEXT: store i64 [[CALL]], i64* [[K]], align 8
|
|
// CHECK25-NEXT: store i32 0, i32* [[DOTOMP_LB4]], align 4
|
|
// CHECK25-NEXT: store i32 8, i32* [[DOTOMP_UB5]], align 4
|
|
// CHECK25-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_LB4]], align 4
|
|
// CHECK25-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV6]], align 4
|
|
// CHECK25-NEXT: [[TMP12:%.*]] = load i64, i64* [[K]], align 8
|
|
// CHECK25-NEXT: store i64 [[TMP12]], i64* [[DOTLINEAR_START]], align 8
|
|
// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND9:%.*]]
|
|
// CHECK25: omp.inner.for.cond9:
|
|
// CHECK25-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !6
|
|
// CHECK25-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB5]], align 4, !llvm.access.group !6
|
|
// CHECK25-NEXT: [[CMP10:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
|
|
// CHECK25-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY11:%.*]], label [[OMP_INNER_FOR_END19:%.*]]
|
|
// CHECK25: omp.inner.for.body11:
|
|
// CHECK25-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !6
|
|
// CHECK25-NEXT: [[MUL12:%.*]] = mul nsw i32 [[TMP15]], 1
|
|
// CHECK25-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL12]]
|
|
// CHECK25-NEXT: store i32 [[SUB]], i32* [[I7]], align 4, !llvm.access.group !6
|
|
// CHECK25-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8, !llvm.access.group !6
|
|
// CHECK25-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !6
|
|
// CHECK25-NEXT: [[MUL13:%.*]] = mul nsw i32 [[TMP17]], 3
|
|
// CHECK25-NEXT: [[CONV:%.*]] = sext i32 [[MUL13]] to i64
|
|
// CHECK25-NEXT: [[ADD14:%.*]] = add nsw i64 [[TMP16]], [[CONV]]
|
|
// CHECK25-NEXT: store i64 [[ADD14]], i64* [[K8]], align 8, !llvm.access.group !6
|
|
// CHECK25-NEXT: [[TMP18:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !6
|
|
// CHECK25-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP18]], 1
|
|
// CHECK25-NEXT: store i32 [[ADD15]], i32* [[A]], align 4, !llvm.access.group !6
|
|
// CHECK25-NEXT: br label [[OMP_BODY_CONTINUE16:%.*]]
|
|
// CHECK25: omp.body.continue16:
|
|
// CHECK25-NEXT: br label [[OMP_INNER_FOR_INC17:%.*]]
|
|
// CHECK25: omp.inner.for.inc17:
|
|
// CHECK25-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !6
|
|
// CHECK25-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP19]], 1
|
|
// CHECK25-NEXT: store i32 [[ADD18]], i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !6
|
|
// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND9]], !llvm.loop [[LOOP7:![0-9]+]]
|
|
// CHECK25: omp.inner.for.end19:
|
|
// CHECK25-NEXT: store i32 1, i32* [[I7]], align 4
|
|
// CHECK25-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8
|
|
// CHECK25-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP20]], 27
|
|
// CHECK25-NEXT: store i64 [[ADD20]], i64* [[K]], align 8
|
|
// CHECK25-NEXT: store i32 12, i32* [[LIN]], align 4
|
|
// CHECK25-NEXT: store i64 0, i64* [[DOTOMP_LB22]], align 8
|
|
// CHECK25-NEXT: store i64 3, i64* [[DOTOMP_UB23]], align 8
|
|
// CHECK25-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_LB22]], align 8
|
|
// CHECK25-NEXT: store i64 [[TMP21]], i64* [[DOTOMP_IV24]], align 8
|
|
// CHECK25-NEXT: [[TMP22:%.*]] = load i32, i32* [[LIN]], align 4
|
|
// CHECK25-NEXT: store i32 [[TMP22]], i32* [[DOTLINEAR_START25]], align 4
|
|
// CHECK25-NEXT: [[TMP23:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK25-NEXT: store i32 [[TMP23]], i32* [[DOTLINEAR_START26]], align 4
|
|
// CHECK25-NEXT: [[CALL27:%.*]] = call i64 @_Z7get_valv()
|
|
// CHECK25-NEXT: store i64 [[CALL27]], i64* [[DOTLINEAR_STEP]], align 8
|
|
// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND30:%.*]]
|
|
// CHECK25: omp.inner.for.cond30:
|
|
// CHECK25-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !9
|
|
// CHECK25-NEXT: [[TMP25:%.*]] = load i64, i64* [[DOTOMP_UB23]], align 8, !llvm.access.group !9
|
|
// CHECK25-NEXT: [[CMP31:%.*]] = icmp ule i64 [[TMP24]], [[TMP25]]
|
|
// CHECK25-NEXT: br i1 [[CMP31]], label [[OMP_INNER_FOR_BODY32:%.*]], label [[OMP_INNER_FOR_END49:%.*]]
|
|
// CHECK25: omp.inner.for.body32:
|
|
// CHECK25-NEXT: [[TMP26:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !9
|
|
// CHECK25-NEXT: [[MUL33:%.*]] = mul i64 [[TMP26]], 400
|
|
// CHECK25-NEXT: [[SUB34:%.*]] = sub i64 2000, [[MUL33]]
|
|
// CHECK25-NEXT: store i64 [[SUB34]], i64* [[IT]], align 8, !llvm.access.group !9
|
|
// CHECK25-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTLINEAR_START25]], align 4, !llvm.access.group !9
|
|
// CHECK25-NEXT: [[CONV35:%.*]] = sext i32 [[TMP27]] to i64
|
|
// CHECK25-NEXT: [[TMP28:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !9
|
|
// CHECK25-NEXT: [[TMP29:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !9
|
|
// CHECK25-NEXT: [[MUL36:%.*]] = mul i64 [[TMP28]], [[TMP29]]
|
|
// CHECK25-NEXT: [[ADD37:%.*]] = add i64 [[CONV35]], [[MUL36]]
|
|
// CHECK25-NEXT: [[CONV38:%.*]] = trunc i64 [[ADD37]] to i32
|
|
// CHECK25-NEXT: store i32 [[CONV38]], i32* [[LIN28]], align 4, !llvm.access.group !9
|
|
// CHECK25-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTLINEAR_START26]], align 4, !llvm.access.group !9
|
|
// CHECK25-NEXT: [[CONV39:%.*]] = sext i32 [[TMP30]] to i64
|
|
// CHECK25-NEXT: [[TMP31:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !9
|
|
// CHECK25-NEXT: [[TMP32:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !9
|
|
// CHECK25-NEXT: [[MUL40:%.*]] = mul i64 [[TMP31]], [[TMP32]]
|
|
// CHECK25-NEXT: [[ADD41:%.*]] = add i64 [[CONV39]], [[MUL40]]
|
|
// CHECK25-NEXT: [[CONV42:%.*]] = trunc i64 [[ADD41]] to i32
|
|
// CHECK25-NEXT: store i32 [[CONV42]], i32* [[A29]], align 4, !llvm.access.group !9
|
|
// CHECK25-NEXT: [[TMP33:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !9
|
|
// CHECK25-NEXT: [[CONV43:%.*]] = sext i16 [[TMP33]] to i32
|
|
// CHECK25-NEXT: [[ADD44:%.*]] = add nsw i32 [[CONV43]], 1
|
|
// CHECK25-NEXT: [[CONV45:%.*]] = trunc i32 [[ADD44]] to i16
|
|
// CHECK25-NEXT: store i16 [[CONV45]], i16* [[AA]], align 2, !llvm.access.group !9
|
|
// CHECK25-NEXT: br label [[OMP_BODY_CONTINUE46:%.*]]
|
|
// CHECK25: omp.body.continue46:
|
|
// CHECK25-NEXT: br label [[OMP_INNER_FOR_INC47:%.*]]
|
|
// CHECK25: omp.inner.for.inc47:
|
|
// CHECK25-NEXT: [[TMP34:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !9
|
|
// CHECK25-NEXT: [[ADD48:%.*]] = add i64 [[TMP34]], 1
|
|
// CHECK25-NEXT: store i64 [[ADD48]], i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !9
|
|
// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND30]], !llvm.loop [[LOOP10:![0-9]+]]
|
|
// CHECK25: omp.inner.for.end49:
|
|
// CHECK25-NEXT: store i64 400, i64* [[IT]], align 8
|
|
// CHECK25-NEXT: [[TMP35:%.*]] = load i32, i32* [[DOTLINEAR_START25]], align 4
|
|
// CHECK25-NEXT: [[CONV50:%.*]] = sext i32 [[TMP35]] to i64
|
|
// CHECK25-NEXT: [[TMP36:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
|
|
// CHECK25-NEXT: [[MUL51:%.*]] = mul i64 4, [[TMP36]]
|
|
// CHECK25-NEXT: [[ADD52:%.*]] = add i64 [[CONV50]], [[MUL51]]
|
|
// CHECK25-NEXT: [[CONV53:%.*]] = trunc i64 [[ADD52]] to i32
|
|
// CHECK25-NEXT: store i32 [[CONV53]], i32* [[LIN]], align 4
|
|
// CHECK25-NEXT: [[TMP37:%.*]] = load i32, i32* [[DOTLINEAR_START26]], align 4
|
|
// CHECK25-NEXT: [[CONV54:%.*]] = sext i32 [[TMP37]] to i64
|
|
// CHECK25-NEXT: [[TMP38:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
|
|
// CHECK25-NEXT: [[MUL55:%.*]] = mul i64 4, [[TMP38]]
|
|
// CHECK25-NEXT: [[ADD56:%.*]] = add i64 [[CONV54]], [[MUL55]]
|
|
// CHECK25-NEXT: [[CONV57:%.*]] = trunc i64 [[ADD56]] to i32
|
|
// CHECK25-NEXT: store i32 [[CONV57]], i32* [[A]], align 4
|
|
// CHECK25-NEXT: store i32 0, i32* [[DOTOMP_LB59]], align 4
|
|
// CHECK25-NEXT: store i32 3, i32* [[DOTOMP_UB60]], align 4
|
|
// CHECK25-NEXT: [[TMP39:%.*]] = load i32, i32* [[DOTOMP_LB59]], align 4
|
|
// CHECK25-NEXT: store i32 [[TMP39]], i32* [[DOTOMP_IV61]], align 4
|
|
// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND63:%.*]]
|
|
// CHECK25: omp.inner.for.cond63:
|
|
// CHECK25-NEXT: [[TMP40:%.*]] = load i32, i32* [[DOTOMP_IV61]], align 4, !llvm.access.group !12
|
|
// CHECK25-NEXT: [[TMP41:%.*]] = load i32, i32* [[DOTOMP_UB60]], align 4, !llvm.access.group !12
|
|
// CHECK25-NEXT: [[CMP64:%.*]] = icmp sle i32 [[TMP40]], [[TMP41]]
|
|
// CHECK25-NEXT: br i1 [[CMP64]], label [[OMP_INNER_FOR_BODY65:%.*]], label [[OMP_INNER_FOR_END76:%.*]]
|
|
// CHECK25: omp.inner.for.body65:
|
|
// CHECK25-NEXT: [[TMP42:%.*]] = load i32, i32* [[DOTOMP_IV61]], align 4, !llvm.access.group !12
|
|
// CHECK25-NEXT: [[MUL66:%.*]] = mul nsw i32 [[TMP42]], 4
|
|
// CHECK25-NEXT: [[ADD67:%.*]] = add nsw i32 6, [[MUL66]]
|
|
// CHECK25-NEXT: [[CONV68:%.*]] = trunc i32 [[ADD67]] to i16
|
|
// CHECK25-NEXT: store i16 [[CONV68]], i16* [[IT62]], align 2, !llvm.access.group !12
|
|
// CHECK25-NEXT: [[TMP43:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !12
|
|
// CHECK25-NEXT: [[ADD69:%.*]] = add nsw i32 [[TMP43]], 1
|
|
// CHECK25-NEXT: store i32 [[ADD69]], i32* [[A]], align 4, !llvm.access.group !12
|
|
// CHECK25-NEXT: [[TMP44:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !12
|
|
// CHECK25-NEXT: [[CONV70:%.*]] = sext i16 [[TMP44]] to i32
|
|
// CHECK25-NEXT: [[ADD71:%.*]] = add nsw i32 [[CONV70]], 1
|
|
// CHECK25-NEXT: [[CONV72:%.*]] = trunc i32 [[ADD71]] to i16
|
|
// CHECK25-NEXT: store i16 [[CONV72]], i16* [[AA]], align 2, !llvm.access.group !12
|
|
// CHECK25-NEXT: br label [[OMP_BODY_CONTINUE73:%.*]]
|
|
// CHECK25: omp.body.continue73:
|
|
// CHECK25-NEXT: br label [[OMP_INNER_FOR_INC74:%.*]]
|
|
// CHECK25: omp.inner.for.inc74:
|
|
// CHECK25-NEXT: [[TMP45:%.*]] = load i32, i32* [[DOTOMP_IV61]], align 4, !llvm.access.group !12
|
|
// CHECK25-NEXT: [[ADD75:%.*]] = add nsw i32 [[TMP45]], 1
|
|
// CHECK25-NEXT: store i32 [[ADD75]], i32* [[DOTOMP_IV61]], align 4, !llvm.access.group !12
|
|
// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND63]], !llvm.loop [[LOOP13:![0-9]+]]
|
|
// CHECK25: omp.inner.for.end76:
|
|
// CHECK25-NEXT: store i16 22, i16* [[IT62]], align 2
|
|
// CHECK25-NEXT: [[TMP46:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK25-NEXT: store i32 [[TMP46]], i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK25-NEXT: store i32 0, i32* [[DOTOMP_LB78]], align 4
|
|
// CHECK25-NEXT: store i32 25, i32* [[DOTOMP_UB79]], align 4
|
|
// CHECK25-NEXT: [[TMP47:%.*]] = load i32, i32* [[DOTOMP_LB78]], align 4
|
|
// CHECK25-NEXT: store i32 [[TMP47]], i32* [[DOTOMP_IV80]], align 4
|
|
// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND82:%.*]]
|
|
// CHECK25: omp.inner.for.cond82:
|
|
// CHECK25-NEXT: [[TMP48:%.*]] = load i32, i32* [[DOTOMP_IV80]], align 4, !llvm.access.group !15
|
|
// CHECK25-NEXT: [[TMP49:%.*]] = load i32, i32* [[DOTOMP_UB79]], align 4, !llvm.access.group !15
|
|
// CHECK25-NEXT: [[CMP83:%.*]] = icmp sle i32 [[TMP48]], [[TMP49]]
|
|
// CHECK25-NEXT: br i1 [[CMP83]], label [[OMP_INNER_FOR_BODY84:%.*]], label [[OMP_INNER_FOR_END109:%.*]]
|
|
// CHECK25: omp.inner.for.body84:
|
|
// CHECK25-NEXT: [[TMP50:%.*]] = load i32, i32* [[DOTOMP_IV80]], align 4, !llvm.access.group !15
|
|
// CHECK25-NEXT: [[MUL85:%.*]] = mul nsw i32 [[TMP50]], 1
|
|
// CHECK25-NEXT: [[SUB86:%.*]] = sub nsw i32 122, [[MUL85]]
|
|
// CHECK25-NEXT: [[CONV87:%.*]] = trunc i32 [[SUB86]] to i8
|
|
// CHECK25-NEXT: store i8 [[CONV87]], i8* [[IT81]], align 1, !llvm.access.group !15
|
|
// CHECK25-NEXT: [[TMP51:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !15
|
|
// CHECK25-NEXT: [[ADD88:%.*]] = add nsw i32 [[TMP51]], 1
|
|
// CHECK25-NEXT: store i32 [[ADD88]], i32* [[A]], align 4, !llvm.access.group !15
|
|
// CHECK25-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 2
|
|
// CHECK25-NEXT: [[TMP52:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !15
|
|
// CHECK25-NEXT: [[CONV89:%.*]] = fpext float [[TMP52]] to double
|
|
// CHECK25-NEXT: [[ADD90:%.*]] = fadd double [[CONV89]], 1.000000e+00
|
|
// CHECK25-NEXT: [[CONV91:%.*]] = fptrunc double [[ADD90]] to float
|
|
// CHECK25-NEXT: store float [[CONV91]], float* [[ARRAYIDX]], align 4, !llvm.access.group !15
|
|
// CHECK25-NEXT: [[ARRAYIDX92:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 3
|
|
// CHECK25-NEXT: [[TMP53:%.*]] = load float, float* [[ARRAYIDX92]], align 4, !llvm.access.group !15
|
|
// CHECK25-NEXT: [[CONV93:%.*]] = fpext float [[TMP53]] to double
|
|
// CHECK25-NEXT: [[ADD94:%.*]] = fadd double [[CONV93]], 1.000000e+00
|
|
// CHECK25-NEXT: [[CONV95:%.*]] = fptrunc double [[ADD94]] to float
|
|
// CHECK25-NEXT: store float [[CONV95]], float* [[ARRAYIDX92]], align 4, !llvm.access.group !15
|
|
// CHECK25-NEXT: [[ARRAYIDX96:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i64 0, i64 1
|
|
// CHECK25-NEXT: [[ARRAYIDX97:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX96]], i64 0, i64 2
|
|
// CHECK25-NEXT: [[TMP54:%.*]] = load double, double* [[ARRAYIDX97]], align 8, !llvm.access.group !15
|
|
// CHECK25-NEXT: [[ADD98:%.*]] = fadd double [[TMP54]], 1.000000e+00
|
|
// CHECK25-NEXT: store double [[ADD98]], double* [[ARRAYIDX97]], align 8, !llvm.access.group !15
|
|
// CHECK25-NEXT: [[TMP55:%.*]] = mul nsw i64 1, [[TMP4]]
|
|
// CHECK25-NEXT: [[ARRAYIDX99:%.*]] = getelementptr inbounds double, double* [[VLA1]], i64 [[TMP55]]
|
|
// CHECK25-NEXT: [[ARRAYIDX100:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX99]], i64 3
|
|
// CHECK25-NEXT: [[TMP56:%.*]] = load double, double* [[ARRAYIDX100]], align 8, !llvm.access.group !15
|
|
// CHECK25-NEXT: [[ADD101:%.*]] = fadd double [[TMP56]], 1.000000e+00
|
|
// CHECK25-NEXT: store double [[ADD101]], double* [[ARRAYIDX100]], align 8, !llvm.access.group !15
|
|
// CHECK25-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0
|
|
// CHECK25-NEXT: [[TMP57:%.*]] = load i64, i64* [[X]], align 8, !llvm.access.group !15
|
|
// CHECK25-NEXT: [[ADD102:%.*]] = add nsw i64 [[TMP57]], 1
|
|
// CHECK25-NEXT: store i64 [[ADD102]], i64* [[X]], align 8, !llvm.access.group !15
|
|
// CHECK25-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1
|
|
// CHECK25-NEXT: [[TMP58:%.*]] = load i8, i8* [[Y]], align 8, !llvm.access.group !15
|
|
// CHECK25-NEXT: [[CONV103:%.*]] = sext i8 [[TMP58]] to i32
|
|
// CHECK25-NEXT: [[ADD104:%.*]] = add nsw i32 [[CONV103]], 1
|
|
// CHECK25-NEXT: [[CONV105:%.*]] = trunc i32 [[ADD104]] to i8
|
|
// CHECK25-NEXT: store i8 [[CONV105]], i8* [[Y]], align 8, !llvm.access.group !15
|
|
// CHECK25-NEXT: br label [[OMP_BODY_CONTINUE106:%.*]]
|
|
// CHECK25: omp.body.continue106:
|
|
// CHECK25-NEXT: br label [[OMP_INNER_FOR_INC107:%.*]]
|
|
// CHECK25: omp.inner.for.inc107:
|
|
// CHECK25-NEXT: [[TMP59:%.*]] = load i32, i32* [[DOTOMP_IV80]], align 4, !llvm.access.group !15
|
|
// CHECK25-NEXT: [[ADD108:%.*]] = add nsw i32 [[TMP59]], 1
|
|
// CHECK25-NEXT: store i32 [[ADD108]], i32* [[DOTOMP_IV80]], align 4, !llvm.access.group !15
|
|
// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND82]], !llvm.loop [[LOOP16:![0-9]+]]
|
|
// CHECK25: omp.inner.for.end109:
|
|
// CHECK25-NEXT: store i8 96, i8* [[IT81]], align 1
|
|
// CHECK25-NEXT: [[TMP60:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK25-NEXT: [[TMP61:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
|
|
// CHECK25-NEXT: call void @llvm.stackrestore(i8* [[TMP61]])
|
|
// CHECK25-NEXT: ret i32 [[TMP60]]
|
|
//
|
|
//
|
|
// CHECK25-LABEL: define {{[^@]+}}@_Z3bari
|
|
// CHECK25-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
|
|
// CHECK25-NEXT: entry:
|
|
// CHECK25-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK25-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK25-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8
|
|
// CHECK25-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK25-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK25-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK25-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]])
|
|
// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
|
|
// CHECK25-NEXT: store i32 [[ADD]], i32* [[A]], align 4
|
|
// CHECK25-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK25-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]])
|
|
// CHECK25-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK25-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
|
|
// CHECK25-NEXT: store i32 [[ADD2]], i32* [[A]], align 4
|
|
// CHECK25-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK25-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]])
|
|
// CHECK25-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK25-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
|
|
// CHECK25-NEXT: store i32 [[ADD4]], i32* [[A]], align 4
|
|
// CHECK25-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK25-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]])
|
|
// CHECK25-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK25-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
|
|
// CHECK25-NEXT: store i32 [[ADD6]], i32* [[A]], align 4
|
|
// CHECK25-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK25-NEXT: ret i32 [[TMP8]]
|
|
//
|
|
//
|
|
// CHECK25-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
|
|
// CHECK25-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 {
|
|
// CHECK25-NEXT: entry:
|
|
// CHECK25-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
|
|
// CHECK25-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK25-NEXT: [[B:%.*]] = alloca i32, align 4
|
|
// CHECK25-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8
|
|
// CHECK25-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8
|
|
// CHECK25-NEXT: [[TMP:%.*]] = alloca i64, align 8
|
|
// CHECK25-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
|
|
// CHECK25-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
|
|
// CHECK25-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
|
|
// CHECK25-NEXT: [[IT:%.*]] = alloca i64, align 8
|
|
// CHECK25-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK25-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK25-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK25-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
|
|
// CHECK25-NEXT: store i32 [[ADD]], i32* [[B]], align 4
|
|
// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK25-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
|
|
// CHECK25-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave()
|
|
// CHECK25-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8
|
|
// CHECK25-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]]
|
|
// CHECK25-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2
|
|
// CHECK25-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8
|
|
// CHECK25-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK25-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK25-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK25-NEXT: store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK25: omp.inner.for.cond:
|
|
// CHECK25-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18
|
|
// CHECK25-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !18
|
|
// CHECK25-NEXT: [[CMP:%.*]] = icmp ule i64 [[TMP6]], [[TMP7]]
|
|
// CHECK25-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK25: omp.inner.for.body:
|
|
// CHECK25-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18
|
|
// CHECK25-NEXT: [[MUL:%.*]] = mul i64 [[TMP8]], 400
|
|
// CHECK25-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]
|
|
// CHECK25-NEXT: store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !18
|
|
// CHECK25-NEXT: [[TMP9:%.*]] = load i32, i32* [[B]], align 4, !llvm.access.group !18
|
|
// CHECK25-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP9]] to double
|
|
// CHECK25-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00
|
|
// CHECK25-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
|
|
// CHECK25-NEXT: store double [[ADD2]], double* [[A]], align 8, !llvm.access.group !18
|
|
// CHECK25-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
|
|
// CHECK25-NEXT: [[TMP10:%.*]] = load double, double* [[A3]], align 8, !llvm.access.group !18
|
|
// CHECK25-NEXT: [[INC:%.*]] = fadd double [[TMP10]], 1.000000e+00
|
|
// CHECK25-NEXT: store double [[INC]], double* [[A3]], align 8, !llvm.access.group !18
|
|
// CHECK25-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16
|
|
// CHECK25-NEXT: [[TMP11:%.*]] = mul nsw i64 1, [[TMP2]]
|
|
// CHECK25-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP11]]
|
|
// CHECK25-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
|
|
// CHECK25-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2, !llvm.access.group !18
|
|
// CHECK25-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK25: omp.body.continue:
|
|
// CHECK25-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK25: omp.inner.for.inc:
|
|
// CHECK25-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18
|
|
// CHECK25-NEXT: [[ADD6:%.*]] = add i64 [[TMP12]], 1
|
|
// CHECK25-NEXT: store i64 [[ADD6]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18
|
|
// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]
|
|
// CHECK25: omp.inner.for.end:
|
|
// CHECK25-NEXT: store i64 400, i64* [[IT]], align 8
|
|
// CHECK25-NEXT: [[TMP13:%.*]] = mul nsw i64 1, [[TMP2]]
|
|
// CHECK25-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP13]]
|
|
// CHECK25-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX7]], i64 1
|
|
// CHECK25-NEXT: [[TMP14:%.*]] = load i16, i16* [[ARRAYIDX8]], align 2
|
|
// CHECK25-NEXT: [[CONV9:%.*]] = sext i16 [[TMP14]] to i32
|
|
// CHECK25-NEXT: [[TMP15:%.*]] = load i32, i32* [[B]], align 4
|
|
// CHECK25-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[TMP15]]
|
|
// CHECK25-NEXT: [[TMP16:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
|
|
// CHECK25-NEXT: call void @llvm.stackrestore(i8* [[TMP16]])
|
|
// CHECK25-NEXT: ret i32 [[ADD10]]
|
|
//
|
|
//
|
|
// CHECK25-LABEL: define {{[^@]+}}@_ZL7fstatici
|
|
// CHECK25-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
|
|
// CHECK25-NEXT: entry:
|
|
// CHECK25-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK25-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK25-NEXT: [[AA:%.*]] = alloca i16, align 2
|
|
// CHECK25-NEXT: [[AAA:%.*]] = alloca i8, align 1
|
|
// CHECK25-NEXT: [[B:%.*]] = alloca [10 x i32], align 4
|
|
// CHECK25-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK25-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK25-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK25-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK25-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK25-NEXT: store i16 0, i16* [[AA]], align 2
|
|
// CHECK25-NEXT: store i8 0, i8* [[AAA]], align 1
|
|
// CHECK25-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK25-NEXT: store i32 429496720, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK25-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK25-NEXT: ret i32 [[TMP0]]
|
|
//
|
|
//
|
|
// CHECK25-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
|
|
// CHECK25-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat {
|
|
// CHECK25-NEXT: entry:
|
|
// CHECK25-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK25-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK25-NEXT: [[AA:%.*]] = alloca i16, align 2
|
|
// CHECK25-NEXT: [[B:%.*]] = alloca [10 x i32], align 4
|
|
// CHECK25-NEXT: [[TMP:%.*]] = alloca i64, align 8
|
|
// CHECK25-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
|
|
// CHECK25-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
|
|
// CHECK25-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
|
|
// CHECK25-NEXT: [[I:%.*]] = alloca i64, align 8
|
|
// CHECK25-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK25-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK25-NEXT: store i16 0, i16* [[AA]], align 2
|
|
// CHECK25-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK25-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK25-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK25-NEXT: store i64 [[TMP0]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK25: omp.inner.for.cond:
|
|
// CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !21
|
|
// CHECK25-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !21
|
|
// CHECK25-NEXT: [[CMP:%.*]] = icmp sle i64 [[TMP1]], [[TMP2]]
|
|
// CHECK25-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK25: omp.inner.for.body:
|
|
// CHECK25-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !21
|
|
// CHECK25-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP3]], 3
|
|
// CHECK25-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
|
|
// CHECK25-NEXT: store i64 [[ADD]], i64* [[I]], align 8, !llvm.access.group !21
|
|
// CHECK25-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !21
|
|
// CHECK25-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1
|
|
// CHECK25-NEXT: store i32 [[ADD1]], i32* [[A]], align 4, !llvm.access.group !21
|
|
// CHECK25-NEXT: [[TMP5:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !21
|
|
// CHECK25-NEXT: [[CONV:%.*]] = sext i16 [[TMP5]] to i32
|
|
// CHECK25-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 1
|
|
// CHECK25-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
|
|
// CHECK25-NEXT: store i16 [[CONV3]], i16* [[AA]], align 2, !llvm.access.group !21
|
|
// CHECK25-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2
|
|
// CHECK25-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !21
|
|
// CHECK25-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP6]], 1
|
|
// CHECK25-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !21
|
|
// CHECK25-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK25: omp.body.continue:
|
|
// CHECK25-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK25: omp.inner.for.inc:
|
|
// CHECK25-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !21
|
|
// CHECK25-NEXT: [[ADD5:%.*]] = add nsw i64 [[TMP7]], 1
|
|
// CHECK25-NEXT: store i64 [[ADD5]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !21
|
|
// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]]
|
|
// CHECK25: omp.inner.for.end:
|
|
// CHECK25-NEXT: store i64 11, i64* [[I]], align 8
|
|
// CHECK25-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK25-NEXT: ret i32 [[TMP8]]
|
|
//
|
|
//
|
|
// CHECK26-LABEL: define {{[^@]+}}@_Z7get_valv
|
|
// CHECK26-SAME: () #[[ATTR0:[0-9]+]] {
|
|
// CHECK26-NEXT: entry:
|
|
// CHECK26-NEXT: ret i64 0
|
|
//
|
|
//
|
|
// CHECK26-LABEL: define {{[^@]+}}@_Z3fooi
|
|
// CHECK26-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
|
|
// CHECK26-NEXT: entry:
|
|
// CHECK26-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK26-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK26-NEXT: [[AA:%.*]] = alloca i16, align 2
|
|
// CHECK26-NEXT: [[B:%.*]] = alloca [10 x float], align 4
|
|
// CHECK26-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8
|
|
// CHECK26-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8
|
|
// CHECK26-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8
|
|
// CHECK26-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8
|
|
// CHECK26-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8
|
|
// CHECK26-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK26-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK26-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK26-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK26-NEXT: [[I:%.*]] = alloca i32, align 4
|
|
// CHECK26-NEXT: [[K:%.*]] = alloca i64, align 8
|
|
// CHECK26-NEXT: [[_TMP3:%.*]] = alloca i32, align 4
|
|
// CHECK26-NEXT: [[DOTOMP_LB4:%.*]] = alloca i32, align 4
|
|
// CHECK26-NEXT: [[DOTOMP_UB5:%.*]] = alloca i32, align 4
|
|
// CHECK26-NEXT: [[DOTOMP_IV6:%.*]] = alloca i32, align 4
|
|
// CHECK26-NEXT: [[DOTLINEAR_START:%.*]] = alloca i64, align 8
|
|
// CHECK26-NEXT: [[I7:%.*]] = alloca i32, align 4
|
|
// CHECK26-NEXT: [[K8:%.*]] = alloca i64, align 8
|
|
// CHECK26-NEXT: [[LIN:%.*]] = alloca i32, align 4
|
|
// CHECK26-NEXT: [[_TMP21:%.*]] = alloca i64, align 8
|
|
// CHECK26-NEXT: [[DOTOMP_LB22:%.*]] = alloca i64, align 8
|
|
// CHECK26-NEXT: [[DOTOMP_UB23:%.*]] = alloca i64, align 8
|
|
// CHECK26-NEXT: [[DOTOMP_IV24:%.*]] = alloca i64, align 8
|
|
// CHECK26-NEXT: [[DOTLINEAR_START25:%.*]] = alloca i32, align 4
|
|
// CHECK26-NEXT: [[DOTLINEAR_START26:%.*]] = alloca i32, align 4
|
|
// CHECK26-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8
|
|
// CHECK26-NEXT: [[IT:%.*]] = alloca i64, align 8
|
|
// CHECK26-NEXT: [[LIN28:%.*]] = alloca i32, align 4
|
|
// CHECK26-NEXT: [[A29:%.*]] = alloca i32, align 4
|
|
// CHECK26-NEXT: [[_TMP58:%.*]] = alloca i16, align 2
|
|
// CHECK26-NEXT: [[DOTOMP_LB59:%.*]] = alloca i32, align 4
|
|
// CHECK26-NEXT: [[DOTOMP_UB60:%.*]] = alloca i32, align 4
|
|
// CHECK26-NEXT: [[DOTOMP_IV61:%.*]] = alloca i32, align 4
|
|
// CHECK26-NEXT: [[IT62:%.*]] = alloca i16, align 2
|
|
// CHECK26-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
|
// CHECK26-NEXT: [[_TMP77:%.*]] = alloca i8, align 1
|
|
// CHECK26-NEXT: [[DOTOMP_LB78:%.*]] = alloca i32, align 4
|
|
// CHECK26-NEXT: [[DOTOMP_UB79:%.*]] = alloca i32, align 4
|
|
// CHECK26-NEXT: [[DOTOMP_IV80:%.*]] = alloca i32, align 4
|
|
// CHECK26-NEXT: [[IT81:%.*]] = alloca i8, align 1
|
|
// CHECK26-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK26-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK26-NEXT: store i16 0, i16* [[AA]], align 2
|
|
// CHECK26-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK26-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
|
|
// CHECK26-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave()
|
|
// CHECK26-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8
|
|
// CHECK26-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4
|
|
// CHECK26-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8
|
|
// CHECK26-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK26-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64
|
|
// CHECK26-NEXT: [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]]
|
|
// CHECK26-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8
|
|
// CHECK26-NEXT: store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8
|
|
// CHECK26-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK26-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK26-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK26-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK26-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK26: omp.inner.for.cond:
|
|
// CHECK26-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
|
|
// CHECK26-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !2
|
|
// CHECK26-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
|
|
// CHECK26-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK26: omp.inner.for.body:
|
|
// CHECK26-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
|
|
// CHECK26-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 5
|
|
// CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]]
|
|
// CHECK26-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !2
|
|
// CHECK26-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK26: omp.body.continue:
|
|
// CHECK26-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK26: omp.inner.for.inc:
|
|
// CHECK26-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
|
|
// CHECK26-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1
|
|
// CHECK26-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
|
|
// CHECK26-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]
|
|
// CHECK26: omp.inner.for.end:
|
|
// CHECK26-NEXT: store i32 33, i32* [[I]], align 4
|
|
// CHECK26-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv()
|
|
// CHECK26-NEXT: store i64 [[CALL]], i64* [[K]], align 8
|
|
// CHECK26-NEXT: store i32 0, i32* [[DOTOMP_LB4]], align 4
|
|
// CHECK26-NEXT: store i32 8, i32* [[DOTOMP_UB5]], align 4
|
|
// CHECK26-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_LB4]], align 4
|
|
// CHECK26-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV6]], align 4
|
|
// CHECK26-NEXT: [[TMP12:%.*]] = load i64, i64* [[K]], align 8
|
|
// CHECK26-NEXT: store i64 [[TMP12]], i64* [[DOTLINEAR_START]], align 8
|
|
// CHECK26-NEXT: br label [[OMP_INNER_FOR_COND9:%.*]]
|
|
// CHECK26: omp.inner.for.cond9:
|
|
// CHECK26-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !6
|
|
// CHECK26-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB5]], align 4, !llvm.access.group !6
|
|
// CHECK26-NEXT: [[CMP10:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
|
|
// CHECK26-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY11:%.*]], label [[OMP_INNER_FOR_END19:%.*]]
|
|
// CHECK26: omp.inner.for.body11:
|
|
// CHECK26-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !6
|
|
// CHECK26-NEXT: [[MUL12:%.*]] = mul nsw i32 [[TMP15]], 1
|
|
// CHECK26-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL12]]
|
|
// CHECK26-NEXT: store i32 [[SUB]], i32* [[I7]], align 4, !llvm.access.group !6
|
|
// CHECK26-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8, !llvm.access.group !6
|
|
// CHECK26-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !6
|
|
// CHECK26-NEXT: [[MUL13:%.*]] = mul nsw i32 [[TMP17]], 3
|
|
// CHECK26-NEXT: [[CONV:%.*]] = sext i32 [[MUL13]] to i64
|
|
// CHECK26-NEXT: [[ADD14:%.*]] = add nsw i64 [[TMP16]], [[CONV]]
|
|
// CHECK26-NEXT: store i64 [[ADD14]], i64* [[K8]], align 8, !llvm.access.group !6
|
|
// CHECK26-NEXT: [[TMP18:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !6
|
|
// CHECK26-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP18]], 1
|
|
// CHECK26-NEXT: store i32 [[ADD15]], i32* [[A]], align 4, !llvm.access.group !6
|
|
// CHECK26-NEXT: br label [[OMP_BODY_CONTINUE16:%.*]]
|
|
// CHECK26: omp.body.continue16:
|
|
// CHECK26-NEXT: br label [[OMP_INNER_FOR_INC17:%.*]]
|
|
// CHECK26: omp.inner.for.inc17:
|
|
// CHECK26-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !6
|
|
// CHECK26-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP19]], 1
|
|
// CHECK26-NEXT: store i32 [[ADD18]], i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !6
|
|
// CHECK26-NEXT: br label [[OMP_INNER_FOR_COND9]], !llvm.loop [[LOOP7:![0-9]+]]
|
|
// CHECK26: omp.inner.for.end19:
|
|
// CHECK26-NEXT: store i32 1, i32* [[I7]], align 4
|
|
// CHECK26-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8
|
|
// CHECK26-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP20]], 27
|
|
// CHECK26-NEXT: store i64 [[ADD20]], i64* [[K]], align 8
|
|
// CHECK26-NEXT: store i32 12, i32* [[LIN]], align 4
|
|
// CHECK26-NEXT: store i64 0, i64* [[DOTOMP_LB22]], align 8
|
|
// CHECK26-NEXT: store i64 3, i64* [[DOTOMP_UB23]], align 8
|
|
// CHECK26-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_LB22]], align 8
|
|
// CHECK26-NEXT: store i64 [[TMP21]], i64* [[DOTOMP_IV24]], align 8
|
|
// CHECK26-NEXT: [[TMP22:%.*]] = load i32, i32* [[LIN]], align 4
|
|
// CHECK26-NEXT: store i32 [[TMP22]], i32* [[DOTLINEAR_START25]], align 4
|
|
// CHECK26-NEXT: [[TMP23:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK26-NEXT: store i32 [[TMP23]], i32* [[DOTLINEAR_START26]], align 4
|
|
// CHECK26-NEXT: [[CALL27:%.*]] = call i64 @_Z7get_valv()
|
|
// CHECK26-NEXT: store i64 [[CALL27]], i64* [[DOTLINEAR_STEP]], align 8
|
|
// CHECK26-NEXT: br label [[OMP_INNER_FOR_COND30:%.*]]
|
|
// CHECK26: omp.inner.for.cond30:
|
|
// CHECK26-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !9
|
|
// CHECK26-NEXT: [[TMP25:%.*]] = load i64, i64* [[DOTOMP_UB23]], align 8, !llvm.access.group !9
|
|
// CHECK26-NEXT: [[CMP31:%.*]] = icmp ule i64 [[TMP24]], [[TMP25]]
|
|
// CHECK26-NEXT: br i1 [[CMP31]], label [[OMP_INNER_FOR_BODY32:%.*]], label [[OMP_INNER_FOR_END49:%.*]]
|
|
// CHECK26: omp.inner.for.body32:
|
|
// CHECK26-NEXT: [[TMP26:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !9
|
|
// CHECK26-NEXT: [[MUL33:%.*]] = mul i64 [[TMP26]], 400
|
|
// CHECK26-NEXT: [[SUB34:%.*]] = sub i64 2000, [[MUL33]]
|
|
// CHECK26-NEXT: store i64 [[SUB34]], i64* [[IT]], align 8, !llvm.access.group !9
|
|
// CHECK26-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTLINEAR_START25]], align 4, !llvm.access.group !9
|
|
// CHECK26-NEXT: [[CONV35:%.*]] = sext i32 [[TMP27]] to i64
|
|
// CHECK26-NEXT: [[TMP28:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !9
|
|
// CHECK26-NEXT: [[TMP29:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !9
|
|
// CHECK26-NEXT: [[MUL36:%.*]] = mul i64 [[TMP28]], [[TMP29]]
|
|
// CHECK26-NEXT: [[ADD37:%.*]] = add i64 [[CONV35]], [[MUL36]]
|
|
// CHECK26-NEXT: [[CONV38:%.*]] = trunc i64 [[ADD37]] to i32
|
|
// CHECK26-NEXT: store i32 [[CONV38]], i32* [[LIN28]], align 4, !llvm.access.group !9
|
|
// CHECK26-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTLINEAR_START26]], align 4, !llvm.access.group !9
|
|
// CHECK26-NEXT: [[CONV39:%.*]] = sext i32 [[TMP30]] to i64
|
|
// CHECK26-NEXT: [[TMP31:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !9
|
|
// CHECK26-NEXT: [[TMP32:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !9
|
|
// CHECK26-NEXT: [[MUL40:%.*]] = mul i64 [[TMP31]], [[TMP32]]
|
|
// CHECK26-NEXT: [[ADD41:%.*]] = add i64 [[CONV39]], [[MUL40]]
|
|
// CHECK26-NEXT: [[CONV42:%.*]] = trunc i64 [[ADD41]] to i32
|
|
// CHECK26-NEXT: store i32 [[CONV42]], i32* [[A29]], align 4, !llvm.access.group !9
|
|
// CHECK26-NEXT: [[TMP33:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !9
|
|
// CHECK26-NEXT: [[CONV43:%.*]] = sext i16 [[TMP33]] to i32
|
|
// CHECK26-NEXT: [[ADD44:%.*]] = add nsw i32 [[CONV43]], 1
|
|
// CHECK26-NEXT: [[CONV45:%.*]] = trunc i32 [[ADD44]] to i16
|
|
// CHECK26-NEXT: store i16 [[CONV45]], i16* [[AA]], align 2, !llvm.access.group !9
|
|
// CHECK26-NEXT: br label [[OMP_BODY_CONTINUE46:%.*]]
|
|
// CHECK26: omp.body.continue46:
|
|
// CHECK26-NEXT: br label [[OMP_INNER_FOR_INC47:%.*]]
|
|
// CHECK26: omp.inner.for.inc47:
|
|
// CHECK26-NEXT: [[TMP34:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !9
|
|
// CHECK26-NEXT: [[ADD48:%.*]] = add i64 [[TMP34]], 1
|
|
// CHECK26-NEXT: store i64 [[ADD48]], i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !9
|
|
// CHECK26-NEXT: br label [[OMP_INNER_FOR_COND30]], !llvm.loop [[LOOP10:![0-9]+]]
|
|
// CHECK26: omp.inner.for.end49:
|
|
// CHECK26-NEXT: store i64 400, i64* [[IT]], align 8
|
|
// CHECK26-NEXT: [[TMP35:%.*]] = load i32, i32* [[DOTLINEAR_START25]], align 4
|
|
// CHECK26-NEXT: [[CONV50:%.*]] = sext i32 [[TMP35]] to i64
|
|
// CHECK26-NEXT: [[TMP36:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
|
|
// CHECK26-NEXT: [[MUL51:%.*]] = mul i64 4, [[TMP36]]
|
|
// CHECK26-NEXT: [[ADD52:%.*]] = add i64 [[CONV50]], [[MUL51]]
|
|
// CHECK26-NEXT: [[CONV53:%.*]] = trunc i64 [[ADD52]] to i32
|
|
// CHECK26-NEXT: store i32 [[CONV53]], i32* [[LIN]], align 4
|
|
// CHECK26-NEXT: [[TMP37:%.*]] = load i32, i32* [[DOTLINEAR_START26]], align 4
|
|
// CHECK26-NEXT: [[CONV54:%.*]] = sext i32 [[TMP37]] to i64
|
|
// CHECK26-NEXT: [[TMP38:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
|
|
// CHECK26-NEXT: [[MUL55:%.*]] = mul i64 4, [[TMP38]]
|
|
// CHECK26-NEXT: [[ADD56:%.*]] = add i64 [[CONV54]], [[MUL55]]
|
|
// CHECK26-NEXT: [[CONV57:%.*]] = trunc i64 [[ADD56]] to i32
|
|
// CHECK26-NEXT: store i32 [[CONV57]], i32* [[A]], align 4
|
|
// CHECK26-NEXT: store i32 0, i32* [[DOTOMP_LB59]], align 4
|
|
// CHECK26-NEXT: store i32 3, i32* [[DOTOMP_UB60]], align 4
|
|
// CHECK26-NEXT: [[TMP39:%.*]] = load i32, i32* [[DOTOMP_LB59]], align 4
|
|
// CHECK26-NEXT: store i32 [[TMP39]], i32* [[DOTOMP_IV61]], align 4
|
|
// CHECK26-NEXT: br label [[OMP_INNER_FOR_COND63:%.*]]
|
|
// CHECK26: omp.inner.for.cond63:
|
|
// CHECK26-NEXT: [[TMP40:%.*]] = load i32, i32* [[DOTOMP_IV61]], align 4, !llvm.access.group !12
|
|
// CHECK26-NEXT: [[TMP41:%.*]] = load i32, i32* [[DOTOMP_UB60]], align 4, !llvm.access.group !12
|
|
// CHECK26-NEXT: [[CMP64:%.*]] = icmp sle i32 [[TMP40]], [[TMP41]]
|
|
// CHECK26-NEXT: br i1 [[CMP64]], label [[OMP_INNER_FOR_BODY65:%.*]], label [[OMP_INNER_FOR_END76:%.*]]
|
|
// CHECK26: omp.inner.for.body65:
|
|
// CHECK26-NEXT: [[TMP42:%.*]] = load i32, i32* [[DOTOMP_IV61]], align 4, !llvm.access.group !12
|
|
// CHECK26-NEXT: [[MUL66:%.*]] = mul nsw i32 [[TMP42]], 4
|
|
// CHECK26-NEXT: [[ADD67:%.*]] = add nsw i32 6, [[MUL66]]
|
|
// CHECK26-NEXT: [[CONV68:%.*]] = trunc i32 [[ADD67]] to i16
|
|
// CHECK26-NEXT: store i16 [[CONV68]], i16* [[IT62]], align 2, !llvm.access.group !12
|
|
// CHECK26-NEXT: [[TMP43:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !12
|
|
// CHECK26-NEXT: [[ADD69:%.*]] = add nsw i32 [[TMP43]], 1
|
|
// CHECK26-NEXT: store i32 [[ADD69]], i32* [[A]], align 4, !llvm.access.group !12
|
|
// CHECK26-NEXT: [[TMP44:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !12
|
|
// CHECK26-NEXT: [[CONV70:%.*]] = sext i16 [[TMP44]] to i32
|
|
// CHECK26-NEXT: [[ADD71:%.*]] = add nsw i32 [[CONV70]], 1
|
|
// CHECK26-NEXT: [[CONV72:%.*]] = trunc i32 [[ADD71]] to i16
|
|
// CHECK26-NEXT: store i16 [[CONV72]], i16* [[AA]], align 2, !llvm.access.group !12
|
|
// CHECK26-NEXT: br label [[OMP_BODY_CONTINUE73:%.*]]
|
|
// CHECK26: omp.body.continue73:
|
|
// CHECK26-NEXT: br label [[OMP_INNER_FOR_INC74:%.*]]
|
|
// CHECK26: omp.inner.for.inc74:
|
|
// CHECK26-NEXT: [[TMP45:%.*]] = load i32, i32* [[DOTOMP_IV61]], align 4, !llvm.access.group !12
|
|
// CHECK26-NEXT: [[ADD75:%.*]] = add nsw i32 [[TMP45]], 1
|
|
// CHECK26-NEXT: store i32 [[ADD75]], i32* [[DOTOMP_IV61]], align 4, !llvm.access.group !12
|
|
// CHECK26-NEXT: br label [[OMP_INNER_FOR_COND63]], !llvm.loop [[LOOP13:![0-9]+]]
|
|
// CHECK26: omp.inner.for.end76:
|
|
// CHECK26-NEXT: store i16 22, i16* [[IT62]], align 2
|
|
// CHECK26-NEXT: [[TMP46:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK26-NEXT: store i32 [[TMP46]], i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK26-NEXT: store i32 0, i32* [[DOTOMP_LB78]], align 4
|
|
// CHECK26-NEXT: store i32 25, i32* [[DOTOMP_UB79]], align 4
|
|
// CHECK26-NEXT: [[TMP47:%.*]] = load i32, i32* [[DOTOMP_LB78]], align 4
|
|
// CHECK26-NEXT: store i32 [[TMP47]], i32* [[DOTOMP_IV80]], align 4
|
|
// CHECK26-NEXT: br label [[OMP_INNER_FOR_COND82:%.*]]
|
|
// CHECK26: omp.inner.for.cond82:
|
|
// CHECK26-NEXT: [[TMP48:%.*]] = load i32, i32* [[DOTOMP_IV80]], align 4, !llvm.access.group !15
|
|
// CHECK26-NEXT: [[TMP49:%.*]] = load i32, i32* [[DOTOMP_UB79]], align 4, !llvm.access.group !15
|
|
// CHECK26-NEXT: [[CMP83:%.*]] = icmp sle i32 [[TMP48]], [[TMP49]]
|
|
// CHECK26-NEXT: br i1 [[CMP83]], label [[OMP_INNER_FOR_BODY84:%.*]], label [[OMP_INNER_FOR_END109:%.*]]
|
|
// CHECK26: omp.inner.for.body84:
|
|
// CHECK26-NEXT: [[TMP50:%.*]] = load i32, i32* [[DOTOMP_IV80]], align 4, !llvm.access.group !15
|
|
// CHECK26-NEXT: [[MUL85:%.*]] = mul nsw i32 [[TMP50]], 1
|
|
// CHECK26-NEXT: [[SUB86:%.*]] = sub nsw i32 122, [[MUL85]]
|
|
// CHECK26-NEXT: [[CONV87:%.*]] = trunc i32 [[SUB86]] to i8
|
|
// CHECK26-NEXT: store i8 [[CONV87]], i8* [[IT81]], align 1, !llvm.access.group !15
|
|
// CHECK26-NEXT: [[TMP51:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !15
|
|
// CHECK26-NEXT: [[ADD88:%.*]] = add nsw i32 [[TMP51]], 1
|
|
// CHECK26-NEXT: store i32 [[ADD88]], i32* [[A]], align 4, !llvm.access.group !15
|
|
// CHECK26-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 2
|
|
// CHECK26-NEXT: [[TMP52:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !15
|
|
// CHECK26-NEXT: [[CONV89:%.*]] = fpext float [[TMP52]] to double
|
|
// CHECK26-NEXT: [[ADD90:%.*]] = fadd double [[CONV89]], 1.000000e+00
|
|
// CHECK26-NEXT: [[CONV91:%.*]] = fptrunc double [[ADD90]] to float
|
|
// CHECK26-NEXT: store float [[CONV91]], float* [[ARRAYIDX]], align 4, !llvm.access.group !15
|
|
// CHECK26-NEXT: [[ARRAYIDX92:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 3
|
|
// CHECK26-NEXT: [[TMP53:%.*]] = load float, float* [[ARRAYIDX92]], align 4, !llvm.access.group !15
|
|
// CHECK26-NEXT: [[CONV93:%.*]] = fpext float [[TMP53]] to double
|
|
// CHECK26-NEXT: [[ADD94:%.*]] = fadd double [[CONV93]], 1.000000e+00
|
|
// CHECK26-NEXT: [[CONV95:%.*]] = fptrunc double [[ADD94]] to float
|
|
// CHECK26-NEXT: store float [[CONV95]], float* [[ARRAYIDX92]], align 4, !llvm.access.group !15
|
|
// CHECK26-NEXT: [[ARRAYIDX96:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i64 0, i64 1
|
|
// CHECK26-NEXT: [[ARRAYIDX97:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX96]], i64 0, i64 2
|
|
// CHECK26-NEXT: [[TMP54:%.*]] = load double, double* [[ARRAYIDX97]], align 8, !llvm.access.group !15
|
|
// CHECK26-NEXT: [[ADD98:%.*]] = fadd double [[TMP54]], 1.000000e+00
|
|
// CHECK26-NEXT: store double [[ADD98]], double* [[ARRAYIDX97]], align 8, !llvm.access.group !15
|
|
// CHECK26-NEXT: [[TMP55:%.*]] = mul nsw i64 1, [[TMP4]]
|
|
// CHECK26-NEXT: [[ARRAYIDX99:%.*]] = getelementptr inbounds double, double* [[VLA1]], i64 [[TMP55]]
|
|
// CHECK26-NEXT: [[ARRAYIDX100:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX99]], i64 3
|
|
// CHECK26-NEXT: [[TMP56:%.*]] = load double, double* [[ARRAYIDX100]], align 8, !llvm.access.group !15
|
|
// CHECK26-NEXT: [[ADD101:%.*]] = fadd double [[TMP56]], 1.000000e+00
|
|
// CHECK26-NEXT: store double [[ADD101]], double* [[ARRAYIDX100]], align 8, !llvm.access.group !15
|
|
// CHECK26-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0
|
|
// CHECK26-NEXT: [[TMP57:%.*]] = load i64, i64* [[X]], align 8, !llvm.access.group !15
|
|
// CHECK26-NEXT: [[ADD102:%.*]] = add nsw i64 [[TMP57]], 1
|
|
// CHECK26-NEXT: store i64 [[ADD102]], i64* [[X]], align 8, !llvm.access.group !15
|
|
// CHECK26-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1
|
|
// CHECK26-NEXT: [[TMP58:%.*]] = load i8, i8* [[Y]], align 8, !llvm.access.group !15
|
|
// CHECK26-NEXT: [[CONV103:%.*]] = sext i8 [[TMP58]] to i32
|
|
// CHECK26-NEXT: [[ADD104:%.*]] = add nsw i32 [[CONV103]], 1
|
|
// CHECK26-NEXT: [[CONV105:%.*]] = trunc i32 [[ADD104]] to i8
|
|
// CHECK26-NEXT: store i8 [[CONV105]], i8* [[Y]], align 8, !llvm.access.group !15
|
|
// CHECK26-NEXT: br label [[OMP_BODY_CONTINUE106:%.*]]
|
|
// CHECK26: omp.body.continue106:
|
|
// CHECK26-NEXT: br label [[OMP_INNER_FOR_INC107:%.*]]
|
|
// CHECK26: omp.inner.for.inc107:
|
|
// CHECK26-NEXT: [[TMP59:%.*]] = load i32, i32* [[DOTOMP_IV80]], align 4, !llvm.access.group !15
|
|
// CHECK26-NEXT: [[ADD108:%.*]] = add nsw i32 [[TMP59]], 1
|
|
// CHECK26-NEXT: store i32 [[ADD108]], i32* [[DOTOMP_IV80]], align 4, !llvm.access.group !15
|
|
// CHECK26-NEXT: br label [[OMP_INNER_FOR_COND82]], !llvm.loop [[LOOP16:![0-9]+]]
|
|
// CHECK26: omp.inner.for.end109:
|
|
// CHECK26-NEXT: store i8 96, i8* [[IT81]], align 1
|
|
// CHECK26-NEXT: [[TMP60:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK26-NEXT: [[TMP61:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
|
|
// CHECK26-NEXT: call void @llvm.stackrestore(i8* [[TMP61]])
|
|
// CHECK26-NEXT: ret i32 [[TMP60]]
|
|
//
|
|
//
|
|
// CHECK26-LABEL: define {{[^@]+}}@_Z3bari
|
|
// CHECK26-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
|
|
// CHECK26-NEXT: entry:
|
|
// CHECK26-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK26-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK26-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8
|
|
// CHECK26-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK26-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK26-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK26-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]])
|
|
// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
|
|
// CHECK26-NEXT: store i32 [[ADD]], i32* [[A]], align 4
|
|
// CHECK26-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK26-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]])
|
|
// CHECK26-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK26-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
|
|
// CHECK26-NEXT: store i32 [[ADD2]], i32* [[A]], align 4
|
|
// CHECK26-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK26-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]])
|
|
// CHECK26-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK26-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
|
|
// CHECK26-NEXT: store i32 [[ADD4]], i32* [[A]], align 4
|
|
// CHECK26-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK26-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]])
|
|
// CHECK26-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK26-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
|
|
// CHECK26-NEXT: store i32 [[ADD6]], i32* [[A]], align 4
|
|
// CHECK26-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK26-NEXT: ret i32 [[TMP8]]
|
|
//
|
|
//
|
|
// CHECK26-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
|
|
// CHECK26-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 {
|
|
// CHECK26-NEXT: entry:
|
|
// CHECK26-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
|
|
// CHECK26-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK26-NEXT: [[B:%.*]] = alloca i32, align 4
|
|
// CHECK26-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8
|
|
// CHECK26-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8
|
|
// CHECK26-NEXT: [[TMP:%.*]] = alloca i64, align 8
|
|
// CHECK26-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
|
|
// CHECK26-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
|
|
// CHECK26-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
|
|
// CHECK26-NEXT: [[IT:%.*]] = alloca i64, align 8
|
|
// CHECK26-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK26-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK26-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK26-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
|
|
// CHECK26-NEXT: store i32 [[ADD]], i32* [[B]], align 4
|
|
// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK26-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
|
|
// CHECK26-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave()
|
|
// CHECK26-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8
|
|
// CHECK26-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]]
|
|
// CHECK26-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2
|
|
// CHECK26-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8
|
|
// CHECK26-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK26-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK26-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK26-NEXT: store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK26-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK26: omp.inner.for.cond:
|
|
// CHECK26-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18
|
|
// CHECK26-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !18
|
|
// CHECK26-NEXT: [[CMP:%.*]] = icmp ule i64 [[TMP6]], [[TMP7]]
|
|
// CHECK26-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK26: omp.inner.for.body:
|
|
// CHECK26-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18
|
|
// CHECK26-NEXT: [[MUL:%.*]] = mul i64 [[TMP8]], 400
|
|
// CHECK26-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]
|
|
// CHECK26-NEXT: store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !18
|
|
// CHECK26-NEXT: [[TMP9:%.*]] = load i32, i32* [[B]], align 4, !llvm.access.group !18
|
|
// CHECK26-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP9]] to double
|
|
// CHECK26-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00
|
|
// CHECK26-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
|
|
// CHECK26-NEXT: store double [[ADD2]], double* [[A]], align 8, !llvm.access.group !18
|
|
// CHECK26-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
|
|
// CHECK26-NEXT: [[TMP10:%.*]] = load double, double* [[A3]], align 8, !llvm.access.group !18
|
|
// CHECK26-NEXT: [[INC:%.*]] = fadd double [[TMP10]], 1.000000e+00
|
|
// CHECK26-NEXT: store double [[INC]], double* [[A3]], align 8, !llvm.access.group !18
|
|
// CHECK26-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16
|
|
// CHECK26-NEXT: [[TMP11:%.*]] = mul nsw i64 1, [[TMP2]]
|
|
// CHECK26-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP11]]
|
|
// CHECK26-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
|
|
// CHECK26-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2, !llvm.access.group !18
|
|
// CHECK26-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK26: omp.body.continue:
|
|
// CHECK26-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK26: omp.inner.for.inc:
|
|
// CHECK26-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18
|
|
// CHECK26-NEXT: [[ADD6:%.*]] = add i64 [[TMP12]], 1
|
|
// CHECK26-NEXT: store i64 [[ADD6]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18
|
|
// CHECK26-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]
|
|
// CHECK26: omp.inner.for.end:
|
|
// CHECK26-NEXT: store i64 400, i64* [[IT]], align 8
|
|
// CHECK26-NEXT: [[TMP13:%.*]] = mul nsw i64 1, [[TMP2]]
|
|
// CHECK26-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP13]]
|
|
// CHECK26-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX7]], i64 1
|
|
// CHECK26-NEXT: [[TMP14:%.*]] = load i16, i16* [[ARRAYIDX8]], align 2
|
|
// CHECK26-NEXT: [[CONV9:%.*]] = sext i16 [[TMP14]] to i32
|
|
// CHECK26-NEXT: [[TMP15:%.*]] = load i32, i32* [[B]], align 4
|
|
// CHECK26-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[TMP15]]
|
|
// CHECK26-NEXT: [[TMP16:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
|
|
// CHECK26-NEXT: call void @llvm.stackrestore(i8* [[TMP16]])
|
|
// CHECK26-NEXT: ret i32 [[ADD10]]
|
|
//
|
|
//
|
|
// CHECK26-LABEL: define {{[^@]+}}@_ZL7fstatici
|
|
// CHECK26-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
|
|
// CHECK26-NEXT: entry:
|
|
// CHECK26-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK26-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK26-NEXT: [[AA:%.*]] = alloca i16, align 2
|
|
// CHECK26-NEXT: [[AAA:%.*]] = alloca i8, align 1
|
|
// CHECK26-NEXT: [[B:%.*]] = alloca [10 x i32], align 4
|
|
// CHECK26-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK26-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK26-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK26-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK26-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK26-NEXT: store i16 0, i16* [[AA]], align 2
|
|
// CHECK26-NEXT: store i8 0, i8* [[AAA]], align 1
|
|
// CHECK26-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK26-NEXT: store i32 429496720, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK26-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK26-NEXT: ret i32 [[TMP0]]
|
|
//
|
|
//
|
|
// CHECK26-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
|
|
// CHECK26-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat {
|
|
// CHECK26-NEXT: entry:
|
|
// CHECK26-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK26-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK26-NEXT: [[AA:%.*]] = alloca i16, align 2
|
|
// CHECK26-NEXT: [[B:%.*]] = alloca [10 x i32], align 4
|
|
// CHECK26-NEXT: [[TMP:%.*]] = alloca i64, align 8
|
|
// CHECK26-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
|
|
// CHECK26-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
|
|
// CHECK26-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
|
|
// CHECK26-NEXT: [[I:%.*]] = alloca i64, align 8
|
|
// CHECK26-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK26-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK26-NEXT: store i16 0, i16* [[AA]], align 2
|
|
// CHECK26-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK26-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK26-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK26-NEXT: store i64 [[TMP0]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK26-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK26: omp.inner.for.cond:
|
|
// CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !21
|
|
// CHECK26-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !21
|
|
// CHECK26-NEXT: [[CMP:%.*]] = icmp sle i64 [[TMP1]], [[TMP2]]
|
|
// CHECK26-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK26: omp.inner.for.body:
|
|
// CHECK26-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !21
|
|
// CHECK26-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP3]], 3
|
|
// CHECK26-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
|
|
// CHECK26-NEXT: store i64 [[ADD]], i64* [[I]], align 8, !llvm.access.group !21
|
|
// CHECK26-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !21
|
|
// CHECK26-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1
|
|
// CHECK26-NEXT: store i32 [[ADD1]], i32* [[A]], align 4, !llvm.access.group !21
|
|
// CHECK26-NEXT: [[TMP5:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !21
|
|
// CHECK26-NEXT: [[CONV:%.*]] = sext i16 [[TMP5]] to i32
|
|
// CHECK26-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 1
|
|
// CHECK26-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
|
|
// CHECK26-NEXT: store i16 [[CONV3]], i16* [[AA]], align 2, !llvm.access.group !21
|
|
// CHECK26-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2
|
|
// CHECK26-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !21
|
|
// CHECK26-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP6]], 1
|
|
// CHECK26-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !21
|
|
// CHECK26-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK26: omp.body.continue:
|
|
// CHECK26-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK26: omp.inner.for.inc:
|
|
// CHECK26-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !21
|
|
// CHECK26-NEXT: [[ADD5:%.*]] = add nsw i64 [[TMP7]], 1
|
|
// CHECK26-NEXT: store i64 [[ADD5]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !21
|
|
// CHECK26-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]]
|
|
// CHECK26: omp.inner.for.end:
|
|
// CHECK26-NEXT: store i64 11, i64* [[I]], align 8
|
|
// CHECK26-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK26-NEXT: ret i32 [[TMP8]]
|
|
//
|
|
//
|
|
// CHECK27-LABEL: define {{[^@]+}}@_Z7get_valv
|
|
// CHECK27-SAME: () #[[ATTR0:[0-9]+]] {
|
|
// CHECK27-NEXT: entry:
|
|
// CHECK27-NEXT: ret i64 0
|
|
//
|
|
//
|
|
// CHECK27-LABEL: define {{[^@]+}}@_Z3fooi
|
|
// CHECK27-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
|
|
// CHECK27-NEXT: entry:
|
|
// CHECK27-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK27-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK27-NEXT: [[AA:%.*]] = alloca i16, align 2
|
|
// CHECK27-NEXT: [[B:%.*]] = alloca [10 x float], align 4
|
|
// CHECK27-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4
|
|
// CHECK27-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4
|
|
// CHECK27-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8
|
|
// CHECK27-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4
|
|
// CHECK27-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4
|
|
// CHECK27-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK27-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK27-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK27-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK27-NEXT: [[I:%.*]] = alloca i32, align 4
|
|
// CHECK27-NEXT: [[K:%.*]] = alloca i64, align 8
|
|
// CHECK27-NEXT: [[_TMP3:%.*]] = alloca i32, align 4
|
|
// CHECK27-NEXT: [[DOTOMP_LB4:%.*]] = alloca i32, align 4
|
|
// CHECK27-NEXT: [[DOTOMP_UB5:%.*]] = alloca i32, align 4
|
|
// CHECK27-NEXT: [[DOTOMP_IV6:%.*]] = alloca i32, align 4
|
|
// CHECK27-NEXT: [[DOTLINEAR_START:%.*]] = alloca i64, align 8
|
|
// CHECK27-NEXT: [[I7:%.*]] = alloca i32, align 4
|
|
// CHECK27-NEXT: [[K8:%.*]] = alloca i64, align 8
|
|
// CHECK27-NEXT: [[LIN:%.*]] = alloca i32, align 4
|
|
// CHECK27-NEXT: [[_TMP21:%.*]] = alloca i64, align 4
|
|
// CHECK27-NEXT: [[DOTOMP_LB22:%.*]] = alloca i64, align 8
|
|
// CHECK27-NEXT: [[DOTOMP_UB23:%.*]] = alloca i64, align 8
|
|
// CHECK27-NEXT: [[DOTOMP_IV24:%.*]] = alloca i64, align 8
|
|
// CHECK27-NEXT: [[DOTLINEAR_START25:%.*]] = alloca i32, align 4
|
|
// CHECK27-NEXT: [[DOTLINEAR_START26:%.*]] = alloca i32, align 4
|
|
// CHECK27-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8
|
|
// CHECK27-NEXT: [[IT:%.*]] = alloca i64, align 8
|
|
// CHECK27-NEXT: [[LIN28:%.*]] = alloca i32, align 4
|
|
// CHECK27-NEXT: [[A29:%.*]] = alloca i32, align 4
|
|
// CHECK27-NEXT: [[_TMP58:%.*]] = alloca i16, align 2
|
|
// CHECK27-NEXT: [[DOTOMP_LB59:%.*]] = alloca i32, align 4
|
|
// CHECK27-NEXT: [[DOTOMP_UB60:%.*]] = alloca i32, align 4
|
|
// CHECK27-NEXT: [[DOTOMP_IV61:%.*]] = alloca i32, align 4
|
|
// CHECK27-NEXT: [[IT62:%.*]] = alloca i16, align 2
|
|
// CHECK27-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
|
// CHECK27-NEXT: [[_TMP77:%.*]] = alloca i8, align 1
|
|
// CHECK27-NEXT: [[DOTOMP_LB78:%.*]] = alloca i32, align 4
|
|
// CHECK27-NEXT: [[DOTOMP_UB79:%.*]] = alloca i32, align 4
|
|
// CHECK27-NEXT: [[DOTOMP_IV80:%.*]] = alloca i32, align 4
|
|
// CHECK27-NEXT: [[IT81:%.*]] = alloca i8, align 1
|
|
// CHECK27-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK27-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK27-NEXT: store i16 0, i16* [[AA]], align 2
|
|
// CHECK27-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK27-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave()
|
|
// CHECK27-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4
|
|
// CHECK27-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4
|
|
// CHECK27-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4
|
|
// CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK27-NEXT: [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]]
|
|
// CHECK27-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8
|
|
// CHECK27-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4
|
|
// CHECK27-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK27-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK27-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK27: omp.inner.for.cond:
|
|
// CHECK27-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
|
|
// CHECK27-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !3
|
|
// CHECK27-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
|
|
// CHECK27-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK27: omp.inner.for.body:
|
|
// CHECK27-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
|
|
// CHECK27-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5
|
|
// CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]]
|
|
// CHECK27-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !3
|
|
// CHECK27-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK27: omp.body.continue:
|
|
// CHECK27-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK27: omp.inner.for.inc:
|
|
// CHECK27-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
|
|
// CHECK27-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
|
|
// CHECK27-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
|
|
// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]
|
|
// CHECK27: omp.inner.for.end:
|
|
// CHECK27-NEXT: store i32 33, i32* [[I]], align 4
|
|
// CHECK27-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv()
|
|
// CHECK27-NEXT: store i64 [[CALL]], i64* [[K]], align 8
|
|
// CHECK27-NEXT: store i32 0, i32* [[DOTOMP_LB4]], align 4
|
|
// CHECK27-NEXT: store i32 8, i32* [[DOTOMP_UB5]], align 4
|
|
// CHECK27-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_LB4]], align 4
|
|
// CHECK27-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV6]], align 4
|
|
// CHECK27-NEXT: [[TMP10:%.*]] = load i64, i64* [[K]], align 8
|
|
// CHECK27-NEXT: store i64 [[TMP10]], i64* [[DOTLINEAR_START]], align 8
|
|
// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND9:%.*]]
|
|
// CHECK27: omp.inner.for.cond9:
|
|
// CHECK27-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !7
|
|
// CHECK27-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB5]], align 4, !llvm.access.group !7
|
|
// CHECK27-NEXT: [[CMP10:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]]
|
|
// CHECK27-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY11:%.*]], label [[OMP_INNER_FOR_END19:%.*]]
|
|
// CHECK27: omp.inner.for.body11:
|
|
// CHECK27-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !7
|
|
// CHECK27-NEXT: [[MUL12:%.*]] = mul nsw i32 [[TMP13]], 1
|
|
// CHECK27-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL12]]
|
|
// CHECK27-NEXT: store i32 [[SUB]], i32* [[I7]], align 4, !llvm.access.group !7
|
|
// CHECK27-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8, !llvm.access.group !7
|
|
// CHECK27-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !7
|
|
// CHECK27-NEXT: [[MUL13:%.*]] = mul nsw i32 [[TMP15]], 3
|
|
// CHECK27-NEXT: [[CONV:%.*]] = sext i32 [[MUL13]] to i64
|
|
// CHECK27-NEXT: [[ADD14:%.*]] = add nsw i64 [[TMP14]], [[CONV]]
|
|
// CHECK27-NEXT: store i64 [[ADD14]], i64* [[K8]], align 8, !llvm.access.group !7
|
|
// CHECK27-NEXT: [[TMP16:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !7
|
|
// CHECK27-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP16]], 1
|
|
// CHECK27-NEXT: store i32 [[ADD15]], i32* [[A]], align 4, !llvm.access.group !7
|
|
// CHECK27-NEXT: br label [[OMP_BODY_CONTINUE16:%.*]]
|
|
// CHECK27: omp.body.continue16:
|
|
// CHECK27-NEXT: br label [[OMP_INNER_FOR_INC17:%.*]]
|
|
// CHECK27: omp.inner.for.inc17:
|
|
// CHECK27-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !7
|
|
// CHECK27-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP17]], 1
|
|
// CHECK27-NEXT: store i32 [[ADD18]], i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !7
|
|
// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND9]], !llvm.loop [[LOOP8:![0-9]+]]
|
|
// CHECK27: omp.inner.for.end19:
|
|
// CHECK27-NEXT: store i32 1, i32* [[I7]], align 4
|
|
// CHECK27-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8
|
|
// CHECK27-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP18]], 27
|
|
// CHECK27-NEXT: store i64 [[ADD20]], i64* [[K]], align 8
|
|
// CHECK27-NEXT: store i32 12, i32* [[LIN]], align 4
|
|
// CHECK27-NEXT: store i64 0, i64* [[DOTOMP_LB22]], align 8
|
|
// CHECK27-NEXT: store i64 3, i64* [[DOTOMP_UB23]], align 8
|
|
// CHECK27-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_LB22]], align 8
|
|
// CHECK27-NEXT: store i64 [[TMP19]], i64* [[DOTOMP_IV24]], align 8
|
|
// CHECK27-NEXT: [[TMP20:%.*]] = load i32, i32* [[LIN]], align 4
|
|
// CHECK27-NEXT: store i32 [[TMP20]], i32* [[DOTLINEAR_START25]], align 4
|
|
// CHECK27-NEXT: [[TMP21:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK27-NEXT: store i32 [[TMP21]], i32* [[DOTLINEAR_START26]], align 4
|
|
// CHECK27-NEXT: [[CALL27:%.*]] = call i64 @_Z7get_valv()
|
|
// CHECK27-NEXT: store i64 [[CALL27]], i64* [[DOTLINEAR_STEP]], align 8
|
|
// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND30:%.*]]
|
|
// CHECK27: omp.inner.for.cond30:
|
|
// CHECK27-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !10
|
|
// CHECK27-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_UB23]], align 8, !llvm.access.group !10
|
|
// CHECK27-NEXT: [[CMP31:%.*]] = icmp ule i64 [[TMP22]], [[TMP23]]
|
|
// CHECK27-NEXT: br i1 [[CMP31]], label [[OMP_INNER_FOR_BODY32:%.*]], label [[OMP_INNER_FOR_END49:%.*]]
|
|
// CHECK27: omp.inner.for.body32:
|
|
// CHECK27-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !10
|
|
// CHECK27-NEXT: [[MUL33:%.*]] = mul i64 [[TMP24]], 400
|
|
// CHECK27-NEXT: [[SUB34:%.*]] = sub i64 2000, [[MUL33]]
|
|
// CHECK27-NEXT: store i64 [[SUB34]], i64* [[IT]], align 8, !llvm.access.group !10
|
|
// CHECK27-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTLINEAR_START25]], align 4, !llvm.access.group !10
|
|
// CHECK27-NEXT: [[CONV35:%.*]] = sext i32 [[TMP25]] to i64
|
|
// CHECK27-NEXT: [[TMP26:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !10
|
|
// CHECK27-NEXT: [[TMP27:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !10
|
|
// CHECK27-NEXT: [[MUL36:%.*]] = mul i64 [[TMP26]], [[TMP27]]
|
|
// CHECK27-NEXT: [[ADD37:%.*]] = add i64 [[CONV35]], [[MUL36]]
|
|
// CHECK27-NEXT: [[CONV38:%.*]] = trunc i64 [[ADD37]] to i32
|
|
// CHECK27-NEXT: store i32 [[CONV38]], i32* [[LIN28]], align 4, !llvm.access.group !10
|
|
// CHECK27-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTLINEAR_START26]], align 4, !llvm.access.group !10
|
|
// CHECK27-NEXT: [[CONV39:%.*]] = sext i32 [[TMP28]] to i64
|
|
// CHECK27-NEXT: [[TMP29:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !10
|
|
// CHECK27-NEXT: [[TMP30:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !10
|
|
// CHECK27-NEXT: [[MUL40:%.*]] = mul i64 [[TMP29]], [[TMP30]]
|
|
// CHECK27-NEXT: [[ADD41:%.*]] = add i64 [[CONV39]], [[MUL40]]
|
|
// CHECK27-NEXT: [[CONV42:%.*]] = trunc i64 [[ADD41]] to i32
|
|
// CHECK27-NEXT: store i32 [[CONV42]], i32* [[A29]], align 4, !llvm.access.group !10
|
|
// CHECK27-NEXT: [[TMP31:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !10
|
|
// CHECK27-NEXT: [[CONV43:%.*]] = sext i16 [[TMP31]] to i32
|
|
// CHECK27-NEXT: [[ADD44:%.*]] = add nsw i32 [[CONV43]], 1
|
|
// CHECK27-NEXT: [[CONV45:%.*]] = trunc i32 [[ADD44]] to i16
|
|
// CHECK27-NEXT: store i16 [[CONV45]], i16* [[AA]], align 2, !llvm.access.group !10
|
|
// CHECK27-NEXT: br label [[OMP_BODY_CONTINUE46:%.*]]
|
|
// CHECK27: omp.body.continue46:
|
|
// CHECK27-NEXT: br label [[OMP_INNER_FOR_INC47:%.*]]
|
|
// CHECK27: omp.inner.for.inc47:
|
|
// CHECK27-NEXT: [[TMP32:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !10
|
|
// CHECK27-NEXT: [[ADD48:%.*]] = add i64 [[TMP32]], 1
|
|
// CHECK27-NEXT: store i64 [[ADD48]], i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !10
|
|
// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND30]], !llvm.loop [[LOOP11:![0-9]+]]
|
|
// CHECK27: omp.inner.for.end49:
|
|
// CHECK27-NEXT: store i64 400, i64* [[IT]], align 8
|
|
// CHECK27-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTLINEAR_START25]], align 4
|
|
// CHECK27-NEXT: [[CONV50:%.*]] = sext i32 [[TMP33]] to i64
|
|
// CHECK27-NEXT: [[TMP34:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
|
|
// CHECK27-NEXT: [[MUL51:%.*]] = mul i64 4, [[TMP34]]
|
|
// CHECK27-NEXT: [[ADD52:%.*]] = add i64 [[CONV50]], [[MUL51]]
|
|
// CHECK27-NEXT: [[CONV53:%.*]] = trunc i64 [[ADD52]] to i32
|
|
// CHECK27-NEXT: store i32 [[CONV53]], i32* [[LIN]], align 4
|
|
// CHECK27-NEXT: [[TMP35:%.*]] = load i32, i32* [[DOTLINEAR_START26]], align 4
|
|
// CHECK27-NEXT: [[CONV54:%.*]] = sext i32 [[TMP35]] to i64
|
|
// CHECK27-NEXT: [[TMP36:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
|
|
// CHECK27-NEXT: [[MUL55:%.*]] = mul i64 4, [[TMP36]]
|
|
// CHECK27-NEXT: [[ADD56:%.*]] = add i64 [[CONV54]], [[MUL55]]
|
|
// CHECK27-NEXT: [[CONV57:%.*]] = trunc i64 [[ADD56]] to i32
|
|
// CHECK27-NEXT: store i32 [[CONV57]], i32* [[A]], align 4
|
|
// CHECK27-NEXT: store i32 0, i32* [[DOTOMP_LB59]], align 4
|
|
// CHECK27-NEXT: store i32 3, i32* [[DOTOMP_UB60]], align 4
|
|
// CHECK27-NEXT: [[TMP37:%.*]] = load i32, i32* [[DOTOMP_LB59]], align 4
|
|
// CHECK27-NEXT: store i32 [[TMP37]], i32* [[DOTOMP_IV61]], align 4
|
|
// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND63:%.*]]
|
|
// CHECK27: omp.inner.for.cond63:
|
|
// CHECK27-NEXT: [[TMP38:%.*]] = load i32, i32* [[DOTOMP_IV61]], align 4, !llvm.access.group !13
|
|
// CHECK27-NEXT: [[TMP39:%.*]] = load i32, i32* [[DOTOMP_UB60]], align 4, !llvm.access.group !13
|
|
// CHECK27-NEXT: [[CMP64:%.*]] = icmp sle i32 [[TMP38]], [[TMP39]]
|
|
// CHECK27-NEXT: br i1 [[CMP64]], label [[OMP_INNER_FOR_BODY65:%.*]], label [[OMP_INNER_FOR_END76:%.*]]
|
|
// CHECK27: omp.inner.for.body65:
|
|
// CHECK27-NEXT: [[TMP40:%.*]] = load i32, i32* [[DOTOMP_IV61]], align 4, !llvm.access.group !13
|
|
// CHECK27-NEXT: [[MUL66:%.*]] = mul nsw i32 [[TMP40]], 4
|
|
// CHECK27-NEXT: [[ADD67:%.*]] = add nsw i32 6, [[MUL66]]
|
|
// CHECK27-NEXT: [[CONV68:%.*]] = trunc i32 [[ADD67]] to i16
|
|
// CHECK27-NEXT: store i16 [[CONV68]], i16* [[IT62]], align 2, !llvm.access.group !13
|
|
// CHECK27-NEXT: [[TMP41:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !13
|
|
// CHECK27-NEXT: [[ADD69:%.*]] = add nsw i32 [[TMP41]], 1
|
|
// CHECK27-NEXT: store i32 [[ADD69]], i32* [[A]], align 4, !llvm.access.group !13
|
|
// CHECK27-NEXT: [[TMP42:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !13
|
|
// CHECK27-NEXT: [[CONV70:%.*]] = sext i16 [[TMP42]] to i32
|
|
// CHECK27-NEXT: [[ADD71:%.*]] = add nsw i32 [[CONV70]], 1
|
|
// CHECK27-NEXT: [[CONV72:%.*]] = trunc i32 [[ADD71]] to i16
|
|
// CHECK27-NEXT: store i16 [[CONV72]], i16* [[AA]], align 2, !llvm.access.group !13
|
|
// CHECK27-NEXT: br label [[OMP_BODY_CONTINUE73:%.*]]
|
|
// CHECK27: omp.body.continue73:
|
|
// CHECK27-NEXT: br label [[OMP_INNER_FOR_INC74:%.*]]
|
|
// CHECK27: omp.inner.for.inc74:
|
|
// CHECK27-NEXT: [[TMP43:%.*]] = load i32, i32* [[DOTOMP_IV61]], align 4, !llvm.access.group !13
|
|
// CHECK27-NEXT: [[ADD75:%.*]] = add nsw i32 [[TMP43]], 1
|
|
// CHECK27-NEXT: store i32 [[ADD75]], i32* [[DOTOMP_IV61]], align 4, !llvm.access.group !13
|
|
// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND63]], !llvm.loop [[LOOP14:![0-9]+]]
|
|
// CHECK27: omp.inner.for.end76:
|
|
// CHECK27-NEXT: store i16 22, i16* [[IT62]], align 2
|
|
// CHECK27-NEXT: [[TMP44:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK27-NEXT: store i32 [[TMP44]], i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK27-NEXT: store i32 0, i32* [[DOTOMP_LB78]], align 4
|
|
// CHECK27-NEXT: store i32 25, i32* [[DOTOMP_UB79]], align 4
|
|
// CHECK27-NEXT: [[TMP45:%.*]] = load i32, i32* [[DOTOMP_LB78]], align 4
|
|
// CHECK27-NEXT: store i32 [[TMP45]], i32* [[DOTOMP_IV80]], align 4
|
|
// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND82:%.*]]
|
|
// CHECK27: omp.inner.for.cond82:
|
|
// CHECK27-NEXT: [[TMP46:%.*]] = load i32, i32* [[DOTOMP_IV80]], align 4, !llvm.access.group !16
|
|
// CHECK27-NEXT: [[TMP47:%.*]] = load i32, i32* [[DOTOMP_UB79]], align 4, !llvm.access.group !16
|
|
// CHECK27-NEXT: [[CMP83:%.*]] = icmp sle i32 [[TMP46]], [[TMP47]]
|
|
// CHECK27-NEXT: br i1 [[CMP83]], label [[OMP_INNER_FOR_BODY84:%.*]], label [[OMP_INNER_FOR_END109:%.*]]
|
|
// CHECK27: omp.inner.for.body84:
|
|
// CHECK27-NEXT: [[TMP48:%.*]] = load i32, i32* [[DOTOMP_IV80]], align 4, !llvm.access.group !16
|
|
// CHECK27-NEXT: [[MUL85:%.*]] = mul nsw i32 [[TMP48]], 1
|
|
// CHECK27-NEXT: [[SUB86:%.*]] = sub nsw i32 122, [[MUL85]]
|
|
// CHECK27-NEXT: [[CONV87:%.*]] = trunc i32 [[SUB86]] to i8
|
|
// CHECK27-NEXT: store i8 [[CONV87]], i8* [[IT81]], align 1, !llvm.access.group !16
|
|
// CHECK27-NEXT: [[TMP49:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !16
|
|
// CHECK27-NEXT: [[ADD88:%.*]] = add nsw i32 [[TMP49]], 1
|
|
// CHECK27-NEXT: store i32 [[ADD88]], i32* [[A]], align 4, !llvm.access.group !16
|
|
// CHECK27-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 2
|
|
// CHECK27-NEXT: [[TMP50:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !16
|
|
// CHECK27-NEXT: [[CONV89:%.*]] = fpext float [[TMP50]] to double
|
|
// CHECK27-NEXT: [[ADD90:%.*]] = fadd double [[CONV89]], 1.000000e+00
|
|
// CHECK27-NEXT: [[CONV91:%.*]] = fptrunc double [[ADD90]] to float
|
|
// CHECK27-NEXT: store float [[CONV91]], float* [[ARRAYIDX]], align 4, !llvm.access.group !16
|
|
// CHECK27-NEXT: [[ARRAYIDX92:%.*]] = getelementptr inbounds float, float* [[VLA]], i32 3
|
|
// CHECK27-NEXT: [[TMP51:%.*]] = load float, float* [[ARRAYIDX92]], align 4, !llvm.access.group !16
|
|
// CHECK27-NEXT: [[CONV93:%.*]] = fpext float [[TMP51]] to double
|
|
// CHECK27-NEXT: [[ADD94:%.*]] = fadd double [[CONV93]], 1.000000e+00
|
|
// CHECK27-NEXT: [[CONV95:%.*]] = fptrunc double [[ADD94]] to float
|
|
// CHECK27-NEXT: store float [[CONV95]], float* [[ARRAYIDX92]], align 4, !llvm.access.group !16
|
|
// CHECK27-NEXT: [[ARRAYIDX96:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i32 0, i32 1
|
|
// CHECK27-NEXT: [[ARRAYIDX97:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX96]], i32 0, i32 2
|
|
// CHECK27-NEXT: [[TMP52:%.*]] = load double, double* [[ARRAYIDX97]], align 8, !llvm.access.group !16
|
|
// CHECK27-NEXT: [[ADD98:%.*]] = fadd double [[TMP52]], 1.000000e+00
|
|
// CHECK27-NEXT: store double [[ADD98]], double* [[ARRAYIDX97]], align 8, !llvm.access.group !16
|
|
// CHECK27-NEXT: [[TMP53:%.*]] = mul nsw i32 1, [[TMP2]]
|
|
// CHECK27-NEXT: [[ARRAYIDX99:%.*]] = getelementptr inbounds double, double* [[VLA1]], i32 [[TMP53]]
|
|
// CHECK27-NEXT: [[ARRAYIDX100:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX99]], i32 3
|
|
// CHECK27-NEXT: [[TMP54:%.*]] = load double, double* [[ARRAYIDX100]], align 8, !llvm.access.group !16
|
|
// CHECK27-NEXT: [[ADD101:%.*]] = fadd double [[TMP54]], 1.000000e+00
|
|
// CHECK27-NEXT: store double [[ADD101]], double* [[ARRAYIDX100]], align 8, !llvm.access.group !16
|
|
// CHECK27-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0
|
|
// CHECK27-NEXT: [[TMP55:%.*]] = load i64, i64* [[X]], align 4, !llvm.access.group !16
|
|
// CHECK27-NEXT: [[ADD102:%.*]] = add nsw i64 [[TMP55]], 1
|
|
// CHECK27-NEXT: store i64 [[ADD102]], i64* [[X]], align 4, !llvm.access.group !16
|
|
// CHECK27-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1
|
|
// CHECK27-NEXT: [[TMP56:%.*]] = load i8, i8* [[Y]], align 4, !llvm.access.group !16
|
|
// CHECK27-NEXT: [[CONV103:%.*]] = sext i8 [[TMP56]] to i32
|
|
// CHECK27-NEXT: [[ADD104:%.*]] = add nsw i32 [[CONV103]], 1
|
|
// CHECK27-NEXT: [[CONV105:%.*]] = trunc i32 [[ADD104]] to i8
|
|
// CHECK27-NEXT: store i8 [[CONV105]], i8* [[Y]], align 4, !llvm.access.group !16
|
|
// CHECK27-NEXT: br label [[OMP_BODY_CONTINUE106:%.*]]
|
|
// CHECK27: omp.body.continue106:
|
|
// CHECK27-NEXT: br label [[OMP_INNER_FOR_INC107:%.*]]
|
|
// CHECK27: omp.inner.for.inc107:
|
|
// CHECK27-NEXT: [[TMP57:%.*]] = load i32, i32* [[DOTOMP_IV80]], align 4, !llvm.access.group !16
|
|
// CHECK27-NEXT: [[ADD108:%.*]] = add nsw i32 [[TMP57]], 1
|
|
// CHECK27-NEXT: store i32 [[ADD108]], i32* [[DOTOMP_IV80]], align 4, !llvm.access.group !16
|
|
// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND82]], !llvm.loop [[LOOP17:![0-9]+]]
|
|
// CHECK27: omp.inner.for.end109:
|
|
// CHECK27-NEXT: store i8 96, i8* [[IT81]], align 1
|
|
// CHECK27-NEXT: [[TMP58:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK27-NEXT: [[TMP59:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
|
|
// CHECK27-NEXT: call void @llvm.stackrestore(i8* [[TMP59]])
|
|
// CHECK27-NEXT: ret i32 [[TMP58]]
|
|
//
|
|
//
|
|
// CHECK27-LABEL: define {{[^@]+}}@_Z3bari
|
|
// CHECK27-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
|
|
// CHECK27-NEXT: entry:
|
|
// CHECK27-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK27-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK27-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4
|
|
// CHECK27-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK27-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK27-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK27-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]])
|
|
// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
|
|
// CHECK27-NEXT: store i32 [[ADD]], i32* [[A]], align 4
|
|
// CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK27-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]])
|
|
// CHECK27-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK27-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
|
|
// CHECK27-NEXT: store i32 [[ADD2]], i32* [[A]], align 4
|
|
// CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK27-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]])
|
|
// CHECK27-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK27-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
|
|
// CHECK27-NEXT: store i32 [[ADD4]], i32* [[A]], align 4
|
|
// CHECK27-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK27-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]])
|
|
// CHECK27-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK27-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
|
|
// CHECK27-NEXT: store i32 [[ADD6]], i32* [[A]], align 4
|
|
// CHECK27-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK27-NEXT: ret i32 [[TMP8]]
|
|
//
|
|
//
|
|
// CHECK27-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
|
|
// CHECK27-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 {
|
|
// CHECK27-NEXT: entry:
|
|
// CHECK27-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
|
|
// CHECK27-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK27-NEXT: [[B:%.*]] = alloca i32, align 4
|
|
// CHECK27-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4
|
|
// CHECK27-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4
|
|
// CHECK27-NEXT: [[TMP:%.*]] = alloca i64, align 4
|
|
// CHECK27-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
|
|
// CHECK27-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
|
|
// CHECK27-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
|
|
// CHECK27-NEXT: [[IT:%.*]] = alloca i64, align 8
|
|
// CHECK27-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK27-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK27-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK27-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
|
|
// CHECK27-NEXT: store i32 [[ADD]], i32* [[B]], align 4
|
|
// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK27-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave()
|
|
// CHECK27-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4
|
|
// CHECK27-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]]
|
|
// CHECK27-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2
|
|
// CHECK27-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4
|
|
// CHECK27-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK27-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK27-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK27-NEXT: store i64 [[TMP4]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK27: omp.inner.for.cond:
|
|
// CHECK27-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !19
|
|
// CHECK27-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !19
|
|
// CHECK27-NEXT: [[CMP:%.*]] = icmp ule i64 [[TMP5]], [[TMP6]]
|
|
// CHECK27-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK27: omp.inner.for.body:
|
|
// CHECK27-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !19
|
|
// CHECK27-NEXT: [[MUL:%.*]] = mul i64 [[TMP7]], 400
|
|
// CHECK27-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]
|
|
// CHECK27-NEXT: store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !19
|
|
// CHECK27-NEXT: [[TMP8:%.*]] = load i32, i32* [[B]], align 4, !llvm.access.group !19
|
|
// CHECK27-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP8]] to double
|
|
// CHECK27-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00
|
|
// CHECK27-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
|
|
// CHECK27-NEXT: store double [[ADD2]], double* [[A]], align 4, !llvm.access.group !19
|
|
// CHECK27-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
|
|
// CHECK27-NEXT: [[TMP9:%.*]] = load double, double* [[A3]], align 4, !llvm.access.group !19
|
|
// CHECK27-NEXT: [[INC:%.*]] = fadd double [[TMP9]], 1.000000e+00
|
|
// CHECK27-NEXT: store double [[INC]], double* [[A3]], align 4, !llvm.access.group !19
|
|
// CHECK27-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16
|
|
// CHECK27-NEXT: [[TMP10:%.*]] = mul nsw i32 1, [[TMP1]]
|
|
// CHECK27-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP10]]
|
|
// CHECK27-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
|
|
// CHECK27-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2, !llvm.access.group !19
|
|
// CHECK27-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK27: omp.body.continue:
|
|
// CHECK27-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK27: omp.inner.for.inc:
|
|
// CHECK27-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !19
|
|
// CHECK27-NEXT: [[ADD6:%.*]] = add i64 [[TMP11]], 1
|
|
// CHECK27-NEXT: store i64 [[ADD6]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !19
|
|
// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]]
|
|
// CHECK27: omp.inner.for.end:
|
|
// CHECK27-NEXT: store i64 400, i64* [[IT]], align 8
|
|
// CHECK27-NEXT: [[TMP12:%.*]] = mul nsw i32 1, [[TMP1]]
|
|
// CHECK27-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP12]]
|
|
// CHECK27-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX7]], i32 1
|
|
// CHECK27-NEXT: [[TMP13:%.*]] = load i16, i16* [[ARRAYIDX8]], align 2
|
|
// CHECK27-NEXT: [[CONV9:%.*]] = sext i16 [[TMP13]] to i32
|
|
// CHECK27-NEXT: [[TMP14:%.*]] = load i32, i32* [[B]], align 4
|
|
// CHECK27-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[TMP14]]
|
|
// CHECK27-NEXT: [[TMP15:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
|
|
// CHECK27-NEXT: call void @llvm.stackrestore(i8* [[TMP15]])
|
|
// CHECK27-NEXT: ret i32 [[ADD10]]
|
|
//
|
|
//
|
|
// CHECK27-LABEL: define {{[^@]+}}@_ZL7fstatici
|
|
// CHECK27-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
|
|
// CHECK27-NEXT: entry:
|
|
// CHECK27-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK27-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK27-NEXT: [[AA:%.*]] = alloca i16, align 2
|
|
// CHECK27-NEXT: [[AAA:%.*]] = alloca i8, align 1
|
|
// CHECK27-NEXT: [[B:%.*]] = alloca [10 x i32], align 4
|
|
// CHECK27-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK27-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK27-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK27-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK27-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK27-NEXT: store i16 0, i16* [[AA]], align 2
|
|
// CHECK27-NEXT: store i8 0, i8* [[AAA]], align 1
|
|
// CHECK27-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK27-NEXT: store i32 429496720, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK27-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK27-NEXT: ret i32 [[TMP0]]
|
|
//
|
|
//
|
|
// CHECK27-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
|
|
// CHECK27-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat {
|
|
// CHECK27-NEXT: entry:
|
|
// CHECK27-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK27-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK27-NEXT: [[AA:%.*]] = alloca i16, align 2
|
|
// CHECK27-NEXT: [[B:%.*]] = alloca [10 x i32], align 4
|
|
// CHECK27-NEXT: [[TMP:%.*]] = alloca i64, align 4
|
|
// CHECK27-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
|
|
// CHECK27-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
|
|
// CHECK27-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
|
|
// CHECK27-NEXT: [[I:%.*]] = alloca i64, align 8
|
|
// CHECK27-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK27-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK27-NEXT: store i16 0, i16* [[AA]], align 2
|
|
// CHECK27-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK27-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK27-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK27-NEXT: store i64 [[TMP0]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK27: omp.inner.for.cond:
|
|
// CHECK27-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !22
|
|
// CHECK27-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !22
|
|
// CHECK27-NEXT: [[CMP:%.*]] = icmp sle i64 [[TMP1]], [[TMP2]]
|
|
// CHECK27-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK27: omp.inner.for.body:
|
|
// CHECK27-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !22
|
|
// CHECK27-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP3]], 3
|
|
// CHECK27-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
|
|
// CHECK27-NEXT: store i64 [[ADD]], i64* [[I]], align 8, !llvm.access.group !22
|
|
// CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !22
|
|
// CHECK27-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1
|
|
// CHECK27-NEXT: store i32 [[ADD1]], i32* [[A]], align 4, !llvm.access.group !22
|
|
// CHECK27-NEXT: [[TMP5:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !22
|
|
// CHECK27-NEXT: [[CONV:%.*]] = sext i16 [[TMP5]] to i32
|
|
// CHECK27-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 1
|
|
// CHECK27-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
|
|
// CHECK27-NEXT: store i16 [[CONV3]], i16* [[AA]], align 2, !llvm.access.group !22
|
|
// CHECK27-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2
|
|
// CHECK27-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !22
|
|
// CHECK27-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP6]], 1
|
|
// CHECK27-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !22
|
|
// CHECK27-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK27: omp.body.continue:
|
|
// CHECK27-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK27: omp.inner.for.inc:
|
|
// CHECK27-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !22
|
|
// CHECK27-NEXT: [[ADD5:%.*]] = add nsw i64 [[TMP7]], 1
|
|
// CHECK27-NEXT: store i64 [[ADD5]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !22
|
|
// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]]
|
|
// CHECK27: omp.inner.for.end:
|
|
// CHECK27-NEXT: store i64 11, i64* [[I]], align 8
|
|
// CHECK27-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK27-NEXT: ret i32 [[TMP8]]
|
|
//
|
|
//
|
|
// CHECK28-LABEL: define {{[^@]+}}@_Z7get_valv
|
|
// CHECK28-SAME: () #[[ATTR0:[0-9]+]] {
|
|
// CHECK28-NEXT: entry:
|
|
// CHECK28-NEXT: ret i64 0
|
|
//
|
|
//
|
|
// CHECK28-LABEL: define {{[^@]+}}@_Z3fooi
|
|
// CHECK28-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
|
|
// CHECK28-NEXT: entry:
|
|
// CHECK28-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK28-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK28-NEXT: [[AA:%.*]] = alloca i16, align 2
|
|
// CHECK28-NEXT: [[B:%.*]] = alloca [10 x float], align 4
|
|
// CHECK28-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4
|
|
// CHECK28-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4
|
|
// CHECK28-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8
|
|
// CHECK28-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4
|
|
// CHECK28-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4
|
|
// CHECK28-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK28-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK28-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK28-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK28-NEXT: [[I:%.*]] = alloca i32, align 4
|
|
// CHECK28-NEXT: [[K:%.*]] = alloca i64, align 8
|
|
// CHECK28-NEXT: [[_TMP3:%.*]] = alloca i32, align 4
|
|
// CHECK28-NEXT: [[DOTOMP_LB4:%.*]] = alloca i32, align 4
|
|
// CHECK28-NEXT: [[DOTOMP_UB5:%.*]] = alloca i32, align 4
|
|
// CHECK28-NEXT: [[DOTOMP_IV6:%.*]] = alloca i32, align 4
|
|
// CHECK28-NEXT: [[DOTLINEAR_START:%.*]] = alloca i64, align 8
|
|
// CHECK28-NEXT: [[I7:%.*]] = alloca i32, align 4
|
|
// CHECK28-NEXT: [[K8:%.*]] = alloca i64, align 8
|
|
// CHECK28-NEXT: [[LIN:%.*]] = alloca i32, align 4
|
|
// CHECK28-NEXT: [[_TMP21:%.*]] = alloca i64, align 4
|
|
// CHECK28-NEXT: [[DOTOMP_LB22:%.*]] = alloca i64, align 8
|
|
// CHECK28-NEXT: [[DOTOMP_UB23:%.*]] = alloca i64, align 8
|
|
// CHECK28-NEXT: [[DOTOMP_IV24:%.*]] = alloca i64, align 8
|
|
// CHECK28-NEXT: [[DOTLINEAR_START25:%.*]] = alloca i32, align 4
|
|
// CHECK28-NEXT: [[DOTLINEAR_START26:%.*]] = alloca i32, align 4
|
|
// CHECK28-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8
|
|
// CHECK28-NEXT: [[IT:%.*]] = alloca i64, align 8
|
|
// CHECK28-NEXT: [[LIN28:%.*]] = alloca i32, align 4
|
|
// CHECK28-NEXT: [[A29:%.*]] = alloca i32, align 4
|
|
// CHECK28-NEXT: [[_TMP58:%.*]] = alloca i16, align 2
|
|
// CHECK28-NEXT: [[DOTOMP_LB59:%.*]] = alloca i32, align 4
|
|
// CHECK28-NEXT: [[DOTOMP_UB60:%.*]] = alloca i32, align 4
|
|
// CHECK28-NEXT: [[DOTOMP_IV61:%.*]] = alloca i32, align 4
|
|
// CHECK28-NEXT: [[IT62:%.*]] = alloca i16, align 2
|
|
// CHECK28-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
|
// CHECK28-NEXT: [[_TMP77:%.*]] = alloca i8, align 1
|
|
// CHECK28-NEXT: [[DOTOMP_LB78:%.*]] = alloca i32, align 4
|
|
// CHECK28-NEXT: [[DOTOMP_UB79:%.*]] = alloca i32, align 4
|
|
// CHECK28-NEXT: [[DOTOMP_IV80:%.*]] = alloca i32, align 4
|
|
// CHECK28-NEXT: [[IT81:%.*]] = alloca i8, align 1
|
|
// CHECK28-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK28-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK28-NEXT: store i16 0, i16* [[AA]], align 2
|
|
// CHECK28-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK28-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave()
|
|
// CHECK28-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4
|
|
// CHECK28-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4
|
|
// CHECK28-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4
|
|
// CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK28-NEXT: [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]]
|
|
// CHECK28-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8
|
|
// CHECK28-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4
|
|
// CHECK28-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK28-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK28-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK28: omp.inner.for.cond:
|
|
// CHECK28-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
|
|
// CHECK28-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !3
|
|
// CHECK28-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
|
|
// CHECK28-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK28: omp.inner.for.body:
|
|
// CHECK28-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
|
|
// CHECK28-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5
|
|
// CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]]
|
|
// CHECK28-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !3
|
|
// CHECK28-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK28: omp.body.continue:
|
|
// CHECK28-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK28: omp.inner.for.inc:
|
|
// CHECK28-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
|
|
// CHECK28-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
|
|
// CHECK28-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
|
|
// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]
|
|
// CHECK28: omp.inner.for.end:
|
|
// CHECK28-NEXT: store i32 33, i32* [[I]], align 4
|
|
// CHECK28-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv()
|
|
// CHECK28-NEXT: store i64 [[CALL]], i64* [[K]], align 8
|
|
// CHECK28-NEXT: store i32 0, i32* [[DOTOMP_LB4]], align 4
|
|
// CHECK28-NEXT: store i32 8, i32* [[DOTOMP_UB5]], align 4
|
|
// CHECK28-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_LB4]], align 4
|
|
// CHECK28-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV6]], align 4
|
|
// CHECK28-NEXT: [[TMP10:%.*]] = load i64, i64* [[K]], align 8
|
|
// CHECK28-NEXT: store i64 [[TMP10]], i64* [[DOTLINEAR_START]], align 8
|
|
// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND9:%.*]]
|
|
// CHECK28: omp.inner.for.cond9:
|
|
// CHECK28-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !7
|
|
// CHECK28-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB5]], align 4, !llvm.access.group !7
|
|
// CHECK28-NEXT: [[CMP10:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]]
|
|
// CHECK28-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY11:%.*]], label [[OMP_INNER_FOR_END19:%.*]]
|
|
// CHECK28: omp.inner.for.body11:
|
|
// CHECK28-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !7
|
|
// CHECK28-NEXT: [[MUL12:%.*]] = mul nsw i32 [[TMP13]], 1
|
|
// CHECK28-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL12]]
|
|
// CHECK28-NEXT: store i32 [[SUB]], i32* [[I7]], align 4, !llvm.access.group !7
|
|
// CHECK28-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8, !llvm.access.group !7
|
|
// CHECK28-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !7
|
|
// CHECK28-NEXT: [[MUL13:%.*]] = mul nsw i32 [[TMP15]], 3
|
|
// CHECK28-NEXT: [[CONV:%.*]] = sext i32 [[MUL13]] to i64
|
|
// CHECK28-NEXT: [[ADD14:%.*]] = add nsw i64 [[TMP14]], [[CONV]]
|
|
// CHECK28-NEXT: store i64 [[ADD14]], i64* [[K8]], align 8, !llvm.access.group !7
|
|
// CHECK28-NEXT: [[TMP16:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !7
|
|
// CHECK28-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP16]], 1
|
|
// CHECK28-NEXT: store i32 [[ADD15]], i32* [[A]], align 4, !llvm.access.group !7
|
|
// CHECK28-NEXT: br label [[OMP_BODY_CONTINUE16:%.*]]
|
|
// CHECK28: omp.body.continue16:
|
|
// CHECK28-NEXT: br label [[OMP_INNER_FOR_INC17:%.*]]
|
|
// CHECK28: omp.inner.for.inc17:
|
|
// CHECK28-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !7
|
|
// CHECK28-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP17]], 1
|
|
// CHECK28-NEXT: store i32 [[ADD18]], i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !7
|
|
// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND9]], !llvm.loop [[LOOP8:![0-9]+]]
|
|
// CHECK28: omp.inner.for.end19:
|
|
// CHECK28-NEXT: store i32 1, i32* [[I7]], align 4
|
|
// CHECK28-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8
|
|
// CHECK28-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP18]], 27
|
|
// CHECK28-NEXT: store i64 [[ADD20]], i64* [[K]], align 8
|
|
// CHECK28-NEXT: store i32 12, i32* [[LIN]], align 4
|
|
// CHECK28-NEXT: store i64 0, i64* [[DOTOMP_LB22]], align 8
|
|
// CHECK28-NEXT: store i64 3, i64* [[DOTOMP_UB23]], align 8
|
|
// CHECK28-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_LB22]], align 8
|
|
// CHECK28-NEXT: store i64 [[TMP19]], i64* [[DOTOMP_IV24]], align 8
|
|
// CHECK28-NEXT: [[TMP20:%.*]] = load i32, i32* [[LIN]], align 4
|
|
// CHECK28-NEXT: store i32 [[TMP20]], i32* [[DOTLINEAR_START25]], align 4
|
|
// CHECK28-NEXT: [[TMP21:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK28-NEXT: store i32 [[TMP21]], i32* [[DOTLINEAR_START26]], align 4
|
|
// CHECK28-NEXT: [[CALL27:%.*]] = call i64 @_Z7get_valv()
|
|
// CHECK28-NEXT: store i64 [[CALL27]], i64* [[DOTLINEAR_STEP]], align 8
|
|
// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND30:%.*]]
|
|
// CHECK28: omp.inner.for.cond30:
|
|
// CHECK28-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !10
|
|
// CHECK28-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_UB23]], align 8, !llvm.access.group !10
|
|
// CHECK28-NEXT: [[CMP31:%.*]] = icmp ule i64 [[TMP22]], [[TMP23]]
|
|
// CHECK28-NEXT: br i1 [[CMP31]], label [[OMP_INNER_FOR_BODY32:%.*]], label [[OMP_INNER_FOR_END49:%.*]]
|
|
// CHECK28: omp.inner.for.body32:
|
|
// CHECK28-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !10
|
|
// CHECK28-NEXT: [[MUL33:%.*]] = mul i64 [[TMP24]], 400
|
|
// CHECK28-NEXT: [[SUB34:%.*]] = sub i64 2000, [[MUL33]]
|
|
// CHECK28-NEXT: store i64 [[SUB34]], i64* [[IT]], align 8, !llvm.access.group !10
|
|
// CHECK28-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTLINEAR_START25]], align 4, !llvm.access.group !10
|
|
// CHECK28-NEXT: [[CONV35:%.*]] = sext i32 [[TMP25]] to i64
|
|
// CHECK28-NEXT: [[TMP26:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !10
|
|
// CHECK28-NEXT: [[TMP27:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !10
|
|
// CHECK28-NEXT: [[MUL36:%.*]] = mul i64 [[TMP26]], [[TMP27]]
|
|
// CHECK28-NEXT: [[ADD37:%.*]] = add i64 [[CONV35]], [[MUL36]]
|
|
// CHECK28-NEXT: [[CONV38:%.*]] = trunc i64 [[ADD37]] to i32
|
|
// CHECK28-NEXT: store i32 [[CONV38]], i32* [[LIN28]], align 4, !llvm.access.group !10
|
|
// CHECK28-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTLINEAR_START26]], align 4, !llvm.access.group !10
|
|
// CHECK28-NEXT: [[CONV39:%.*]] = sext i32 [[TMP28]] to i64
|
|
// CHECK28-NEXT: [[TMP29:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !10
|
|
// CHECK28-NEXT: [[TMP30:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !10
|
|
// CHECK28-NEXT: [[MUL40:%.*]] = mul i64 [[TMP29]], [[TMP30]]
|
|
// CHECK28-NEXT: [[ADD41:%.*]] = add i64 [[CONV39]], [[MUL40]]
|
|
// CHECK28-NEXT: [[CONV42:%.*]] = trunc i64 [[ADD41]] to i32
|
|
// CHECK28-NEXT: store i32 [[CONV42]], i32* [[A29]], align 4, !llvm.access.group !10
|
|
// CHECK28-NEXT: [[TMP31:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !10
|
|
// CHECK28-NEXT: [[CONV43:%.*]] = sext i16 [[TMP31]] to i32
|
|
// CHECK28-NEXT: [[ADD44:%.*]] = add nsw i32 [[CONV43]], 1
|
|
// CHECK28-NEXT: [[CONV45:%.*]] = trunc i32 [[ADD44]] to i16
|
|
// CHECK28-NEXT: store i16 [[CONV45]], i16* [[AA]], align 2, !llvm.access.group !10
|
|
// CHECK28-NEXT: br label [[OMP_BODY_CONTINUE46:%.*]]
|
|
// CHECK28: omp.body.continue46:
|
|
// CHECK28-NEXT: br label [[OMP_INNER_FOR_INC47:%.*]]
|
|
// CHECK28: omp.inner.for.inc47:
|
|
// CHECK28-NEXT: [[TMP32:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !10
|
|
// CHECK28-NEXT: [[ADD48:%.*]] = add i64 [[TMP32]], 1
|
|
// CHECK28-NEXT: store i64 [[ADD48]], i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !10
|
|
// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND30]], !llvm.loop [[LOOP11:![0-9]+]]
|
|
// CHECK28: omp.inner.for.end49:
|
|
// CHECK28-NEXT: store i64 400, i64* [[IT]], align 8
|
|
// CHECK28-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTLINEAR_START25]], align 4
|
|
// CHECK28-NEXT: [[CONV50:%.*]] = sext i32 [[TMP33]] to i64
|
|
// CHECK28-NEXT: [[TMP34:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
|
|
// CHECK28-NEXT: [[MUL51:%.*]] = mul i64 4, [[TMP34]]
|
|
// CHECK28-NEXT: [[ADD52:%.*]] = add i64 [[CONV50]], [[MUL51]]
|
|
// CHECK28-NEXT: [[CONV53:%.*]] = trunc i64 [[ADD52]] to i32
|
|
// CHECK28-NEXT: store i32 [[CONV53]], i32* [[LIN]], align 4
|
|
// CHECK28-NEXT: [[TMP35:%.*]] = load i32, i32* [[DOTLINEAR_START26]], align 4
|
|
// CHECK28-NEXT: [[CONV54:%.*]] = sext i32 [[TMP35]] to i64
|
|
// CHECK28-NEXT: [[TMP36:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
|
|
// CHECK28-NEXT: [[MUL55:%.*]] = mul i64 4, [[TMP36]]
|
|
// CHECK28-NEXT: [[ADD56:%.*]] = add i64 [[CONV54]], [[MUL55]]
|
|
// CHECK28-NEXT: [[CONV57:%.*]] = trunc i64 [[ADD56]] to i32
|
|
// CHECK28-NEXT: store i32 [[CONV57]], i32* [[A]], align 4
|
|
// CHECK28-NEXT: store i32 0, i32* [[DOTOMP_LB59]], align 4
|
|
// CHECK28-NEXT: store i32 3, i32* [[DOTOMP_UB60]], align 4
|
|
// CHECK28-NEXT: [[TMP37:%.*]] = load i32, i32* [[DOTOMP_LB59]], align 4
|
|
// CHECK28-NEXT: store i32 [[TMP37]], i32* [[DOTOMP_IV61]], align 4
|
|
// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND63:%.*]]
|
|
// CHECK28: omp.inner.for.cond63:
|
|
// CHECK28-NEXT: [[TMP38:%.*]] = load i32, i32* [[DOTOMP_IV61]], align 4, !llvm.access.group !13
|
|
// CHECK28-NEXT: [[TMP39:%.*]] = load i32, i32* [[DOTOMP_UB60]], align 4, !llvm.access.group !13
|
|
// CHECK28-NEXT: [[CMP64:%.*]] = icmp sle i32 [[TMP38]], [[TMP39]]
|
|
// CHECK28-NEXT: br i1 [[CMP64]], label [[OMP_INNER_FOR_BODY65:%.*]], label [[OMP_INNER_FOR_END76:%.*]]
|
|
// CHECK28: omp.inner.for.body65:
|
|
// CHECK28-NEXT: [[TMP40:%.*]] = load i32, i32* [[DOTOMP_IV61]], align 4, !llvm.access.group !13
|
|
// CHECK28-NEXT: [[MUL66:%.*]] = mul nsw i32 [[TMP40]], 4
|
|
// CHECK28-NEXT: [[ADD67:%.*]] = add nsw i32 6, [[MUL66]]
|
|
// CHECK28-NEXT: [[CONV68:%.*]] = trunc i32 [[ADD67]] to i16
|
|
// CHECK28-NEXT: store i16 [[CONV68]], i16* [[IT62]], align 2, !llvm.access.group !13
|
|
// CHECK28-NEXT: [[TMP41:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !13
|
|
// CHECK28-NEXT: [[ADD69:%.*]] = add nsw i32 [[TMP41]], 1
|
|
// CHECK28-NEXT: store i32 [[ADD69]], i32* [[A]], align 4, !llvm.access.group !13
|
|
// CHECK28-NEXT: [[TMP42:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !13
|
|
// CHECK28-NEXT: [[CONV70:%.*]] = sext i16 [[TMP42]] to i32
|
|
// CHECK28-NEXT: [[ADD71:%.*]] = add nsw i32 [[CONV70]], 1
|
|
// CHECK28-NEXT: [[CONV72:%.*]] = trunc i32 [[ADD71]] to i16
|
|
// CHECK28-NEXT: store i16 [[CONV72]], i16* [[AA]], align 2, !llvm.access.group !13
|
|
// CHECK28-NEXT: br label [[OMP_BODY_CONTINUE73:%.*]]
|
|
// CHECK28: omp.body.continue73:
|
|
// CHECK28-NEXT: br label [[OMP_INNER_FOR_INC74:%.*]]
|
|
// CHECK28: omp.inner.for.inc74:
|
|
// CHECK28-NEXT: [[TMP43:%.*]] = load i32, i32* [[DOTOMP_IV61]], align 4, !llvm.access.group !13
|
|
// CHECK28-NEXT: [[ADD75:%.*]] = add nsw i32 [[TMP43]], 1
|
|
// CHECK28-NEXT: store i32 [[ADD75]], i32* [[DOTOMP_IV61]], align 4, !llvm.access.group !13
|
|
// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND63]], !llvm.loop [[LOOP14:![0-9]+]]
|
|
// CHECK28: omp.inner.for.end76:
|
|
// CHECK28-NEXT: store i16 22, i16* [[IT62]], align 2
|
|
// CHECK28-NEXT: [[TMP44:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK28-NEXT: store i32 [[TMP44]], i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK28-NEXT: store i32 0, i32* [[DOTOMP_LB78]], align 4
|
|
// CHECK28-NEXT: store i32 25, i32* [[DOTOMP_UB79]], align 4
|
|
// CHECK28-NEXT: [[TMP45:%.*]] = load i32, i32* [[DOTOMP_LB78]], align 4
|
|
// CHECK28-NEXT: store i32 [[TMP45]], i32* [[DOTOMP_IV80]], align 4
|
|
// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND82:%.*]]
|
|
// CHECK28: omp.inner.for.cond82:
|
|
// CHECK28-NEXT: [[TMP46:%.*]] = load i32, i32* [[DOTOMP_IV80]], align 4, !llvm.access.group !16
|
|
// CHECK28-NEXT: [[TMP47:%.*]] = load i32, i32* [[DOTOMP_UB79]], align 4, !llvm.access.group !16
|
|
// CHECK28-NEXT: [[CMP83:%.*]] = icmp sle i32 [[TMP46]], [[TMP47]]
|
|
// CHECK28-NEXT: br i1 [[CMP83]], label [[OMP_INNER_FOR_BODY84:%.*]], label [[OMP_INNER_FOR_END109:%.*]]
|
|
// CHECK28: omp.inner.for.body84:
|
|
// CHECK28-NEXT: [[TMP48:%.*]] = load i32, i32* [[DOTOMP_IV80]], align 4, !llvm.access.group !16
|
|
// CHECK28-NEXT: [[MUL85:%.*]] = mul nsw i32 [[TMP48]], 1
|
|
// CHECK28-NEXT: [[SUB86:%.*]] = sub nsw i32 122, [[MUL85]]
|
|
// CHECK28-NEXT: [[CONV87:%.*]] = trunc i32 [[SUB86]] to i8
|
|
// CHECK28-NEXT: store i8 [[CONV87]], i8* [[IT81]], align 1, !llvm.access.group !16
|
|
// CHECK28-NEXT: [[TMP49:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !16
|
|
// CHECK28-NEXT: [[ADD88:%.*]] = add nsw i32 [[TMP49]], 1
|
|
// CHECK28-NEXT: store i32 [[ADD88]], i32* [[A]], align 4, !llvm.access.group !16
|
|
// CHECK28-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 2
|
|
// CHECK28-NEXT: [[TMP50:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !16
|
|
// CHECK28-NEXT: [[CONV89:%.*]] = fpext float [[TMP50]] to double
|
|
// CHECK28-NEXT: [[ADD90:%.*]] = fadd double [[CONV89]], 1.000000e+00
|
|
// CHECK28-NEXT: [[CONV91:%.*]] = fptrunc double [[ADD90]] to float
|
|
// CHECK28-NEXT: store float [[CONV91]], float* [[ARRAYIDX]], align 4, !llvm.access.group !16
|
|
// CHECK28-NEXT: [[ARRAYIDX92:%.*]] = getelementptr inbounds float, float* [[VLA]], i32 3
|
|
// CHECK28-NEXT: [[TMP51:%.*]] = load float, float* [[ARRAYIDX92]], align 4, !llvm.access.group !16
|
|
// CHECK28-NEXT: [[CONV93:%.*]] = fpext float [[TMP51]] to double
|
|
// CHECK28-NEXT: [[ADD94:%.*]] = fadd double [[CONV93]], 1.000000e+00
|
|
// CHECK28-NEXT: [[CONV95:%.*]] = fptrunc double [[ADD94]] to float
|
|
// CHECK28-NEXT: store float [[CONV95]], float* [[ARRAYIDX92]], align 4, !llvm.access.group !16
|
|
// CHECK28-NEXT: [[ARRAYIDX96:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i32 0, i32 1
|
|
// CHECK28-NEXT: [[ARRAYIDX97:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX96]], i32 0, i32 2
|
|
// CHECK28-NEXT: [[TMP52:%.*]] = load double, double* [[ARRAYIDX97]], align 8, !llvm.access.group !16
|
|
// CHECK28-NEXT: [[ADD98:%.*]] = fadd double [[TMP52]], 1.000000e+00
|
|
// CHECK28-NEXT: store double [[ADD98]], double* [[ARRAYIDX97]], align 8, !llvm.access.group !16
|
|
// CHECK28-NEXT: [[TMP53:%.*]] = mul nsw i32 1, [[TMP2]]
|
|
// CHECK28-NEXT: [[ARRAYIDX99:%.*]] = getelementptr inbounds double, double* [[VLA1]], i32 [[TMP53]]
|
|
// CHECK28-NEXT: [[ARRAYIDX100:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX99]], i32 3
|
|
// CHECK28-NEXT: [[TMP54:%.*]] = load double, double* [[ARRAYIDX100]], align 8, !llvm.access.group !16
|
|
// CHECK28-NEXT: [[ADD101:%.*]] = fadd double [[TMP54]], 1.000000e+00
|
|
// CHECK28-NEXT: store double [[ADD101]], double* [[ARRAYIDX100]], align 8, !llvm.access.group !16
|
|
// CHECK28-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0
|
|
// CHECK28-NEXT: [[TMP55:%.*]] = load i64, i64* [[X]], align 4, !llvm.access.group !16
|
|
// CHECK28-NEXT: [[ADD102:%.*]] = add nsw i64 [[TMP55]], 1
|
|
// CHECK28-NEXT: store i64 [[ADD102]], i64* [[X]], align 4, !llvm.access.group !16
|
|
// CHECK28-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1
|
|
// CHECK28-NEXT: [[TMP56:%.*]] = load i8, i8* [[Y]], align 4, !llvm.access.group !16
|
|
// CHECK28-NEXT: [[CONV103:%.*]] = sext i8 [[TMP56]] to i32
|
|
// CHECK28-NEXT: [[ADD104:%.*]] = add nsw i32 [[CONV103]], 1
|
|
// CHECK28-NEXT: [[CONV105:%.*]] = trunc i32 [[ADD104]] to i8
|
|
// CHECK28-NEXT: store i8 [[CONV105]], i8* [[Y]], align 4, !llvm.access.group !16
|
|
// CHECK28-NEXT: br label [[OMP_BODY_CONTINUE106:%.*]]
|
|
// CHECK28: omp.body.continue106:
|
|
// CHECK28-NEXT: br label [[OMP_INNER_FOR_INC107:%.*]]
|
|
// CHECK28: omp.inner.for.inc107:
|
|
// CHECK28-NEXT: [[TMP57:%.*]] = load i32, i32* [[DOTOMP_IV80]], align 4, !llvm.access.group !16
|
|
// CHECK28-NEXT: [[ADD108:%.*]] = add nsw i32 [[TMP57]], 1
|
|
// CHECK28-NEXT: store i32 [[ADD108]], i32* [[DOTOMP_IV80]], align 4, !llvm.access.group !16
|
|
// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND82]], !llvm.loop [[LOOP17:![0-9]+]]
|
|
// CHECK28: omp.inner.for.end109:
|
|
// CHECK28-NEXT: store i8 96, i8* [[IT81]], align 1
|
|
// CHECK28-NEXT: [[TMP58:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK28-NEXT: [[TMP59:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
|
|
// CHECK28-NEXT: call void @llvm.stackrestore(i8* [[TMP59]])
|
|
// CHECK28-NEXT: ret i32 [[TMP58]]
|
|
//
|
|
//
|
|
// CHECK28-LABEL: define {{[^@]+}}@_Z3bari
|
|
// CHECK28-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
|
|
// CHECK28-NEXT: entry:
|
|
// CHECK28-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK28-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK28-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4
|
|
// CHECK28-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK28-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK28-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK28-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]])
|
|
// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
|
|
// CHECK28-NEXT: store i32 [[ADD]], i32* [[A]], align 4
|
|
// CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK28-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]])
|
|
// CHECK28-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK28-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
|
|
// CHECK28-NEXT: store i32 [[ADD2]], i32* [[A]], align 4
|
|
// CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK28-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]])
|
|
// CHECK28-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK28-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
|
|
// CHECK28-NEXT: store i32 [[ADD4]], i32* [[A]], align 4
|
|
// CHECK28-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK28-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]])
|
|
// CHECK28-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK28-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
|
|
// CHECK28-NEXT: store i32 [[ADD6]], i32* [[A]], align 4
|
|
// CHECK28-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK28-NEXT: ret i32 [[TMP8]]
|
|
//
|
|
//
|
|
// CHECK28-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
|
|
// CHECK28-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 {
|
|
// CHECK28-NEXT: entry:
|
|
// CHECK28-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
|
|
// CHECK28-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK28-NEXT: [[B:%.*]] = alloca i32, align 4
|
|
// CHECK28-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4
|
|
// CHECK28-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4
|
|
// CHECK28-NEXT: [[TMP:%.*]] = alloca i64, align 4
|
|
// CHECK28-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
|
|
// CHECK28-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
|
|
// CHECK28-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
|
|
// CHECK28-NEXT: [[IT:%.*]] = alloca i64, align 8
|
|
// CHECK28-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK28-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK28-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK28-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
|
|
// CHECK28-NEXT: store i32 [[ADD]], i32* [[B]], align 4
|
|
// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK28-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave()
|
|
// CHECK28-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4
|
|
// CHECK28-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]]
|
|
// CHECK28-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2
|
|
// CHECK28-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4
|
|
// CHECK28-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK28-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK28-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK28-NEXT: store i64 [[TMP4]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK28: omp.inner.for.cond:
|
|
// CHECK28-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !19
|
|
// CHECK28-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !19
|
|
// CHECK28-NEXT: [[CMP:%.*]] = icmp ule i64 [[TMP5]], [[TMP6]]
|
|
// CHECK28-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK28: omp.inner.for.body:
|
|
// CHECK28-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !19
|
|
// CHECK28-NEXT: [[MUL:%.*]] = mul i64 [[TMP7]], 400
|
|
// CHECK28-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]
|
|
// CHECK28-NEXT: store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !19
|
|
// CHECK28-NEXT: [[TMP8:%.*]] = load i32, i32* [[B]], align 4, !llvm.access.group !19
|
|
// CHECK28-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP8]] to double
|
|
// CHECK28-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00
|
|
// CHECK28-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
|
|
// CHECK28-NEXT: store double [[ADD2]], double* [[A]], align 4, !llvm.access.group !19
|
|
// CHECK28-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
|
|
// CHECK28-NEXT: [[TMP9:%.*]] = load double, double* [[A3]], align 4, !llvm.access.group !19
|
|
// CHECK28-NEXT: [[INC:%.*]] = fadd double [[TMP9]], 1.000000e+00
|
|
// CHECK28-NEXT: store double [[INC]], double* [[A3]], align 4, !llvm.access.group !19
|
|
// CHECK28-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16
|
|
// CHECK28-NEXT: [[TMP10:%.*]] = mul nsw i32 1, [[TMP1]]
|
|
// CHECK28-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP10]]
|
|
// CHECK28-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
|
|
// CHECK28-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2, !llvm.access.group !19
|
|
// CHECK28-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK28: omp.body.continue:
|
|
// CHECK28-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK28: omp.inner.for.inc:
|
|
// CHECK28-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !19
|
|
// CHECK28-NEXT: [[ADD6:%.*]] = add i64 [[TMP11]], 1
|
|
// CHECK28-NEXT: store i64 [[ADD6]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !19
|
|
// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]]
|
|
// CHECK28: omp.inner.for.end:
|
|
// CHECK28-NEXT: store i64 400, i64* [[IT]], align 8
|
|
// CHECK28-NEXT: [[TMP12:%.*]] = mul nsw i32 1, [[TMP1]]
|
|
// CHECK28-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP12]]
|
|
// CHECK28-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX7]], i32 1
|
|
// CHECK28-NEXT: [[TMP13:%.*]] = load i16, i16* [[ARRAYIDX8]], align 2
|
|
// CHECK28-NEXT: [[CONV9:%.*]] = sext i16 [[TMP13]] to i32
|
|
// CHECK28-NEXT: [[TMP14:%.*]] = load i32, i32* [[B]], align 4
|
|
// CHECK28-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[TMP14]]
|
|
// CHECK28-NEXT: [[TMP15:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
|
|
// CHECK28-NEXT: call void @llvm.stackrestore(i8* [[TMP15]])
|
|
// CHECK28-NEXT: ret i32 [[ADD10]]
|
|
//
|
|
//
|
|
// CHECK28-LABEL: define {{[^@]+}}@_ZL7fstatici
|
|
// CHECK28-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
|
|
// CHECK28-NEXT: entry:
|
|
// CHECK28-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK28-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK28-NEXT: [[AA:%.*]] = alloca i16, align 2
|
|
// CHECK28-NEXT: [[AAA:%.*]] = alloca i8, align 1
|
|
// CHECK28-NEXT: [[B:%.*]] = alloca [10 x i32], align 4
|
|
// CHECK28-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK28-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK28-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK28-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK28-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK28-NEXT: store i16 0, i16* [[AA]], align 2
|
|
// CHECK28-NEXT: store i8 0, i8* [[AAA]], align 1
|
|
// CHECK28-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK28-NEXT: store i32 429496720, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK28-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK28-NEXT: ret i32 [[TMP0]]
|
|
//
|
|
//
|
|
// CHECK28-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
|
|
// CHECK28-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat {
|
|
// CHECK28-NEXT: entry:
|
|
// CHECK28-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK28-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK28-NEXT: [[AA:%.*]] = alloca i16, align 2
|
|
// CHECK28-NEXT: [[B:%.*]] = alloca [10 x i32], align 4
|
|
// CHECK28-NEXT: [[TMP:%.*]] = alloca i64, align 4
|
|
// CHECK28-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
|
|
// CHECK28-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
|
|
// CHECK28-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
|
|
// CHECK28-NEXT: [[I:%.*]] = alloca i64, align 8
|
|
// CHECK28-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK28-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK28-NEXT: store i16 0, i16* [[AA]], align 2
|
|
// CHECK28-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK28-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK28-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK28-NEXT: store i64 [[TMP0]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK28: omp.inner.for.cond:
|
|
// CHECK28-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !22
|
|
// CHECK28-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !22
|
|
// CHECK28-NEXT: [[CMP:%.*]] = icmp sle i64 [[TMP1]], [[TMP2]]
|
|
// CHECK28-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK28: omp.inner.for.body:
|
|
// CHECK28-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !22
|
|
// CHECK28-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP3]], 3
|
|
// CHECK28-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
|
|
// CHECK28-NEXT: store i64 [[ADD]], i64* [[I]], align 8, !llvm.access.group !22
|
|
// CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !22
|
|
// CHECK28-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1
|
|
// CHECK28-NEXT: store i32 [[ADD1]], i32* [[A]], align 4, !llvm.access.group !22
|
|
// CHECK28-NEXT: [[TMP5:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !22
|
|
// CHECK28-NEXT: [[CONV:%.*]] = sext i16 [[TMP5]] to i32
|
|
// CHECK28-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 1
|
|
// CHECK28-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
|
|
// CHECK28-NEXT: store i16 [[CONV3]], i16* [[AA]], align 2, !llvm.access.group !22
|
|
// CHECK28-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2
|
|
// CHECK28-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !22
|
|
// CHECK28-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP6]], 1
|
|
// CHECK28-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !22
|
|
// CHECK28-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK28: omp.body.continue:
|
|
// CHECK28-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK28: omp.inner.for.inc:
|
|
// CHECK28-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !22
|
|
// CHECK28-NEXT: [[ADD5:%.*]] = add nsw i64 [[TMP7]], 1
|
|
// CHECK28-NEXT: store i64 [[ADD5]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !22
|
|
// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]]
|
|
// CHECK28: omp.inner.for.end:
|
|
// CHECK28-NEXT: store i64 11, i64* [[I]], align 8
|
|
// CHECK28-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK28-NEXT: ret i32 [[TMP8]]
|
|
//
|
|
//
|
|
// CHECK29-LABEL: define {{[^@]+}}@_Z7get_valv
|
|
// CHECK29-SAME: () #[[ATTR0:[0-9]+]] {
|
|
// CHECK29-NEXT: entry:
|
|
// CHECK29-NEXT: ret i64 0
|
|
//
|
|
//
|
|
// CHECK29-LABEL: define {{[^@]+}}@_Z3fooi
|
|
// CHECK29-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
|
|
// CHECK29-NEXT: entry:
|
|
// CHECK29-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK29-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK29-NEXT: [[AA:%.*]] = alloca i16, align 2
|
|
// CHECK29-NEXT: [[B:%.*]] = alloca [10 x float], align 4
|
|
// CHECK29-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8
|
|
// CHECK29-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8
|
|
// CHECK29-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8
|
|
// CHECK29-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8
|
|
// CHECK29-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8
|
|
// CHECK29-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK29-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK29-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK29-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK29-NEXT: [[I:%.*]] = alloca i32, align 4
|
|
// CHECK29-NEXT: [[K:%.*]] = alloca i64, align 8
|
|
// CHECK29-NEXT: [[_TMP3:%.*]] = alloca i32, align 4
|
|
// CHECK29-NEXT: [[DOTOMP_LB4:%.*]] = alloca i32, align 4
|
|
// CHECK29-NEXT: [[DOTOMP_UB5:%.*]] = alloca i32, align 4
|
|
// CHECK29-NEXT: [[DOTOMP_IV6:%.*]] = alloca i32, align 4
|
|
// CHECK29-NEXT: [[DOTLINEAR_START:%.*]] = alloca i64, align 8
|
|
// CHECK29-NEXT: [[I7:%.*]] = alloca i32, align 4
|
|
// CHECK29-NEXT: [[K8:%.*]] = alloca i64, align 8
|
|
// CHECK29-NEXT: [[LIN:%.*]] = alloca i32, align 4
|
|
// CHECK29-NEXT: [[_TMP21:%.*]] = alloca i64, align 8
|
|
// CHECK29-NEXT: [[DOTOMP_LB22:%.*]] = alloca i64, align 8
|
|
// CHECK29-NEXT: [[DOTOMP_UB23:%.*]] = alloca i64, align 8
|
|
// CHECK29-NEXT: [[DOTOMP_IV24:%.*]] = alloca i64, align 8
|
|
// CHECK29-NEXT: [[DOTLINEAR_START25:%.*]] = alloca i32, align 4
|
|
// CHECK29-NEXT: [[DOTLINEAR_START26:%.*]] = alloca i32, align 4
|
|
// CHECK29-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8
|
|
// CHECK29-NEXT: [[IT:%.*]] = alloca i64, align 8
|
|
// CHECK29-NEXT: [[LIN28:%.*]] = alloca i32, align 4
|
|
// CHECK29-NEXT: [[A29:%.*]] = alloca i32, align 4
|
|
// CHECK29-NEXT: [[_TMP58:%.*]] = alloca i16, align 2
|
|
// CHECK29-NEXT: [[DOTOMP_LB59:%.*]] = alloca i32, align 4
|
|
// CHECK29-NEXT: [[DOTOMP_UB60:%.*]] = alloca i32, align 4
|
|
// CHECK29-NEXT: [[DOTOMP_IV61:%.*]] = alloca i32, align 4
|
|
// CHECK29-NEXT: [[IT62:%.*]] = alloca i16, align 2
|
|
// CHECK29-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
|
// CHECK29-NEXT: [[_TMP77:%.*]] = alloca i8, align 1
|
|
// CHECK29-NEXT: [[DOTOMP_LB78:%.*]] = alloca i32, align 4
|
|
// CHECK29-NEXT: [[DOTOMP_UB79:%.*]] = alloca i32, align 4
|
|
// CHECK29-NEXT: [[DOTOMP_IV80:%.*]] = alloca i32, align 4
|
|
// CHECK29-NEXT: [[IT81:%.*]] = alloca i8, align 1
|
|
// CHECK29-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK29-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK29-NEXT: store i16 0, i16* [[AA]], align 2
|
|
// CHECK29-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK29-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
|
|
// CHECK29-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave()
|
|
// CHECK29-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8
|
|
// CHECK29-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4
|
|
// CHECK29-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8
|
|
// CHECK29-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK29-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64
|
|
// CHECK29-NEXT: [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]]
|
|
// CHECK29-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8
|
|
// CHECK29-NEXT: store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8
|
|
// CHECK29-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK29-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK29-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK29-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK29-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK29: omp.inner.for.cond:
|
|
// CHECK29-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
|
|
// CHECK29-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !2
|
|
// CHECK29-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
|
|
// CHECK29-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK29: omp.inner.for.body:
|
|
// CHECK29-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
|
|
// CHECK29-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 5
|
|
// CHECK29-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]]
|
|
// CHECK29-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !2
|
|
// CHECK29-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK29: omp.body.continue:
|
|
// CHECK29-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK29: omp.inner.for.inc:
|
|
// CHECK29-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
|
|
// CHECK29-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1
|
|
// CHECK29-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
|
|
// CHECK29-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]
|
|
// CHECK29: omp.inner.for.end:
|
|
// CHECK29-NEXT: store i32 33, i32* [[I]], align 4
|
|
// CHECK29-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv()
|
|
// CHECK29-NEXT: store i64 [[CALL]], i64* [[K]], align 8
|
|
// CHECK29-NEXT: store i32 0, i32* [[DOTOMP_LB4]], align 4
|
|
// CHECK29-NEXT: store i32 8, i32* [[DOTOMP_UB5]], align 4
|
|
// CHECK29-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_LB4]], align 4
|
|
// CHECK29-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV6]], align 4
|
|
// CHECK29-NEXT: [[TMP12:%.*]] = load i64, i64* [[K]], align 8
|
|
// CHECK29-NEXT: store i64 [[TMP12]], i64* [[DOTLINEAR_START]], align 8
|
|
// CHECK29-NEXT: br label [[OMP_INNER_FOR_COND9:%.*]]
|
|
// CHECK29: omp.inner.for.cond9:
|
|
// CHECK29-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !6
|
|
// CHECK29-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB5]], align 4, !llvm.access.group !6
|
|
// CHECK29-NEXT: [[CMP10:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
|
|
// CHECK29-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY11:%.*]], label [[OMP_INNER_FOR_END19:%.*]]
|
|
// CHECK29: omp.inner.for.body11:
|
|
// CHECK29-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !6
|
|
// CHECK29-NEXT: [[MUL12:%.*]] = mul nsw i32 [[TMP15]], 1
|
|
// CHECK29-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL12]]
|
|
// CHECK29-NEXT: store i32 [[SUB]], i32* [[I7]], align 4, !llvm.access.group !6
|
|
// CHECK29-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8, !llvm.access.group !6
|
|
// CHECK29-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !6
|
|
// CHECK29-NEXT: [[MUL13:%.*]] = mul nsw i32 [[TMP17]], 3
|
|
// CHECK29-NEXT: [[CONV:%.*]] = sext i32 [[MUL13]] to i64
|
|
// CHECK29-NEXT: [[ADD14:%.*]] = add nsw i64 [[TMP16]], [[CONV]]
|
|
// CHECK29-NEXT: store i64 [[ADD14]], i64* [[K8]], align 8, !llvm.access.group !6
|
|
// CHECK29-NEXT: [[TMP18:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !6
|
|
// CHECK29-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP18]], 1
|
|
// CHECK29-NEXT: store i32 [[ADD15]], i32* [[A]], align 4, !llvm.access.group !6
|
|
// CHECK29-NEXT: br label [[OMP_BODY_CONTINUE16:%.*]]
|
|
// CHECK29: omp.body.continue16:
|
|
// CHECK29-NEXT: br label [[OMP_INNER_FOR_INC17:%.*]]
|
|
// CHECK29: omp.inner.for.inc17:
|
|
// CHECK29-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !6
|
|
// CHECK29-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP19]], 1
|
|
// CHECK29-NEXT: store i32 [[ADD18]], i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !6
|
|
// CHECK29-NEXT: br label [[OMP_INNER_FOR_COND9]], !llvm.loop [[LOOP7:![0-9]+]]
|
|
// CHECK29: omp.inner.for.end19:
|
|
// CHECK29-NEXT: store i32 1, i32* [[I7]], align 4
|
|
// CHECK29-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8
|
|
// CHECK29-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP20]], 27
|
|
// CHECK29-NEXT: store i64 [[ADD20]], i64* [[K]], align 8
|
|
// CHECK29-NEXT: store i32 12, i32* [[LIN]], align 4
|
|
// CHECK29-NEXT: store i64 0, i64* [[DOTOMP_LB22]], align 8
|
|
// CHECK29-NEXT: store i64 3, i64* [[DOTOMP_UB23]], align 8
|
|
// CHECK29-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_LB22]], align 8
|
|
// CHECK29-NEXT: store i64 [[TMP21]], i64* [[DOTOMP_IV24]], align 8
|
|
// CHECK29-NEXT: [[TMP22:%.*]] = load i32, i32* [[LIN]], align 4
|
|
// CHECK29-NEXT: store i32 [[TMP22]], i32* [[DOTLINEAR_START25]], align 4
|
|
// CHECK29-NEXT: [[TMP23:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK29-NEXT: store i32 [[TMP23]], i32* [[DOTLINEAR_START26]], align 4
|
|
// CHECK29-NEXT: [[CALL27:%.*]] = call i64 @_Z7get_valv()
|
|
// CHECK29-NEXT: store i64 [[CALL27]], i64* [[DOTLINEAR_STEP]], align 8
|
|
// CHECK29-NEXT: br label [[OMP_INNER_FOR_COND30:%.*]]
|
|
// CHECK29: omp.inner.for.cond30:
|
|
// CHECK29-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !9
|
|
// CHECK29-NEXT: [[TMP25:%.*]] = load i64, i64* [[DOTOMP_UB23]], align 8, !llvm.access.group !9
|
|
// CHECK29-NEXT: [[CMP31:%.*]] = icmp ule i64 [[TMP24]], [[TMP25]]
|
|
// CHECK29-NEXT: br i1 [[CMP31]], label [[OMP_INNER_FOR_BODY32:%.*]], label [[OMP_INNER_FOR_END49:%.*]]
|
|
// CHECK29: omp.inner.for.body32:
|
|
// CHECK29-NEXT: [[TMP26:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !9
|
|
// CHECK29-NEXT: [[MUL33:%.*]] = mul i64 [[TMP26]], 400
|
|
// CHECK29-NEXT: [[SUB34:%.*]] = sub i64 2000, [[MUL33]]
|
|
// CHECK29-NEXT: store i64 [[SUB34]], i64* [[IT]], align 8, !llvm.access.group !9
|
|
// CHECK29-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTLINEAR_START25]], align 4, !llvm.access.group !9
|
|
// CHECK29-NEXT: [[CONV35:%.*]] = sext i32 [[TMP27]] to i64
|
|
// CHECK29-NEXT: [[TMP28:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !9
|
|
// CHECK29-NEXT: [[TMP29:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !9
|
|
// CHECK29-NEXT: [[MUL36:%.*]] = mul i64 [[TMP28]], [[TMP29]]
|
|
// CHECK29-NEXT: [[ADD37:%.*]] = add i64 [[CONV35]], [[MUL36]]
|
|
// CHECK29-NEXT: [[CONV38:%.*]] = trunc i64 [[ADD37]] to i32
|
|
// CHECK29-NEXT: store i32 [[CONV38]], i32* [[LIN28]], align 4, !llvm.access.group !9
|
|
// CHECK29-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTLINEAR_START26]], align 4, !llvm.access.group !9
|
|
// CHECK29-NEXT: [[CONV39:%.*]] = sext i32 [[TMP30]] to i64
|
|
// CHECK29-NEXT: [[TMP31:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !9
|
|
// CHECK29-NEXT: [[TMP32:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !9
|
|
// CHECK29-NEXT: [[MUL40:%.*]] = mul i64 [[TMP31]], [[TMP32]]
|
|
// CHECK29-NEXT: [[ADD41:%.*]] = add i64 [[CONV39]], [[MUL40]]
|
|
// CHECK29-NEXT: [[CONV42:%.*]] = trunc i64 [[ADD41]] to i32
|
|
// CHECK29-NEXT: store i32 [[CONV42]], i32* [[A29]], align 4, !llvm.access.group !9
|
|
// CHECK29-NEXT: [[TMP33:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !9
|
|
// CHECK29-NEXT: [[CONV43:%.*]] = sext i16 [[TMP33]] to i32
|
|
// CHECK29-NEXT: [[ADD44:%.*]] = add nsw i32 [[CONV43]], 1
|
|
// CHECK29-NEXT: [[CONV45:%.*]] = trunc i32 [[ADD44]] to i16
|
|
// CHECK29-NEXT: store i16 [[CONV45]], i16* [[AA]], align 2, !llvm.access.group !9
|
|
// CHECK29-NEXT: br label [[OMP_BODY_CONTINUE46:%.*]]
|
|
// CHECK29: omp.body.continue46:
|
|
// CHECK29-NEXT: br label [[OMP_INNER_FOR_INC47:%.*]]
|
|
// CHECK29: omp.inner.for.inc47:
|
|
// CHECK29-NEXT: [[TMP34:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !9
|
|
// CHECK29-NEXT: [[ADD48:%.*]] = add i64 [[TMP34]], 1
|
|
// CHECK29-NEXT: store i64 [[ADD48]], i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !9
|
|
// CHECK29-NEXT: br label [[OMP_INNER_FOR_COND30]], !llvm.loop [[LOOP10:![0-9]+]]
|
|
// CHECK29: omp.inner.for.end49:
|
|
// CHECK29-NEXT: store i64 400, i64* [[IT]], align 8
|
|
// CHECK29-NEXT: [[TMP35:%.*]] = load i32, i32* [[DOTLINEAR_START25]], align 4
|
|
// CHECK29-NEXT: [[CONV50:%.*]] = sext i32 [[TMP35]] to i64
|
|
// CHECK29-NEXT: [[TMP36:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
|
|
// CHECK29-NEXT: [[MUL51:%.*]] = mul i64 4, [[TMP36]]
|
|
// CHECK29-NEXT: [[ADD52:%.*]] = add i64 [[CONV50]], [[MUL51]]
|
|
// CHECK29-NEXT: [[CONV53:%.*]] = trunc i64 [[ADD52]] to i32
|
|
// CHECK29-NEXT: store i32 [[CONV53]], i32* [[LIN]], align 4
|
|
// CHECK29-NEXT: [[TMP37:%.*]] = load i32, i32* [[DOTLINEAR_START26]], align 4
|
|
// CHECK29-NEXT: [[CONV54:%.*]] = sext i32 [[TMP37]] to i64
|
|
// CHECK29-NEXT: [[TMP38:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
|
|
// CHECK29-NEXT: [[MUL55:%.*]] = mul i64 4, [[TMP38]]
|
|
// CHECK29-NEXT: [[ADD56:%.*]] = add i64 [[CONV54]], [[MUL55]]
|
|
// CHECK29-NEXT: [[CONV57:%.*]] = trunc i64 [[ADD56]] to i32
|
|
// CHECK29-NEXT: store i32 [[CONV57]], i32* [[A]], align 4
|
|
// CHECK29-NEXT: store i32 0, i32* [[DOTOMP_LB59]], align 4
|
|
// CHECK29-NEXT: store i32 3, i32* [[DOTOMP_UB60]], align 4
|
|
// CHECK29-NEXT: [[TMP39:%.*]] = load i32, i32* [[DOTOMP_LB59]], align 4
|
|
// CHECK29-NEXT: store i32 [[TMP39]], i32* [[DOTOMP_IV61]], align 4
|
|
// CHECK29-NEXT: br label [[OMP_INNER_FOR_COND63:%.*]]
|
|
// CHECK29: omp.inner.for.cond63:
|
|
// CHECK29-NEXT: [[TMP40:%.*]] = load i32, i32* [[DOTOMP_IV61]], align 4, !llvm.access.group !12
|
|
// CHECK29-NEXT: [[TMP41:%.*]] = load i32, i32* [[DOTOMP_UB60]], align 4, !llvm.access.group !12
|
|
// CHECK29-NEXT: [[CMP64:%.*]] = icmp sle i32 [[TMP40]], [[TMP41]]
|
|
// CHECK29-NEXT: br i1 [[CMP64]], label [[OMP_INNER_FOR_BODY65:%.*]], label [[OMP_INNER_FOR_END76:%.*]]
|
|
// CHECK29: omp.inner.for.body65:
|
|
// CHECK29-NEXT: [[TMP42:%.*]] = load i32, i32* [[DOTOMP_IV61]], align 4, !llvm.access.group !12
|
|
// CHECK29-NEXT: [[MUL66:%.*]] = mul nsw i32 [[TMP42]], 4
|
|
// CHECK29-NEXT: [[ADD67:%.*]] = add nsw i32 6, [[MUL66]]
|
|
// CHECK29-NEXT: [[CONV68:%.*]] = trunc i32 [[ADD67]] to i16
|
|
// CHECK29-NEXT: store i16 [[CONV68]], i16* [[IT62]], align 2, !llvm.access.group !12
|
|
// CHECK29-NEXT: [[TMP43:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !12
|
|
// CHECK29-NEXT: [[ADD69:%.*]] = add nsw i32 [[TMP43]], 1
|
|
// CHECK29-NEXT: store i32 [[ADD69]], i32* [[A]], align 4, !llvm.access.group !12
|
|
// CHECK29-NEXT: [[TMP44:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !12
|
|
// CHECK29-NEXT: [[CONV70:%.*]] = sext i16 [[TMP44]] to i32
|
|
// CHECK29-NEXT: [[ADD71:%.*]] = add nsw i32 [[CONV70]], 1
|
|
// CHECK29-NEXT: [[CONV72:%.*]] = trunc i32 [[ADD71]] to i16
|
|
// CHECK29-NEXT: store i16 [[CONV72]], i16* [[AA]], align 2, !llvm.access.group !12
|
|
// CHECK29-NEXT: br label [[OMP_BODY_CONTINUE73:%.*]]
|
|
// CHECK29: omp.body.continue73:
|
|
// CHECK29-NEXT: br label [[OMP_INNER_FOR_INC74:%.*]]
|
|
// CHECK29: omp.inner.for.inc74:
|
|
// CHECK29-NEXT: [[TMP45:%.*]] = load i32, i32* [[DOTOMP_IV61]], align 4, !llvm.access.group !12
|
|
// CHECK29-NEXT: [[ADD75:%.*]] = add nsw i32 [[TMP45]], 1
|
|
// CHECK29-NEXT: store i32 [[ADD75]], i32* [[DOTOMP_IV61]], align 4, !llvm.access.group !12
|
|
// CHECK29-NEXT: br label [[OMP_INNER_FOR_COND63]], !llvm.loop [[LOOP13:![0-9]+]]
|
|
// CHECK29: omp.inner.for.end76:
|
|
// CHECK29-NEXT: store i16 22, i16* [[IT62]], align 2
|
|
// CHECK29-NEXT: [[TMP46:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK29-NEXT: store i32 [[TMP46]], i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK29-NEXT: store i32 0, i32* [[DOTOMP_LB78]], align 4
|
|
// CHECK29-NEXT: store i32 25, i32* [[DOTOMP_UB79]], align 4
|
|
// CHECK29-NEXT: [[TMP47:%.*]] = load i32, i32* [[DOTOMP_LB78]], align 4
|
|
// CHECK29-NEXT: store i32 [[TMP47]], i32* [[DOTOMP_IV80]], align 4
|
|
// CHECK29-NEXT: br label [[OMP_INNER_FOR_COND82:%.*]]
|
|
// CHECK29: omp.inner.for.cond82:
|
|
// CHECK29-NEXT: [[TMP48:%.*]] = load i32, i32* [[DOTOMP_IV80]], align 4, !llvm.access.group !15
|
|
// CHECK29-NEXT: [[TMP49:%.*]] = load i32, i32* [[DOTOMP_UB79]], align 4, !llvm.access.group !15
|
|
// CHECK29-NEXT: [[CMP83:%.*]] = icmp sle i32 [[TMP48]], [[TMP49]]
|
|
// CHECK29-NEXT: br i1 [[CMP83]], label [[OMP_INNER_FOR_BODY84:%.*]], label [[OMP_INNER_FOR_END109:%.*]]
|
|
// CHECK29: omp.inner.for.body84:
|
|
// CHECK29-NEXT: [[TMP50:%.*]] = load i32, i32* [[DOTOMP_IV80]], align 4, !llvm.access.group !15
|
|
// CHECK29-NEXT: [[MUL85:%.*]] = mul nsw i32 [[TMP50]], 1
|
|
// CHECK29-NEXT: [[SUB86:%.*]] = sub nsw i32 122, [[MUL85]]
|
|
// CHECK29-NEXT: [[CONV87:%.*]] = trunc i32 [[SUB86]] to i8
|
|
// CHECK29-NEXT: store i8 [[CONV87]], i8* [[IT81]], align 1, !llvm.access.group !15
|
|
// CHECK29-NEXT: [[TMP51:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !15
|
|
// CHECK29-NEXT: [[ADD88:%.*]] = add nsw i32 [[TMP51]], 1
|
|
// CHECK29-NEXT: store i32 [[ADD88]], i32* [[A]], align 4, !llvm.access.group !15
|
|
// CHECK29-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 2
|
|
// CHECK29-NEXT: [[TMP52:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !15
|
|
// CHECK29-NEXT: [[CONV89:%.*]] = fpext float [[TMP52]] to double
|
|
// CHECK29-NEXT: [[ADD90:%.*]] = fadd double [[CONV89]], 1.000000e+00
|
|
// CHECK29-NEXT: [[CONV91:%.*]] = fptrunc double [[ADD90]] to float
|
|
// CHECK29-NEXT: store float [[CONV91]], float* [[ARRAYIDX]], align 4, !llvm.access.group !15
|
|
// CHECK29-NEXT: [[ARRAYIDX92:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 3
|
|
// CHECK29-NEXT: [[TMP53:%.*]] = load float, float* [[ARRAYIDX92]], align 4, !llvm.access.group !15
|
|
// CHECK29-NEXT: [[CONV93:%.*]] = fpext float [[TMP53]] to double
|
|
// CHECK29-NEXT: [[ADD94:%.*]] = fadd double [[CONV93]], 1.000000e+00
|
|
// CHECK29-NEXT: [[CONV95:%.*]] = fptrunc double [[ADD94]] to float
|
|
// CHECK29-NEXT: store float [[CONV95]], float* [[ARRAYIDX92]], align 4, !llvm.access.group !15
|
|
// CHECK29-NEXT: [[ARRAYIDX96:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i64 0, i64 1
|
|
// CHECK29-NEXT: [[ARRAYIDX97:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX96]], i64 0, i64 2
|
|
// CHECK29-NEXT: [[TMP54:%.*]] = load double, double* [[ARRAYIDX97]], align 8, !llvm.access.group !15
|
|
// CHECK29-NEXT: [[ADD98:%.*]] = fadd double [[TMP54]], 1.000000e+00
|
|
// CHECK29-NEXT: store double [[ADD98]], double* [[ARRAYIDX97]], align 8, !llvm.access.group !15
|
|
// CHECK29-NEXT: [[TMP55:%.*]] = mul nsw i64 1, [[TMP4]]
|
|
// CHECK29-NEXT: [[ARRAYIDX99:%.*]] = getelementptr inbounds double, double* [[VLA1]], i64 [[TMP55]]
|
|
// CHECK29-NEXT: [[ARRAYIDX100:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX99]], i64 3
|
|
// CHECK29-NEXT: [[TMP56:%.*]] = load double, double* [[ARRAYIDX100]], align 8, !llvm.access.group !15
|
|
// CHECK29-NEXT: [[ADD101:%.*]] = fadd double [[TMP56]], 1.000000e+00
|
|
// CHECK29-NEXT: store double [[ADD101]], double* [[ARRAYIDX100]], align 8, !llvm.access.group !15
|
|
// CHECK29-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0
|
|
// CHECK29-NEXT: [[TMP57:%.*]] = load i64, i64* [[X]], align 8, !llvm.access.group !15
|
|
// CHECK29-NEXT: [[ADD102:%.*]] = add nsw i64 [[TMP57]], 1
|
|
// CHECK29-NEXT: store i64 [[ADD102]], i64* [[X]], align 8, !llvm.access.group !15
|
|
// CHECK29-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1
|
|
// CHECK29-NEXT: [[TMP58:%.*]] = load i8, i8* [[Y]], align 8, !llvm.access.group !15
|
|
// CHECK29-NEXT: [[CONV103:%.*]] = sext i8 [[TMP58]] to i32
|
|
// CHECK29-NEXT: [[ADD104:%.*]] = add nsw i32 [[CONV103]], 1
|
|
// CHECK29-NEXT: [[CONV105:%.*]] = trunc i32 [[ADD104]] to i8
|
|
// CHECK29-NEXT: store i8 [[CONV105]], i8* [[Y]], align 8, !llvm.access.group !15
|
|
// CHECK29-NEXT: br label [[OMP_BODY_CONTINUE106:%.*]]
|
|
// CHECK29: omp.body.continue106:
|
|
// CHECK29-NEXT: br label [[OMP_INNER_FOR_INC107:%.*]]
|
|
// CHECK29: omp.inner.for.inc107:
|
|
// CHECK29-NEXT: [[TMP59:%.*]] = load i32, i32* [[DOTOMP_IV80]], align 4, !llvm.access.group !15
|
|
// CHECK29-NEXT: [[ADD108:%.*]] = add nsw i32 [[TMP59]], 1
|
|
// CHECK29-NEXT: store i32 [[ADD108]], i32* [[DOTOMP_IV80]], align 4, !llvm.access.group !15
|
|
// CHECK29-NEXT: br label [[OMP_INNER_FOR_COND82]], !llvm.loop [[LOOP16:![0-9]+]]
|
|
// CHECK29: omp.inner.for.end109:
|
|
// CHECK29-NEXT: store i8 96, i8* [[IT81]], align 1
|
|
// CHECK29-NEXT: [[TMP60:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK29-NEXT: [[TMP61:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
|
|
// CHECK29-NEXT: call void @llvm.stackrestore(i8* [[TMP61]])
|
|
// CHECK29-NEXT: ret i32 [[TMP60]]
|
|
//
|
|
//
|
|
// CHECK29-LABEL: define {{[^@]+}}@_Z3bari
|
|
// CHECK29-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
|
|
// CHECK29-NEXT: entry:
|
|
// CHECK29-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK29-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK29-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8
|
|
// CHECK29-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK29-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK29-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK29-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]])
|
|
// CHECK29-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK29-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
|
|
// CHECK29-NEXT: store i32 [[ADD]], i32* [[A]], align 4
|
|
// CHECK29-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK29-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]])
|
|
// CHECK29-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK29-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
|
|
// CHECK29-NEXT: store i32 [[ADD2]], i32* [[A]], align 4
|
|
// CHECK29-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK29-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]])
|
|
// CHECK29-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK29-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
|
|
// CHECK29-NEXT: store i32 [[ADD4]], i32* [[A]], align 4
|
|
// CHECK29-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK29-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]])
|
|
// CHECK29-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK29-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
|
|
// CHECK29-NEXT: store i32 [[ADD6]], i32* [[A]], align 4
|
|
// CHECK29-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK29-NEXT: ret i32 [[TMP8]]
|
|
//
|
|
//
|
|
// CHECK29-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
|
|
// CHECK29-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 {
|
|
// CHECK29-NEXT: entry:
|
|
// CHECK29-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
|
|
// CHECK29-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK29-NEXT: [[B:%.*]] = alloca i32, align 4
|
|
// CHECK29-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8
|
|
// CHECK29-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8
|
|
// CHECK29-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
|
|
// CHECK29-NEXT: [[TMP:%.*]] = alloca i64, align 8
|
|
// CHECK29-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
|
|
// CHECK29-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
|
|
// CHECK29-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
|
|
// CHECK29-NEXT: [[IT:%.*]] = alloca i64, align 8
|
|
// CHECK29-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK29-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK29-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK29-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK29-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
|
|
// CHECK29-NEXT: store i32 [[ADD]], i32* [[B]], align 4
|
|
// CHECK29-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK29-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
|
|
// CHECK29-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave()
|
|
// CHECK29-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8
|
|
// CHECK29-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]]
|
|
// CHECK29-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2
|
|
// CHECK29-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8
|
|
// CHECK29-NEXT: [[TMP5:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK29-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 60
|
|
// CHECK29-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8
|
|
// CHECK29-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
|
|
// CHECK29-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK29-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK29-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK29-NEXT: store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK29-NEXT: [[TMP7:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
|
|
// CHECK29-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP7]] to i1
|
|
// CHECK29-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
|
|
// CHECK29: omp_if.then:
|
|
// CHECK29-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK29: omp.inner.for.cond:
|
|
// CHECK29-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18
|
|
// CHECK29-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !18
|
|
// CHECK29-NEXT: [[CMP2:%.*]] = icmp ule i64 [[TMP8]], [[TMP9]]
|
|
// CHECK29-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK29: omp.inner.for.body:
|
|
// CHECK29-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18
|
|
// CHECK29-NEXT: [[MUL:%.*]] = mul i64 [[TMP10]], 400
|
|
// CHECK29-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]
|
|
// CHECK29-NEXT: store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !18
|
|
// CHECK29-NEXT: [[TMP11:%.*]] = load i32, i32* [[B]], align 4, !llvm.access.group !18
|
|
// CHECK29-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP11]] to double
|
|
// CHECK29-NEXT: [[ADD3:%.*]] = fadd double [[CONV]], 1.500000e+00
|
|
// CHECK29-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
|
|
// CHECK29-NEXT: store double [[ADD3]], double* [[A]], align 8, !nontemporal !19, !llvm.access.group !18
|
|
// CHECK29-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
|
|
// CHECK29-NEXT: [[TMP12:%.*]] = load double, double* [[A4]], align 8, !nontemporal !19, !llvm.access.group !18
|
|
// CHECK29-NEXT: [[INC:%.*]] = fadd double [[TMP12]], 1.000000e+00
|
|
// CHECK29-NEXT: store double [[INC]], double* [[A4]], align 8, !nontemporal !19, !llvm.access.group !18
|
|
// CHECK29-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16
|
|
// CHECK29-NEXT: [[TMP13:%.*]] = mul nsw i64 1, [[TMP2]]
|
|
// CHECK29-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP13]]
|
|
// CHECK29-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
|
|
// CHECK29-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2, !llvm.access.group !18
|
|
// CHECK29-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK29: omp.body.continue:
|
|
// CHECK29-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK29: omp.inner.for.inc:
|
|
// CHECK29-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18
|
|
// CHECK29-NEXT: [[ADD7:%.*]] = add i64 [[TMP14]], 1
|
|
// CHECK29-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18
|
|
// CHECK29-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]]
|
|
// CHECK29: omp.inner.for.end:
|
|
// CHECK29-NEXT: br label [[OMP_IF_END:%.*]]
|
|
// CHECK29: omp_if.else:
|
|
// CHECK29-NEXT: br label [[OMP_INNER_FOR_COND8:%.*]]
|
|
// CHECK29: omp.inner.for.cond8:
|
|
// CHECK29-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK29-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK29-NEXT: [[CMP9:%.*]] = icmp ule i64 [[TMP15]], [[TMP16]]
|
|
// CHECK29-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY10:%.*]], label [[OMP_INNER_FOR_END24:%.*]]
|
|
// CHECK29: omp.inner.for.body10:
|
|
// CHECK29-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK29-NEXT: [[MUL11:%.*]] = mul i64 [[TMP17]], 400
|
|
// CHECK29-NEXT: [[SUB12:%.*]] = sub i64 2000, [[MUL11]]
|
|
// CHECK29-NEXT: store i64 [[SUB12]], i64* [[IT]], align 8
|
|
// CHECK29-NEXT: [[TMP18:%.*]] = load i32, i32* [[B]], align 4
|
|
// CHECK29-NEXT: [[CONV13:%.*]] = sitofp i32 [[TMP18]] to double
|
|
// CHECK29-NEXT: [[ADD14:%.*]] = fadd double [[CONV13]], 1.500000e+00
|
|
// CHECK29-NEXT: [[A15:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
|
|
// CHECK29-NEXT: store double [[ADD14]], double* [[A15]], align 8
|
|
// CHECK29-NEXT: [[A16:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
|
|
// CHECK29-NEXT: [[TMP19:%.*]] = load double, double* [[A16]], align 8
|
|
// CHECK29-NEXT: [[INC17:%.*]] = fadd double [[TMP19]], 1.000000e+00
|
|
// CHECK29-NEXT: store double [[INC17]], double* [[A16]], align 8
|
|
// CHECK29-NEXT: [[CONV18:%.*]] = fptosi double [[INC17]] to i16
|
|
// CHECK29-NEXT: [[TMP20:%.*]] = mul nsw i64 1, [[TMP2]]
|
|
// CHECK29-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP20]]
|
|
// CHECK29-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX19]], i64 1
|
|
// CHECK29-NEXT: store i16 [[CONV18]], i16* [[ARRAYIDX20]], align 2
|
|
// CHECK29-NEXT: br label [[OMP_BODY_CONTINUE21:%.*]]
|
|
// CHECK29: omp.body.continue21:
|
|
// CHECK29-NEXT: br label [[OMP_INNER_FOR_INC22:%.*]]
|
|
// CHECK29: omp.inner.for.inc22:
|
|
// CHECK29-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK29-NEXT: [[ADD23:%.*]] = add i64 [[TMP21]], 1
|
|
// CHECK29-NEXT: store i64 [[ADD23]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK29-NEXT: br label [[OMP_INNER_FOR_COND8]], !llvm.loop [[LOOP22:![0-9]+]]
|
|
// CHECK29: omp.inner.for.end24:
|
|
// CHECK29-NEXT: br label [[OMP_IF_END]]
|
|
// CHECK29: omp_if.end:
|
|
// CHECK29-NEXT: store i64 400, i64* [[IT]], align 8
|
|
// CHECK29-NEXT: [[TMP22:%.*]] = mul nsw i64 1, [[TMP2]]
|
|
// CHECK29-NEXT: [[ARRAYIDX25:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP22]]
|
|
// CHECK29-NEXT: [[ARRAYIDX26:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX25]], i64 1
|
|
// CHECK29-NEXT: [[TMP23:%.*]] = load i16, i16* [[ARRAYIDX26]], align 2
|
|
// CHECK29-NEXT: [[CONV27:%.*]] = sext i16 [[TMP23]] to i32
|
|
// CHECK29-NEXT: [[TMP24:%.*]] = load i32, i32* [[B]], align 4
|
|
// CHECK29-NEXT: [[ADD28:%.*]] = add nsw i32 [[CONV27]], [[TMP24]]
|
|
// CHECK29-NEXT: [[TMP25:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
|
|
// CHECK29-NEXT: call void @llvm.stackrestore(i8* [[TMP25]])
|
|
// CHECK29-NEXT: ret i32 [[ADD28]]
|
|
//
|
|
//
|
|
// CHECK29-LABEL: define {{[^@]+}}@_ZL7fstatici
|
|
// CHECK29-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
|
|
// CHECK29-NEXT: entry:
|
|
// CHECK29-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK29-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK29-NEXT: [[AA:%.*]] = alloca i16, align 2
|
|
// CHECK29-NEXT: [[AAA:%.*]] = alloca i8, align 1
|
|
// CHECK29-NEXT: [[B:%.*]] = alloca [10 x i32], align 4
|
|
// CHECK29-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK29-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK29-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK29-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK29-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK29-NEXT: store i16 0, i16* [[AA]], align 2
|
|
// CHECK29-NEXT: store i8 0, i8* [[AAA]], align 1
|
|
// CHECK29-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK29-NEXT: store i32 429496720, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK29-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK29-NEXT: ret i32 [[TMP0]]
|
|
//
|
|
//
|
|
// CHECK29-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
|
|
// CHECK29-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat {
|
|
// CHECK29-NEXT: entry:
|
|
// CHECK29-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK29-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK29-NEXT: [[AA:%.*]] = alloca i16, align 2
|
|
// CHECK29-NEXT: [[B:%.*]] = alloca [10 x i32], align 4
|
|
// CHECK29-NEXT: [[TMP:%.*]] = alloca i64, align 8
|
|
// CHECK29-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
|
|
// CHECK29-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
|
|
// CHECK29-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
|
|
// CHECK29-NEXT: [[I:%.*]] = alloca i64, align 8
|
|
// CHECK29-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK29-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK29-NEXT: store i16 0, i16* [[AA]], align 2
|
|
// CHECK29-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK29-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK29-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK29-NEXT: store i64 [[TMP0]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK29-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK29: omp.inner.for.cond:
|
|
// CHECK29-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !24
|
|
// CHECK29-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !24
|
|
// CHECK29-NEXT: [[CMP:%.*]] = icmp sle i64 [[TMP1]], [[TMP2]]
|
|
// CHECK29-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK29: omp.inner.for.body:
|
|
// CHECK29-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !24
|
|
// CHECK29-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP3]], 3
|
|
// CHECK29-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
|
|
// CHECK29-NEXT: store i64 [[ADD]], i64* [[I]], align 8, !llvm.access.group !24
|
|
// CHECK29-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !24
|
|
// CHECK29-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1
|
|
// CHECK29-NEXT: store i32 [[ADD1]], i32* [[A]], align 4, !llvm.access.group !24
|
|
// CHECK29-NEXT: [[TMP5:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !24
|
|
// CHECK29-NEXT: [[CONV:%.*]] = sext i16 [[TMP5]] to i32
|
|
// CHECK29-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 1
|
|
// CHECK29-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
|
|
// CHECK29-NEXT: store i16 [[CONV3]], i16* [[AA]], align 2, !llvm.access.group !24
|
|
// CHECK29-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2
|
|
// CHECK29-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !24
|
|
// CHECK29-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP6]], 1
|
|
// CHECK29-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !24
|
|
// CHECK29-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK29: omp.body.continue:
|
|
// CHECK29-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK29: omp.inner.for.inc:
|
|
// CHECK29-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !24
|
|
// CHECK29-NEXT: [[ADD5:%.*]] = add nsw i64 [[TMP7]], 1
|
|
// CHECK29-NEXT: store i64 [[ADD5]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !24
|
|
// CHECK29-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]]
|
|
// CHECK29: omp.inner.for.end:
|
|
// CHECK29-NEXT: store i64 11, i64* [[I]], align 8
|
|
// CHECK29-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK29-NEXT: ret i32 [[TMP8]]
|
|
//
|
|
//
|
|
// CHECK30-LABEL: define {{[^@]+}}@_Z7get_valv
|
|
// CHECK30-SAME: () #[[ATTR0:[0-9]+]] {
|
|
// CHECK30-NEXT: entry:
|
|
// CHECK30-NEXT: ret i64 0
|
|
//
|
|
//
|
|
// CHECK30-LABEL: define {{[^@]+}}@_Z3fooi
|
|
// CHECK30-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
|
|
// CHECK30-NEXT: entry:
|
|
// CHECK30-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK30-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK30-NEXT: [[AA:%.*]] = alloca i16, align 2
|
|
// CHECK30-NEXT: [[B:%.*]] = alloca [10 x float], align 4
|
|
// CHECK30-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8
|
|
// CHECK30-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8
|
|
// CHECK30-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8
|
|
// CHECK30-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8
|
|
// CHECK30-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8
|
|
// CHECK30-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK30-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK30-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK30-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK30-NEXT: [[I:%.*]] = alloca i32, align 4
|
|
// CHECK30-NEXT: [[K:%.*]] = alloca i64, align 8
|
|
// CHECK30-NEXT: [[_TMP3:%.*]] = alloca i32, align 4
|
|
// CHECK30-NEXT: [[DOTOMP_LB4:%.*]] = alloca i32, align 4
|
|
// CHECK30-NEXT: [[DOTOMP_UB5:%.*]] = alloca i32, align 4
|
|
// CHECK30-NEXT: [[DOTOMP_IV6:%.*]] = alloca i32, align 4
|
|
// CHECK30-NEXT: [[DOTLINEAR_START:%.*]] = alloca i64, align 8
|
|
// CHECK30-NEXT: [[I7:%.*]] = alloca i32, align 4
|
|
// CHECK30-NEXT: [[K8:%.*]] = alloca i64, align 8
|
|
// CHECK30-NEXT: [[LIN:%.*]] = alloca i32, align 4
|
|
// CHECK30-NEXT: [[_TMP21:%.*]] = alloca i64, align 8
|
|
// CHECK30-NEXT: [[DOTOMP_LB22:%.*]] = alloca i64, align 8
|
|
// CHECK30-NEXT: [[DOTOMP_UB23:%.*]] = alloca i64, align 8
|
|
// CHECK30-NEXT: [[DOTOMP_IV24:%.*]] = alloca i64, align 8
|
|
// CHECK30-NEXT: [[DOTLINEAR_START25:%.*]] = alloca i32, align 4
|
|
// CHECK30-NEXT: [[DOTLINEAR_START26:%.*]] = alloca i32, align 4
|
|
// CHECK30-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8
|
|
// CHECK30-NEXT: [[IT:%.*]] = alloca i64, align 8
|
|
// CHECK30-NEXT: [[LIN28:%.*]] = alloca i32, align 4
|
|
// CHECK30-NEXT: [[A29:%.*]] = alloca i32, align 4
|
|
// CHECK30-NEXT: [[_TMP58:%.*]] = alloca i16, align 2
|
|
// CHECK30-NEXT: [[DOTOMP_LB59:%.*]] = alloca i32, align 4
|
|
// CHECK30-NEXT: [[DOTOMP_UB60:%.*]] = alloca i32, align 4
|
|
// CHECK30-NEXT: [[DOTOMP_IV61:%.*]] = alloca i32, align 4
|
|
// CHECK30-NEXT: [[IT62:%.*]] = alloca i16, align 2
|
|
// CHECK30-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
|
// CHECK30-NEXT: [[_TMP77:%.*]] = alloca i8, align 1
|
|
// CHECK30-NEXT: [[DOTOMP_LB78:%.*]] = alloca i32, align 4
|
|
// CHECK30-NEXT: [[DOTOMP_UB79:%.*]] = alloca i32, align 4
|
|
// CHECK30-NEXT: [[DOTOMP_IV80:%.*]] = alloca i32, align 4
|
|
// CHECK30-NEXT: [[IT81:%.*]] = alloca i8, align 1
|
|
// CHECK30-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK30-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK30-NEXT: store i16 0, i16* [[AA]], align 2
|
|
// CHECK30-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK30-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
|
|
// CHECK30-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave()
|
|
// CHECK30-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8
|
|
// CHECK30-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4
|
|
// CHECK30-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8
|
|
// CHECK30-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK30-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64
|
|
// CHECK30-NEXT: [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]]
|
|
// CHECK30-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8
|
|
// CHECK30-NEXT: store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8
|
|
// CHECK30-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK30-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK30-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK30-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK30-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK30: omp.inner.for.cond:
|
|
// CHECK30-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
|
|
// CHECK30-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !2
|
|
// CHECK30-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
|
|
// CHECK30-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK30: omp.inner.for.body:
|
|
// CHECK30-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
|
|
// CHECK30-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 5
|
|
// CHECK30-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]]
|
|
// CHECK30-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !2
|
|
// CHECK30-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK30: omp.body.continue:
|
|
// CHECK30-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK30: omp.inner.for.inc:
|
|
// CHECK30-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
|
|
// CHECK30-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1
|
|
// CHECK30-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
|
|
// CHECK30-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]
|
|
// CHECK30: omp.inner.for.end:
|
|
// CHECK30-NEXT: store i32 33, i32* [[I]], align 4
|
|
// CHECK30-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv()
|
|
// CHECK30-NEXT: store i64 [[CALL]], i64* [[K]], align 8
|
|
// CHECK30-NEXT: store i32 0, i32* [[DOTOMP_LB4]], align 4
|
|
// CHECK30-NEXT: store i32 8, i32* [[DOTOMP_UB5]], align 4
|
|
// CHECK30-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_LB4]], align 4
|
|
// CHECK30-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV6]], align 4
|
|
// CHECK30-NEXT: [[TMP12:%.*]] = load i64, i64* [[K]], align 8
|
|
// CHECK30-NEXT: store i64 [[TMP12]], i64* [[DOTLINEAR_START]], align 8
|
|
// CHECK30-NEXT: br label [[OMP_INNER_FOR_COND9:%.*]]
|
|
// CHECK30: omp.inner.for.cond9:
|
|
// CHECK30-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !6
|
|
// CHECK30-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB5]], align 4, !llvm.access.group !6
|
|
// CHECK30-NEXT: [[CMP10:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
|
|
// CHECK30-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY11:%.*]], label [[OMP_INNER_FOR_END19:%.*]]
|
|
// CHECK30: omp.inner.for.body11:
|
|
// CHECK30-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !6
|
|
// CHECK30-NEXT: [[MUL12:%.*]] = mul nsw i32 [[TMP15]], 1
|
|
// CHECK30-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL12]]
|
|
// CHECK30-NEXT: store i32 [[SUB]], i32* [[I7]], align 4, !llvm.access.group !6
|
|
// CHECK30-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8, !llvm.access.group !6
|
|
// CHECK30-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !6
|
|
// CHECK30-NEXT: [[MUL13:%.*]] = mul nsw i32 [[TMP17]], 3
|
|
// CHECK30-NEXT: [[CONV:%.*]] = sext i32 [[MUL13]] to i64
|
|
// CHECK30-NEXT: [[ADD14:%.*]] = add nsw i64 [[TMP16]], [[CONV]]
|
|
// CHECK30-NEXT: store i64 [[ADD14]], i64* [[K8]], align 8, !llvm.access.group !6
|
|
// CHECK30-NEXT: [[TMP18:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !6
|
|
// CHECK30-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP18]], 1
|
|
// CHECK30-NEXT: store i32 [[ADD15]], i32* [[A]], align 4, !llvm.access.group !6
|
|
// CHECK30-NEXT: br label [[OMP_BODY_CONTINUE16:%.*]]
|
|
// CHECK30: omp.body.continue16:
|
|
// CHECK30-NEXT: br label [[OMP_INNER_FOR_INC17:%.*]]
|
|
// CHECK30: omp.inner.for.inc17:
|
|
// CHECK30-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !6
|
|
// CHECK30-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP19]], 1
|
|
// CHECK30-NEXT: store i32 [[ADD18]], i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !6
|
|
// CHECK30-NEXT: br label [[OMP_INNER_FOR_COND9]], !llvm.loop [[LOOP7:![0-9]+]]
|
|
// CHECK30: omp.inner.for.end19:
|
|
// CHECK30-NEXT: store i32 1, i32* [[I7]], align 4
|
|
// CHECK30-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8
|
|
// CHECK30-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP20]], 27
|
|
// CHECK30-NEXT: store i64 [[ADD20]], i64* [[K]], align 8
|
|
// CHECK30-NEXT: store i32 12, i32* [[LIN]], align 4
|
|
// CHECK30-NEXT: store i64 0, i64* [[DOTOMP_LB22]], align 8
|
|
// CHECK30-NEXT: store i64 3, i64* [[DOTOMP_UB23]], align 8
|
|
// CHECK30-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_LB22]], align 8
|
|
// CHECK30-NEXT: store i64 [[TMP21]], i64* [[DOTOMP_IV24]], align 8
|
|
// CHECK30-NEXT: [[TMP22:%.*]] = load i32, i32* [[LIN]], align 4
|
|
// CHECK30-NEXT: store i32 [[TMP22]], i32* [[DOTLINEAR_START25]], align 4
|
|
// CHECK30-NEXT: [[TMP23:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK30-NEXT: store i32 [[TMP23]], i32* [[DOTLINEAR_START26]], align 4
|
|
// CHECK30-NEXT: [[CALL27:%.*]] = call i64 @_Z7get_valv()
|
|
// CHECK30-NEXT: store i64 [[CALL27]], i64* [[DOTLINEAR_STEP]], align 8
|
|
// CHECK30-NEXT: br label [[OMP_INNER_FOR_COND30:%.*]]
|
|
// CHECK30: omp.inner.for.cond30:
|
|
// CHECK30-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !9
|
|
// CHECK30-NEXT: [[TMP25:%.*]] = load i64, i64* [[DOTOMP_UB23]], align 8, !llvm.access.group !9
|
|
// CHECK30-NEXT: [[CMP31:%.*]] = icmp ule i64 [[TMP24]], [[TMP25]]
|
|
// CHECK30-NEXT: br i1 [[CMP31]], label [[OMP_INNER_FOR_BODY32:%.*]], label [[OMP_INNER_FOR_END49:%.*]]
|
|
// CHECK30: omp.inner.for.body32:
|
|
// CHECK30-NEXT: [[TMP26:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !9
|
|
// CHECK30-NEXT: [[MUL33:%.*]] = mul i64 [[TMP26]], 400
|
|
// CHECK30-NEXT: [[SUB34:%.*]] = sub i64 2000, [[MUL33]]
|
|
// CHECK30-NEXT: store i64 [[SUB34]], i64* [[IT]], align 8, !llvm.access.group !9
|
|
// CHECK30-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTLINEAR_START25]], align 4, !llvm.access.group !9
|
|
// CHECK30-NEXT: [[CONV35:%.*]] = sext i32 [[TMP27]] to i64
|
|
// CHECK30-NEXT: [[TMP28:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !9
|
|
// CHECK30-NEXT: [[TMP29:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !9
|
|
// CHECK30-NEXT: [[MUL36:%.*]] = mul i64 [[TMP28]], [[TMP29]]
|
|
// CHECK30-NEXT: [[ADD37:%.*]] = add i64 [[CONV35]], [[MUL36]]
|
|
// CHECK30-NEXT: [[CONV38:%.*]] = trunc i64 [[ADD37]] to i32
|
|
// CHECK30-NEXT: store i32 [[CONV38]], i32* [[LIN28]], align 4, !llvm.access.group !9
|
|
// CHECK30-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTLINEAR_START26]], align 4, !llvm.access.group !9
|
|
// CHECK30-NEXT: [[CONV39:%.*]] = sext i32 [[TMP30]] to i64
|
|
// CHECK30-NEXT: [[TMP31:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !9
|
|
// CHECK30-NEXT: [[TMP32:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !9
|
|
// CHECK30-NEXT: [[MUL40:%.*]] = mul i64 [[TMP31]], [[TMP32]]
|
|
// CHECK30-NEXT: [[ADD41:%.*]] = add i64 [[CONV39]], [[MUL40]]
|
|
// CHECK30-NEXT: [[CONV42:%.*]] = trunc i64 [[ADD41]] to i32
|
|
// CHECK30-NEXT: store i32 [[CONV42]], i32* [[A29]], align 4, !llvm.access.group !9
|
|
// CHECK30-NEXT: [[TMP33:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !9
|
|
// CHECK30-NEXT: [[CONV43:%.*]] = sext i16 [[TMP33]] to i32
|
|
// CHECK30-NEXT: [[ADD44:%.*]] = add nsw i32 [[CONV43]], 1
|
|
// CHECK30-NEXT: [[CONV45:%.*]] = trunc i32 [[ADD44]] to i16
|
|
// CHECK30-NEXT: store i16 [[CONV45]], i16* [[AA]], align 2, !llvm.access.group !9
|
|
// CHECK30-NEXT: br label [[OMP_BODY_CONTINUE46:%.*]]
|
|
// CHECK30: omp.body.continue46:
|
|
// CHECK30-NEXT: br label [[OMP_INNER_FOR_INC47:%.*]]
|
|
// CHECK30: omp.inner.for.inc47:
|
|
// CHECK30-NEXT: [[TMP34:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !9
|
|
// CHECK30-NEXT: [[ADD48:%.*]] = add i64 [[TMP34]], 1
|
|
// CHECK30-NEXT: store i64 [[ADD48]], i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !9
|
|
// CHECK30-NEXT: br label [[OMP_INNER_FOR_COND30]], !llvm.loop [[LOOP10:![0-9]+]]
|
|
// CHECK30: omp.inner.for.end49:
|
|
// CHECK30-NEXT: store i64 400, i64* [[IT]], align 8
|
|
// CHECK30-NEXT: [[TMP35:%.*]] = load i32, i32* [[DOTLINEAR_START25]], align 4
|
|
// CHECK30-NEXT: [[CONV50:%.*]] = sext i32 [[TMP35]] to i64
|
|
// CHECK30-NEXT: [[TMP36:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
|
|
// CHECK30-NEXT: [[MUL51:%.*]] = mul i64 4, [[TMP36]]
|
|
// CHECK30-NEXT: [[ADD52:%.*]] = add i64 [[CONV50]], [[MUL51]]
|
|
// CHECK30-NEXT: [[CONV53:%.*]] = trunc i64 [[ADD52]] to i32
|
|
// CHECK30-NEXT: store i32 [[CONV53]], i32* [[LIN]], align 4
|
|
// CHECK30-NEXT: [[TMP37:%.*]] = load i32, i32* [[DOTLINEAR_START26]], align 4
|
|
// CHECK30-NEXT: [[CONV54:%.*]] = sext i32 [[TMP37]] to i64
|
|
// CHECK30-NEXT: [[TMP38:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
|
|
// CHECK30-NEXT: [[MUL55:%.*]] = mul i64 4, [[TMP38]]
|
|
// CHECK30-NEXT: [[ADD56:%.*]] = add i64 [[CONV54]], [[MUL55]]
|
|
// CHECK30-NEXT: [[CONV57:%.*]] = trunc i64 [[ADD56]] to i32
|
|
// CHECK30-NEXT: store i32 [[CONV57]], i32* [[A]], align 4
|
|
// CHECK30-NEXT: store i32 0, i32* [[DOTOMP_LB59]], align 4
|
|
// CHECK30-NEXT: store i32 3, i32* [[DOTOMP_UB60]], align 4
|
|
// CHECK30-NEXT: [[TMP39:%.*]] = load i32, i32* [[DOTOMP_LB59]], align 4
|
|
// CHECK30-NEXT: store i32 [[TMP39]], i32* [[DOTOMP_IV61]], align 4
|
|
// CHECK30-NEXT: br label [[OMP_INNER_FOR_COND63:%.*]]
|
|
// CHECK30: omp.inner.for.cond63:
|
|
// CHECK30-NEXT: [[TMP40:%.*]] = load i32, i32* [[DOTOMP_IV61]], align 4, !llvm.access.group !12
|
|
// CHECK30-NEXT: [[TMP41:%.*]] = load i32, i32* [[DOTOMP_UB60]], align 4, !llvm.access.group !12
|
|
// CHECK30-NEXT: [[CMP64:%.*]] = icmp sle i32 [[TMP40]], [[TMP41]]
|
|
// CHECK30-NEXT: br i1 [[CMP64]], label [[OMP_INNER_FOR_BODY65:%.*]], label [[OMP_INNER_FOR_END76:%.*]]
|
|
// CHECK30: omp.inner.for.body65:
|
|
// CHECK30-NEXT: [[TMP42:%.*]] = load i32, i32* [[DOTOMP_IV61]], align 4, !llvm.access.group !12
|
|
// CHECK30-NEXT: [[MUL66:%.*]] = mul nsw i32 [[TMP42]], 4
|
|
// CHECK30-NEXT: [[ADD67:%.*]] = add nsw i32 6, [[MUL66]]
|
|
// CHECK30-NEXT: [[CONV68:%.*]] = trunc i32 [[ADD67]] to i16
|
|
// CHECK30-NEXT: store i16 [[CONV68]], i16* [[IT62]], align 2, !llvm.access.group !12
|
|
// CHECK30-NEXT: [[TMP43:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !12
|
|
// CHECK30-NEXT: [[ADD69:%.*]] = add nsw i32 [[TMP43]], 1
|
|
// CHECK30-NEXT: store i32 [[ADD69]], i32* [[A]], align 4, !llvm.access.group !12
|
|
// CHECK30-NEXT: [[TMP44:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !12
|
|
// CHECK30-NEXT: [[CONV70:%.*]] = sext i16 [[TMP44]] to i32
|
|
// CHECK30-NEXT: [[ADD71:%.*]] = add nsw i32 [[CONV70]], 1
|
|
// CHECK30-NEXT: [[CONV72:%.*]] = trunc i32 [[ADD71]] to i16
|
|
// CHECK30-NEXT: store i16 [[CONV72]], i16* [[AA]], align 2, !llvm.access.group !12
|
|
// CHECK30-NEXT: br label [[OMP_BODY_CONTINUE73:%.*]]
|
|
// CHECK30: omp.body.continue73:
|
|
// CHECK30-NEXT: br label [[OMP_INNER_FOR_INC74:%.*]]
|
|
// CHECK30: omp.inner.for.inc74:
|
|
// CHECK30-NEXT: [[TMP45:%.*]] = load i32, i32* [[DOTOMP_IV61]], align 4, !llvm.access.group !12
|
|
// CHECK30-NEXT: [[ADD75:%.*]] = add nsw i32 [[TMP45]], 1
|
|
// CHECK30-NEXT: store i32 [[ADD75]], i32* [[DOTOMP_IV61]], align 4, !llvm.access.group !12
|
|
// CHECK30-NEXT: br label [[OMP_INNER_FOR_COND63]], !llvm.loop [[LOOP13:![0-9]+]]
|
|
// CHECK30: omp.inner.for.end76:
|
|
// CHECK30-NEXT: store i16 22, i16* [[IT62]], align 2
|
|
// CHECK30-NEXT: [[TMP46:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK30-NEXT: store i32 [[TMP46]], i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK30-NEXT: store i32 0, i32* [[DOTOMP_LB78]], align 4
|
|
// CHECK30-NEXT: store i32 25, i32* [[DOTOMP_UB79]], align 4
|
|
// CHECK30-NEXT: [[TMP47:%.*]] = load i32, i32* [[DOTOMP_LB78]], align 4
|
|
// CHECK30-NEXT: store i32 [[TMP47]], i32* [[DOTOMP_IV80]], align 4
|
|
// CHECK30-NEXT: br label [[OMP_INNER_FOR_COND82:%.*]]
|
|
// CHECK30: omp.inner.for.cond82:
|
|
// CHECK30-NEXT: [[TMP48:%.*]] = load i32, i32* [[DOTOMP_IV80]], align 4, !llvm.access.group !15
|
|
// CHECK30-NEXT: [[TMP49:%.*]] = load i32, i32* [[DOTOMP_UB79]], align 4, !llvm.access.group !15
|
|
// CHECK30-NEXT: [[CMP83:%.*]] = icmp sle i32 [[TMP48]], [[TMP49]]
|
|
// CHECK30-NEXT: br i1 [[CMP83]], label [[OMP_INNER_FOR_BODY84:%.*]], label [[OMP_INNER_FOR_END109:%.*]]
|
|
// CHECK30: omp.inner.for.body84:
|
|
// CHECK30-NEXT: [[TMP50:%.*]] = load i32, i32* [[DOTOMP_IV80]], align 4, !llvm.access.group !15
|
|
// CHECK30-NEXT: [[MUL85:%.*]] = mul nsw i32 [[TMP50]], 1
|
|
// CHECK30-NEXT: [[SUB86:%.*]] = sub nsw i32 122, [[MUL85]]
|
|
// CHECK30-NEXT: [[CONV87:%.*]] = trunc i32 [[SUB86]] to i8
|
|
// CHECK30-NEXT: store i8 [[CONV87]], i8* [[IT81]], align 1, !llvm.access.group !15
|
|
// CHECK30-NEXT: [[TMP51:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !15
|
|
// CHECK30-NEXT: [[ADD88:%.*]] = add nsw i32 [[TMP51]], 1
|
|
// CHECK30-NEXT: store i32 [[ADD88]], i32* [[A]], align 4, !llvm.access.group !15
|
|
// CHECK30-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 2
|
|
// CHECK30-NEXT: [[TMP52:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !15
|
|
// CHECK30-NEXT: [[CONV89:%.*]] = fpext float [[TMP52]] to double
|
|
// CHECK30-NEXT: [[ADD90:%.*]] = fadd double [[CONV89]], 1.000000e+00
|
|
// CHECK30-NEXT: [[CONV91:%.*]] = fptrunc double [[ADD90]] to float
|
|
// CHECK30-NEXT: store float [[CONV91]], float* [[ARRAYIDX]], align 4, !llvm.access.group !15
|
|
// CHECK30-NEXT: [[ARRAYIDX92:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 3
|
|
// CHECK30-NEXT: [[TMP53:%.*]] = load float, float* [[ARRAYIDX92]], align 4, !llvm.access.group !15
|
|
// CHECK30-NEXT: [[CONV93:%.*]] = fpext float [[TMP53]] to double
|
|
// CHECK30-NEXT: [[ADD94:%.*]] = fadd double [[CONV93]], 1.000000e+00
|
|
// CHECK30-NEXT: [[CONV95:%.*]] = fptrunc double [[ADD94]] to float
|
|
// CHECK30-NEXT: store float [[CONV95]], float* [[ARRAYIDX92]], align 4, !llvm.access.group !15
|
|
// CHECK30-NEXT: [[ARRAYIDX96:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i64 0, i64 1
|
|
// CHECK30-NEXT: [[ARRAYIDX97:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX96]], i64 0, i64 2
|
|
// CHECK30-NEXT: [[TMP54:%.*]] = load double, double* [[ARRAYIDX97]], align 8, !llvm.access.group !15
|
|
// CHECK30-NEXT: [[ADD98:%.*]] = fadd double [[TMP54]], 1.000000e+00
|
|
// CHECK30-NEXT: store double [[ADD98]], double* [[ARRAYIDX97]], align 8, !llvm.access.group !15
|
|
// CHECK30-NEXT: [[TMP55:%.*]] = mul nsw i64 1, [[TMP4]]
|
|
// CHECK30-NEXT: [[ARRAYIDX99:%.*]] = getelementptr inbounds double, double* [[VLA1]], i64 [[TMP55]]
|
|
// CHECK30-NEXT: [[ARRAYIDX100:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX99]], i64 3
|
|
// CHECK30-NEXT: [[TMP56:%.*]] = load double, double* [[ARRAYIDX100]], align 8, !llvm.access.group !15
|
|
// CHECK30-NEXT: [[ADD101:%.*]] = fadd double [[TMP56]], 1.000000e+00
|
|
// CHECK30-NEXT: store double [[ADD101]], double* [[ARRAYIDX100]], align 8, !llvm.access.group !15
|
|
// CHECK30-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0
|
|
// CHECK30-NEXT: [[TMP57:%.*]] = load i64, i64* [[X]], align 8, !llvm.access.group !15
|
|
// CHECK30-NEXT: [[ADD102:%.*]] = add nsw i64 [[TMP57]], 1
|
|
// CHECK30-NEXT: store i64 [[ADD102]], i64* [[X]], align 8, !llvm.access.group !15
|
|
// CHECK30-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1
|
|
// CHECK30-NEXT: [[TMP58:%.*]] = load i8, i8* [[Y]], align 8, !llvm.access.group !15
|
|
// CHECK30-NEXT: [[CONV103:%.*]] = sext i8 [[TMP58]] to i32
|
|
// CHECK30-NEXT: [[ADD104:%.*]] = add nsw i32 [[CONV103]], 1
|
|
// CHECK30-NEXT: [[CONV105:%.*]] = trunc i32 [[ADD104]] to i8
|
|
// CHECK30-NEXT: store i8 [[CONV105]], i8* [[Y]], align 8, !llvm.access.group !15
|
|
// CHECK30-NEXT: br label [[OMP_BODY_CONTINUE106:%.*]]
|
|
// CHECK30: omp.body.continue106:
|
|
// CHECK30-NEXT: br label [[OMP_INNER_FOR_INC107:%.*]]
|
|
// CHECK30: omp.inner.for.inc107:
|
|
// CHECK30-NEXT: [[TMP59:%.*]] = load i32, i32* [[DOTOMP_IV80]], align 4, !llvm.access.group !15
|
|
// CHECK30-NEXT: [[ADD108:%.*]] = add nsw i32 [[TMP59]], 1
|
|
// CHECK30-NEXT: store i32 [[ADD108]], i32* [[DOTOMP_IV80]], align 4, !llvm.access.group !15
|
|
// CHECK30-NEXT: br label [[OMP_INNER_FOR_COND82]], !llvm.loop [[LOOP16:![0-9]+]]
|
|
// CHECK30: omp.inner.for.end109:
|
|
// CHECK30-NEXT: store i8 96, i8* [[IT81]], align 1
|
|
// CHECK30-NEXT: [[TMP60:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK30-NEXT: [[TMP61:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
|
|
// CHECK30-NEXT: call void @llvm.stackrestore(i8* [[TMP61]])
|
|
// CHECK30-NEXT: ret i32 [[TMP60]]
|
|
//
|
|
//
|
|
// CHECK30-LABEL: define {{[^@]+}}@_Z3bari
|
|
// CHECK30-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
|
|
// CHECK30-NEXT: entry:
|
|
// CHECK30-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK30-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK30-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8
|
|
// CHECK30-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK30-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK30-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK30-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]])
|
|
// CHECK30-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK30-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
|
|
// CHECK30-NEXT: store i32 [[ADD]], i32* [[A]], align 4
|
|
// CHECK30-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK30-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]])
|
|
// CHECK30-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK30-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
|
|
// CHECK30-NEXT: store i32 [[ADD2]], i32* [[A]], align 4
|
|
// CHECK30-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK30-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]])
|
|
// CHECK30-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK30-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
|
|
// CHECK30-NEXT: store i32 [[ADD4]], i32* [[A]], align 4
|
|
// CHECK30-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK30-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]])
|
|
// CHECK30-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK30-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
|
|
// CHECK30-NEXT: store i32 [[ADD6]], i32* [[A]], align 4
|
|
// CHECK30-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK30-NEXT: ret i32 [[TMP8]]
|
|
//
|
|
//
|
|
// CHECK30-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
|
|
// CHECK30-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 {
|
|
// CHECK30-NEXT: entry:
|
|
// CHECK30-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
|
|
// CHECK30-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK30-NEXT: [[B:%.*]] = alloca i32, align 4
|
|
// CHECK30-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8
|
|
// CHECK30-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8
|
|
// CHECK30-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
|
|
// CHECK30-NEXT: [[TMP:%.*]] = alloca i64, align 8
|
|
// CHECK30-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
|
|
// CHECK30-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
|
|
// CHECK30-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
|
|
// CHECK30-NEXT: [[IT:%.*]] = alloca i64, align 8
|
|
// CHECK30-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK30-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK30-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK30-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK30-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
|
|
// CHECK30-NEXT: store i32 [[ADD]], i32* [[B]], align 4
|
|
// CHECK30-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK30-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
|
|
// CHECK30-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave()
|
|
// CHECK30-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8
|
|
// CHECK30-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]]
|
|
// CHECK30-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2
|
|
// CHECK30-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8
|
|
// CHECK30-NEXT: [[TMP5:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK30-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 60
|
|
// CHECK30-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8
|
|
// CHECK30-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
|
|
// CHECK30-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK30-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK30-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK30-NEXT: store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK30-NEXT: [[TMP7:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
|
|
// CHECK30-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP7]] to i1
|
|
// CHECK30-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
|
|
// CHECK30: omp_if.then:
|
|
// CHECK30-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK30: omp.inner.for.cond:
|
|
// CHECK30-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18
|
|
// CHECK30-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !18
|
|
// CHECK30-NEXT: [[CMP2:%.*]] = icmp ule i64 [[TMP8]], [[TMP9]]
|
|
// CHECK30-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK30: omp.inner.for.body:
|
|
// CHECK30-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18
|
|
// CHECK30-NEXT: [[MUL:%.*]] = mul i64 [[TMP10]], 400
|
|
// CHECK30-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]
|
|
// CHECK30-NEXT: store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !18
|
|
// CHECK30-NEXT: [[TMP11:%.*]] = load i32, i32* [[B]], align 4, !llvm.access.group !18
|
|
// CHECK30-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP11]] to double
|
|
// CHECK30-NEXT: [[ADD3:%.*]] = fadd double [[CONV]], 1.500000e+00
|
|
// CHECK30-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
|
|
// CHECK30-NEXT: store double [[ADD3]], double* [[A]], align 8, !nontemporal !19, !llvm.access.group !18
|
|
// CHECK30-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
|
|
// CHECK30-NEXT: [[TMP12:%.*]] = load double, double* [[A4]], align 8, !nontemporal !19, !llvm.access.group !18
|
|
// CHECK30-NEXT: [[INC:%.*]] = fadd double [[TMP12]], 1.000000e+00
|
|
// CHECK30-NEXT: store double [[INC]], double* [[A4]], align 8, !nontemporal !19, !llvm.access.group !18
|
|
// CHECK30-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16
|
|
// CHECK30-NEXT: [[TMP13:%.*]] = mul nsw i64 1, [[TMP2]]
|
|
// CHECK30-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP13]]
|
|
// CHECK30-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
|
|
// CHECK30-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2, !llvm.access.group !18
|
|
// CHECK30-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK30: omp.body.continue:
|
|
// CHECK30-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK30: omp.inner.for.inc:
|
|
// CHECK30-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18
|
|
// CHECK30-NEXT: [[ADD7:%.*]] = add i64 [[TMP14]], 1
|
|
// CHECK30-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18
|
|
// CHECK30-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]]
|
|
// CHECK30: omp.inner.for.end:
|
|
// CHECK30-NEXT: br label [[OMP_IF_END:%.*]]
|
|
// CHECK30: omp_if.else:
|
|
// CHECK30-NEXT: br label [[OMP_INNER_FOR_COND8:%.*]]
|
|
// CHECK30: omp.inner.for.cond8:
|
|
// CHECK30-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK30-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK30-NEXT: [[CMP9:%.*]] = icmp ule i64 [[TMP15]], [[TMP16]]
|
|
// CHECK30-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY10:%.*]], label [[OMP_INNER_FOR_END24:%.*]]
|
|
// CHECK30: omp.inner.for.body10:
|
|
// CHECK30-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK30-NEXT: [[MUL11:%.*]] = mul i64 [[TMP17]], 400
|
|
// CHECK30-NEXT: [[SUB12:%.*]] = sub i64 2000, [[MUL11]]
|
|
// CHECK30-NEXT: store i64 [[SUB12]], i64* [[IT]], align 8
|
|
// CHECK30-NEXT: [[TMP18:%.*]] = load i32, i32* [[B]], align 4
|
|
// CHECK30-NEXT: [[CONV13:%.*]] = sitofp i32 [[TMP18]] to double
|
|
// CHECK30-NEXT: [[ADD14:%.*]] = fadd double [[CONV13]], 1.500000e+00
|
|
// CHECK30-NEXT: [[A15:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
|
|
// CHECK30-NEXT: store double [[ADD14]], double* [[A15]], align 8
|
|
// CHECK30-NEXT: [[A16:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
|
|
// CHECK30-NEXT: [[TMP19:%.*]] = load double, double* [[A16]], align 8
|
|
// CHECK30-NEXT: [[INC17:%.*]] = fadd double [[TMP19]], 1.000000e+00
|
|
// CHECK30-NEXT: store double [[INC17]], double* [[A16]], align 8
|
|
// CHECK30-NEXT: [[CONV18:%.*]] = fptosi double [[INC17]] to i16
|
|
// CHECK30-NEXT: [[TMP20:%.*]] = mul nsw i64 1, [[TMP2]]
|
|
// CHECK30-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP20]]
|
|
// CHECK30-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX19]], i64 1
|
|
// CHECK30-NEXT: store i16 [[CONV18]], i16* [[ARRAYIDX20]], align 2
|
|
// CHECK30-NEXT: br label [[OMP_BODY_CONTINUE21:%.*]]
|
|
// CHECK30: omp.body.continue21:
|
|
// CHECK30-NEXT: br label [[OMP_INNER_FOR_INC22:%.*]]
|
|
// CHECK30: omp.inner.for.inc22:
|
|
// CHECK30-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK30-NEXT: [[ADD23:%.*]] = add i64 [[TMP21]], 1
|
|
// CHECK30-NEXT: store i64 [[ADD23]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK30-NEXT: br label [[OMP_INNER_FOR_COND8]], !llvm.loop [[LOOP22:![0-9]+]]
|
|
// CHECK30: omp.inner.for.end24:
|
|
// CHECK30-NEXT: br label [[OMP_IF_END]]
|
|
// CHECK30: omp_if.end:
|
|
// CHECK30-NEXT: store i64 400, i64* [[IT]], align 8
|
|
// CHECK30-NEXT: [[TMP22:%.*]] = mul nsw i64 1, [[TMP2]]
|
|
// CHECK30-NEXT: [[ARRAYIDX25:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP22]]
|
|
// CHECK30-NEXT: [[ARRAYIDX26:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX25]], i64 1
|
|
// CHECK30-NEXT: [[TMP23:%.*]] = load i16, i16* [[ARRAYIDX26]], align 2
|
|
// CHECK30-NEXT: [[CONV27:%.*]] = sext i16 [[TMP23]] to i32
|
|
// CHECK30-NEXT: [[TMP24:%.*]] = load i32, i32* [[B]], align 4
|
|
// CHECK30-NEXT: [[ADD28:%.*]] = add nsw i32 [[CONV27]], [[TMP24]]
|
|
// CHECK30-NEXT: [[TMP25:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
|
|
// CHECK30-NEXT: call void @llvm.stackrestore(i8* [[TMP25]])
|
|
// CHECK30-NEXT: ret i32 [[ADD28]]
|
|
//
|
|
//
|
|
// CHECK30-LABEL: define {{[^@]+}}@_ZL7fstatici
|
|
// CHECK30-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
|
|
// CHECK30-NEXT: entry:
|
|
// CHECK30-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK30-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK30-NEXT: [[AA:%.*]] = alloca i16, align 2
|
|
// CHECK30-NEXT: [[AAA:%.*]] = alloca i8, align 1
|
|
// CHECK30-NEXT: [[B:%.*]] = alloca [10 x i32], align 4
|
|
// CHECK30-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK30-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK30-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK30-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK30-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK30-NEXT: store i16 0, i16* [[AA]], align 2
|
|
// CHECK30-NEXT: store i8 0, i8* [[AAA]], align 1
|
|
// CHECK30-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK30-NEXT: store i32 429496720, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK30-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK30-NEXT: ret i32 [[TMP0]]
|
|
//
|
|
//
|
|
// CHECK30-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
|
|
// CHECK30-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat {
|
|
// CHECK30-NEXT: entry:
|
|
// CHECK30-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK30-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK30-NEXT: [[AA:%.*]] = alloca i16, align 2
|
|
// CHECK30-NEXT: [[B:%.*]] = alloca [10 x i32], align 4
|
|
// CHECK30-NEXT: [[TMP:%.*]] = alloca i64, align 8
|
|
// CHECK30-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
|
|
// CHECK30-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
|
|
// CHECK30-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
|
|
// CHECK30-NEXT: [[I:%.*]] = alloca i64, align 8
|
|
// CHECK30-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK30-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK30-NEXT: store i16 0, i16* [[AA]], align 2
|
|
// CHECK30-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK30-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK30-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK30-NEXT: store i64 [[TMP0]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK30-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK30: omp.inner.for.cond:
|
|
// CHECK30-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !24
|
|
// CHECK30-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !24
|
|
// CHECK30-NEXT: [[CMP:%.*]] = icmp sle i64 [[TMP1]], [[TMP2]]
|
|
// CHECK30-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK30: omp.inner.for.body:
|
|
// CHECK30-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !24
|
|
// CHECK30-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP3]], 3
|
|
// CHECK30-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
|
|
// CHECK30-NEXT: store i64 [[ADD]], i64* [[I]], align 8, !llvm.access.group !24
|
|
// CHECK30-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !24
|
|
// CHECK30-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1
|
|
// CHECK30-NEXT: store i32 [[ADD1]], i32* [[A]], align 4, !llvm.access.group !24
|
|
// CHECK30-NEXT: [[TMP5:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !24
|
|
// CHECK30-NEXT: [[CONV:%.*]] = sext i16 [[TMP5]] to i32
|
|
// CHECK30-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 1
|
|
// CHECK30-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
|
|
// CHECK30-NEXT: store i16 [[CONV3]], i16* [[AA]], align 2, !llvm.access.group !24
|
|
// CHECK30-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2
|
|
// CHECK30-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !24
|
|
// CHECK30-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP6]], 1
|
|
// CHECK30-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !24
|
|
// CHECK30-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK30: omp.body.continue:
|
|
// CHECK30-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK30: omp.inner.for.inc:
|
|
// CHECK30-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !24
|
|
// CHECK30-NEXT: [[ADD5:%.*]] = add nsw i64 [[TMP7]], 1
|
|
// CHECK30-NEXT: store i64 [[ADD5]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !24
|
|
// CHECK30-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]]
|
|
// CHECK30: omp.inner.for.end:
|
|
// CHECK30-NEXT: store i64 11, i64* [[I]], align 8
|
|
// CHECK30-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK30-NEXT: ret i32 [[TMP8]]
|
|
//
|
|
//
|
|
// CHECK31-LABEL: define {{[^@]+}}@_Z7get_valv
|
|
// CHECK31-SAME: () #[[ATTR0:[0-9]+]] {
|
|
// CHECK31-NEXT: entry:
|
|
// CHECK31-NEXT: ret i64 0
|
|
//
|
|
//
|
|
// CHECK31-LABEL: define {{[^@]+}}@_Z3fooi
|
|
// CHECK31-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
|
|
// CHECK31-NEXT: entry:
|
|
// CHECK31-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK31-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK31-NEXT: [[AA:%.*]] = alloca i16, align 2
|
|
// CHECK31-NEXT: [[B:%.*]] = alloca [10 x float], align 4
|
|
// CHECK31-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4
|
|
// CHECK31-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4
|
|
// CHECK31-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8
|
|
// CHECK31-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4
|
|
// CHECK31-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4
|
|
// CHECK31-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK31-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK31-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK31-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK31-NEXT: [[I:%.*]] = alloca i32, align 4
|
|
// CHECK31-NEXT: [[K:%.*]] = alloca i64, align 8
|
|
// CHECK31-NEXT: [[_TMP3:%.*]] = alloca i32, align 4
|
|
// CHECK31-NEXT: [[DOTOMP_LB4:%.*]] = alloca i32, align 4
|
|
// CHECK31-NEXT: [[DOTOMP_UB5:%.*]] = alloca i32, align 4
|
|
// CHECK31-NEXT: [[DOTOMP_IV6:%.*]] = alloca i32, align 4
|
|
// CHECK31-NEXT: [[DOTLINEAR_START:%.*]] = alloca i64, align 8
|
|
// CHECK31-NEXT: [[I7:%.*]] = alloca i32, align 4
|
|
// CHECK31-NEXT: [[K8:%.*]] = alloca i64, align 8
|
|
// CHECK31-NEXT: [[LIN:%.*]] = alloca i32, align 4
|
|
// CHECK31-NEXT: [[_TMP21:%.*]] = alloca i64, align 4
|
|
// CHECK31-NEXT: [[DOTOMP_LB22:%.*]] = alloca i64, align 8
|
|
// CHECK31-NEXT: [[DOTOMP_UB23:%.*]] = alloca i64, align 8
|
|
// CHECK31-NEXT: [[DOTOMP_IV24:%.*]] = alloca i64, align 8
|
|
// CHECK31-NEXT: [[DOTLINEAR_START25:%.*]] = alloca i32, align 4
|
|
// CHECK31-NEXT: [[DOTLINEAR_START26:%.*]] = alloca i32, align 4
|
|
// CHECK31-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8
|
|
// CHECK31-NEXT: [[IT:%.*]] = alloca i64, align 8
|
|
// CHECK31-NEXT: [[LIN28:%.*]] = alloca i32, align 4
|
|
// CHECK31-NEXT: [[A29:%.*]] = alloca i32, align 4
|
|
// CHECK31-NEXT: [[_TMP58:%.*]] = alloca i16, align 2
|
|
// CHECK31-NEXT: [[DOTOMP_LB59:%.*]] = alloca i32, align 4
|
|
// CHECK31-NEXT: [[DOTOMP_UB60:%.*]] = alloca i32, align 4
|
|
// CHECK31-NEXT: [[DOTOMP_IV61:%.*]] = alloca i32, align 4
|
|
// CHECK31-NEXT: [[IT62:%.*]] = alloca i16, align 2
|
|
// CHECK31-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
|
// CHECK31-NEXT: [[_TMP77:%.*]] = alloca i8, align 1
|
|
// CHECK31-NEXT: [[DOTOMP_LB78:%.*]] = alloca i32, align 4
|
|
// CHECK31-NEXT: [[DOTOMP_UB79:%.*]] = alloca i32, align 4
|
|
// CHECK31-NEXT: [[DOTOMP_IV80:%.*]] = alloca i32, align 4
|
|
// CHECK31-NEXT: [[IT81:%.*]] = alloca i8, align 1
|
|
// CHECK31-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK31-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK31-NEXT: store i16 0, i16* [[AA]], align 2
|
|
// CHECK31-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK31-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave()
|
|
// CHECK31-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4
|
|
// CHECK31-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4
|
|
// CHECK31-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4
|
|
// CHECK31-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK31-NEXT: [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]]
|
|
// CHECK31-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8
|
|
// CHECK31-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4
|
|
// CHECK31-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK31-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK31-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK31-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK31-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK31: omp.inner.for.cond:
|
|
// CHECK31-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
|
|
// CHECK31-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !3
|
|
// CHECK31-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
|
|
// CHECK31-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK31: omp.inner.for.body:
|
|
// CHECK31-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
|
|
// CHECK31-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5
|
|
// CHECK31-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]]
|
|
// CHECK31-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !3
|
|
// CHECK31-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK31: omp.body.continue:
|
|
// CHECK31-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK31: omp.inner.for.inc:
|
|
// CHECK31-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
|
|
// CHECK31-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
|
|
// CHECK31-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
|
|
// CHECK31-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]
|
|
// CHECK31: omp.inner.for.end:
|
|
// CHECK31-NEXT: store i32 33, i32* [[I]], align 4
|
|
// CHECK31-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv()
|
|
// CHECK31-NEXT: store i64 [[CALL]], i64* [[K]], align 8
|
|
// CHECK31-NEXT: store i32 0, i32* [[DOTOMP_LB4]], align 4
|
|
// CHECK31-NEXT: store i32 8, i32* [[DOTOMP_UB5]], align 4
|
|
// CHECK31-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_LB4]], align 4
|
|
// CHECK31-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV6]], align 4
|
|
// CHECK31-NEXT: [[TMP10:%.*]] = load i64, i64* [[K]], align 8
|
|
// CHECK31-NEXT: store i64 [[TMP10]], i64* [[DOTLINEAR_START]], align 8
|
|
// CHECK31-NEXT: br label [[OMP_INNER_FOR_COND9:%.*]]
|
|
// CHECK31: omp.inner.for.cond9:
|
|
// CHECK31-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !7
|
|
// CHECK31-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB5]], align 4, !llvm.access.group !7
|
|
// CHECK31-NEXT: [[CMP10:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]]
|
|
// CHECK31-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY11:%.*]], label [[OMP_INNER_FOR_END19:%.*]]
|
|
// CHECK31: omp.inner.for.body11:
|
|
// CHECK31-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !7
|
|
// CHECK31-NEXT: [[MUL12:%.*]] = mul nsw i32 [[TMP13]], 1
|
|
// CHECK31-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL12]]
|
|
// CHECK31-NEXT: store i32 [[SUB]], i32* [[I7]], align 4, !llvm.access.group !7
|
|
// CHECK31-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8, !llvm.access.group !7
|
|
// CHECK31-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !7
|
|
// CHECK31-NEXT: [[MUL13:%.*]] = mul nsw i32 [[TMP15]], 3
|
|
// CHECK31-NEXT: [[CONV:%.*]] = sext i32 [[MUL13]] to i64
|
|
// CHECK31-NEXT: [[ADD14:%.*]] = add nsw i64 [[TMP14]], [[CONV]]
|
|
// CHECK31-NEXT: store i64 [[ADD14]], i64* [[K8]], align 8, !llvm.access.group !7
|
|
// CHECK31-NEXT: [[TMP16:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !7
|
|
// CHECK31-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP16]], 1
|
|
// CHECK31-NEXT: store i32 [[ADD15]], i32* [[A]], align 4, !llvm.access.group !7
|
|
// CHECK31-NEXT: br label [[OMP_BODY_CONTINUE16:%.*]]
|
|
// CHECK31: omp.body.continue16:
|
|
// CHECK31-NEXT: br label [[OMP_INNER_FOR_INC17:%.*]]
|
|
// CHECK31: omp.inner.for.inc17:
|
|
// CHECK31-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !7
|
|
// CHECK31-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP17]], 1
|
|
// CHECK31-NEXT: store i32 [[ADD18]], i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !7
|
|
// CHECK31-NEXT: br label [[OMP_INNER_FOR_COND9]], !llvm.loop [[LOOP8:![0-9]+]]
|
|
// CHECK31: omp.inner.for.end19:
|
|
// CHECK31-NEXT: store i32 1, i32* [[I7]], align 4
|
|
// CHECK31-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8
|
|
// CHECK31-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP18]], 27
|
|
// CHECK31-NEXT: store i64 [[ADD20]], i64* [[K]], align 8
|
|
// CHECK31-NEXT: store i32 12, i32* [[LIN]], align 4
|
|
// CHECK31-NEXT: store i64 0, i64* [[DOTOMP_LB22]], align 8
|
|
// CHECK31-NEXT: store i64 3, i64* [[DOTOMP_UB23]], align 8
|
|
// CHECK31-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_LB22]], align 8
|
|
// CHECK31-NEXT: store i64 [[TMP19]], i64* [[DOTOMP_IV24]], align 8
|
|
// CHECK31-NEXT: [[TMP20:%.*]] = load i32, i32* [[LIN]], align 4
|
|
// CHECK31-NEXT: store i32 [[TMP20]], i32* [[DOTLINEAR_START25]], align 4
|
|
// CHECK31-NEXT: [[TMP21:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK31-NEXT: store i32 [[TMP21]], i32* [[DOTLINEAR_START26]], align 4
|
|
// CHECK31-NEXT: [[CALL27:%.*]] = call i64 @_Z7get_valv()
|
|
// CHECK31-NEXT: store i64 [[CALL27]], i64* [[DOTLINEAR_STEP]], align 8
|
|
// CHECK31-NEXT: br label [[OMP_INNER_FOR_COND30:%.*]]
|
|
// CHECK31: omp.inner.for.cond30:
|
|
// CHECK31-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !10
|
|
// CHECK31-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_UB23]], align 8, !llvm.access.group !10
|
|
// CHECK31-NEXT: [[CMP31:%.*]] = icmp ule i64 [[TMP22]], [[TMP23]]
|
|
// CHECK31-NEXT: br i1 [[CMP31]], label [[OMP_INNER_FOR_BODY32:%.*]], label [[OMP_INNER_FOR_END49:%.*]]
|
|
// CHECK31: omp.inner.for.body32:
|
|
// CHECK31-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !10
|
|
// CHECK31-NEXT: [[MUL33:%.*]] = mul i64 [[TMP24]], 400
|
|
// CHECK31-NEXT: [[SUB34:%.*]] = sub i64 2000, [[MUL33]]
|
|
// CHECK31-NEXT: store i64 [[SUB34]], i64* [[IT]], align 8, !llvm.access.group !10
|
|
// CHECK31-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTLINEAR_START25]], align 4, !llvm.access.group !10
|
|
// CHECK31-NEXT: [[CONV35:%.*]] = sext i32 [[TMP25]] to i64
|
|
// CHECK31-NEXT: [[TMP26:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !10
|
|
// CHECK31-NEXT: [[TMP27:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !10
|
|
// CHECK31-NEXT: [[MUL36:%.*]] = mul i64 [[TMP26]], [[TMP27]]
|
|
// CHECK31-NEXT: [[ADD37:%.*]] = add i64 [[CONV35]], [[MUL36]]
|
|
// CHECK31-NEXT: [[CONV38:%.*]] = trunc i64 [[ADD37]] to i32
|
|
// CHECK31-NEXT: store i32 [[CONV38]], i32* [[LIN28]], align 4, !llvm.access.group !10
|
|
// CHECK31-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTLINEAR_START26]], align 4, !llvm.access.group !10
|
|
// CHECK31-NEXT: [[CONV39:%.*]] = sext i32 [[TMP28]] to i64
|
|
// CHECK31-NEXT: [[TMP29:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !10
|
|
// CHECK31-NEXT: [[TMP30:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !10
|
|
// CHECK31-NEXT: [[MUL40:%.*]] = mul i64 [[TMP29]], [[TMP30]]
|
|
// CHECK31-NEXT: [[ADD41:%.*]] = add i64 [[CONV39]], [[MUL40]]
|
|
// CHECK31-NEXT: [[CONV42:%.*]] = trunc i64 [[ADD41]] to i32
|
|
// CHECK31-NEXT: store i32 [[CONV42]], i32* [[A29]], align 4, !llvm.access.group !10
|
|
// CHECK31-NEXT: [[TMP31:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !10
|
|
// CHECK31-NEXT: [[CONV43:%.*]] = sext i16 [[TMP31]] to i32
|
|
// CHECK31-NEXT: [[ADD44:%.*]] = add nsw i32 [[CONV43]], 1
|
|
// CHECK31-NEXT: [[CONV45:%.*]] = trunc i32 [[ADD44]] to i16
|
|
// CHECK31-NEXT: store i16 [[CONV45]], i16* [[AA]], align 2, !llvm.access.group !10
|
|
// CHECK31-NEXT: br label [[OMP_BODY_CONTINUE46:%.*]]
|
|
// CHECK31: omp.body.continue46:
|
|
// CHECK31-NEXT: br label [[OMP_INNER_FOR_INC47:%.*]]
|
|
// CHECK31: omp.inner.for.inc47:
|
|
// CHECK31-NEXT: [[TMP32:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !10
|
|
// CHECK31-NEXT: [[ADD48:%.*]] = add i64 [[TMP32]], 1
|
|
// CHECK31-NEXT: store i64 [[ADD48]], i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !10
|
|
// CHECK31-NEXT: br label [[OMP_INNER_FOR_COND30]], !llvm.loop [[LOOP11:![0-9]+]]
|
|
// CHECK31: omp.inner.for.end49:
|
|
// CHECK31-NEXT: store i64 400, i64* [[IT]], align 8
|
|
// CHECK31-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTLINEAR_START25]], align 4
|
|
// CHECK31-NEXT: [[CONV50:%.*]] = sext i32 [[TMP33]] to i64
|
|
// CHECK31-NEXT: [[TMP34:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
|
|
// CHECK31-NEXT: [[MUL51:%.*]] = mul i64 4, [[TMP34]]
|
|
// CHECK31-NEXT: [[ADD52:%.*]] = add i64 [[CONV50]], [[MUL51]]
|
|
// CHECK31-NEXT: [[CONV53:%.*]] = trunc i64 [[ADD52]] to i32
|
|
// CHECK31-NEXT: store i32 [[CONV53]], i32* [[LIN]], align 4
|
|
// CHECK31-NEXT: [[TMP35:%.*]] = load i32, i32* [[DOTLINEAR_START26]], align 4
|
|
// CHECK31-NEXT: [[CONV54:%.*]] = sext i32 [[TMP35]] to i64
|
|
// CHECK31-NEXT: [[TMP36:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
|
|
// CHECK31-NEXT: [[MUL55:%.*]] = mul i64 4, [[TMP36]]
|
|
// CHECK31-NEXT: [[ADD56:%.*]] = add i64 [[CONV54]], [[MUL55]]
|
|
// CHECK31-NEXT: [[CONV57:%.*]] = trunc i64 [[ADD56]] to i32
|
|
// CHECK31-NEXT: store i32 [[CONV57]], i32* [[A]], align 4
|
|
// CHECK31-NEXT: store i32 0, i32* [[DOTOMP_LB59]], align 4
|
|
// CHECK31-NEXT: store i32 3, i32* [[DOTOMP_UB60]], align 4
|
|
// CHECK31-NEXT: [[TMP37:%.*]] = load i32, i32* [[DOTOMP_LB59]], align 4
|
|
// CHECK31-NEXT: store i32 [[TMP37]], i32* [[DOTOMP_IV61]], align 4
|
|
// CHECK31-NEXT: br label [[OMP_INNER_FOR_COND63:%.*]]
|
|
// CHECK31: omp.inner.for.cond63:
|
|
// CHECK31-NEXT: [[TMP38:%.*]] = load i32, i32* [[DOTOMP_IV61]], align 4, !llvm.access.group !13
|
|
// CHECK31-NEXT: [[TMP39:%.*]] = load i32, i32* [[DOTOMP_UB60]], align 4, !llvm.access.group !13
|
|
// CHECK31-NEXT: [[CMP64:%.*]] = icmp sle i32 [[TMP38]], [[TMP39]]
|
|
// CHECK31-NEXT: br i1 [[CMP64]], label [[OMP_INNER_FOR_BODY65:%.*]], label [[OMP_INNER_FOR_END76:%.*]]
|
|
// CHECK31: omp.inner.for.body65:
|
|
// CHECK31-NEXT: [[TMP40:%.*]] = load i32, i32* [[DOTOMP_IV61]], align 4, !llvm.access.group !13
|
|
// CHECK31-NEXT: [[MUL66:%.*]] = mul nsw i32 [[TMP40]], 4
|
|
// CHECK31-NEXT: [[ADD67:%.*]] = add nsw i32 6, [[MUL66]]
|
|
// CHECK31-NEXT: [[CONV68:%.*]] = trunc i32 [[ADD67]] to i16
|
|
// CHECK31-NEXT: store i16 [[CONV68]], i16* [[IT62]], align 2, !llvm.access.group !13
|
|
// CHECK31-NEXT: [[TMP41:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !13
|
|
// CHECK31-NEXT: [[ADD69:%.*]] = add nsw i32 [[TMP41]], 1
|
|
// CHECK31-NEXT: store i32 [[ADD69]], i32* [[A]], align 4, !llvm.access.group !13
|
|
// CHECK31-NEXT: [[TMP42:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !13
|
|
// CHECK31-NEXT: [[CONV70:%.*]] = sext i16 [[TMP42]] to i32
|
|
// CHECK31-NEXT: [[ADD71:%.*]] = add nsw i32 [[CONV70]], 1
|
|
// CHECK31-NEXT: [[CONV72:%.*]] = trunc i32 [[ADD71]] to i16
|
|
// CHECK31-NEXT: store i16 [[CONV72]], i16* [[AA]], align 2, !llvm.access.group !13
|
|
// CHECK31-NEXT: br label [[OMP_BODY_CONTINUE73:%.*]]
|
|
// CHECK31: omp.body.continue73:
|
|
// CHECK31-NEXT: br label [[OMP_INNER_FOR_INC74:%.*]]
|
|
// CHECK31: omp.inner.for.inc74:
|
|
// CHECK31-NEXT: [[TMP43:%.*]] = load i32, i32* [[DOTOMP_IV61]], align 4, !llvm.access.group !13
|
|
// CHECK31-NEXT: [[ADD75:%.*]] = add nsw i32 [[TMP43]], 1
|
|
// CHECK31-NEXT: store i32 [[ADD75]], i32* [[DOTOMP_IV61]], align 4, !llvm.access.group !13
|
|
// CHECK31-NEXT: br label [[OMP_INNER_FOR_COND63]], !llvm.loop [[LOOP14:![0-9]+]]
|
|
// CHECK31: omp.inner.for.end76:
|
|
// CHECK31-NEXT: store i16 22, i16* [[IT62]], align 2
|
|
// CHECK31-NEXT: [[TMP44:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK31-NEXT: store i32 [[TMP44]], i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK31-NEXT: store i32 0, i32* [[DOTOMP_LB78]], align 4
|
|
// CHECK31-NEXT: store i32 25, i32* [[DOTOMP_UB79]], align 4
|
|
// CHECK31-NEXT: [[TMP45:%.*]] = load i32, i32* [[DOTOMP_LB78]], align 4
|
|
// CHECK31-NEXT: store i32 [[TMP45]], i32* [[DOTOMP_IV80]], align 4
|
|
// CHECK31-NEXT: br label [[OMP_INNER_FOR_COND82:%.*]]
|
|
// CHECK31: omp.inner.for.cond82:
|
|
// CHECK31-NEXT: [[TMP46:%.*]] = load i32, i32* [[DOTOMP_IV80]], align 4, !llvm.access.group !16
|
|
// CHECK31-NEXT: [[TMP47:%.*]] = load i32, i32* [[DOTOMP_UB79]], align 4, !llvm.access.group !16
|
|
// CHECK31-NEXT: [[CMP83:%.*]] = icmp sle i32 [[TMP46]], [[TMP47]]
|
|
// CHECK31-NEXT: br i1 [[CMP83]], label [[OMP_INNER_FOR_BODY84:%.*]], label [[OMP_INNER_FOR_END109:%.*]]
|
|
// CHECK31: omp.inner.for.body84:
|
|
// CHECK31-NEXT: [[TMP48:%.*]] = load i32, i32* [[DOTOMP_IV80]], align 4, !llvm.access.group !16
|
|
// CHECK31-NEXT: [[MUL85:%.*]] = mul nsw i32 [[TMP48]], 1
|
|
// CHECK31-NEXT: [[SUB86:%.*]] = sub nsw i32 122, [[MUL85]]
|
|
// CHECK31-NEXT: [[CONV87:%.*]] = trunc i32 [[SUB86]] to i8
|
|
// CHECK31-NEXT: store i8 [[CONV87]], i8* [[IT81]], align 1, !llvm.access.group !16
|
|
// CHECK31-NEXT: [[TMP49:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !16
|
|
// CHECK31-NEXT: [[ADD88:%.*]] = add nsw i32 [[TMP49]], 1
|
|
// CHECK31-NEXT: store i32 [[ADD88]], i32* [[A]], align 4, !llvm.access.group !16
|
|
// CHECK31-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 2
|
|
// CHECK31-NEXT: [[TMP50:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !16
|
|
// CHECK31-NEXT: [[CONV89:%.*]] = fpext float [[TMP50]] to double
|
|
// CHECK31-NEXT: [[ADD90:%.*]] = fadd double [[CONV89]], 1.000000e+00
|
|
// CHECK31-NEXT: [[CONV91:%.*]] = fptrunc double [[ADD90]] to float
|
|
// CHECK31-NEXT: store float [[CONV91]], float* [[ARRAYIDX]], align 4, !llvm.access.group !16
|
|
// CHECK31-NEXT: [[ARRAYIDX92:%.*]] = getelementptr inbounds float, float* [[VLA]], i32 3
|
|
// CHECK31-NEXT: [[TMP51:%.*]] = load float, float* [[ARRAYIDX92]], align 4, !llvm.access.group !16
|
|
// CHECK31-NEXT: [[CONV93:%.*]] = fpext float [[TMP51]] to double
|
|
// CHECK31-NEXT: [[ADD94:%.*]] = fadd double [[CONV93]], 1.000000e+00
|
|
// CHECK31-NEXT: [[CONV95:%.*]] = fptrunc double [[ADD94]] to float
|
|
// CHECK31-NEXT: store float [[CONV95]], float* [[ARRAYIDX92]], align 4, !llvm.access.group !16
|
|
// CHECK31-NEXT: [[ARRAYIDX96:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i32 0, i32 1
|
|
// CHECK31-NEXT: [[ARRAYIDX97:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX96]], i32 0, i32 2
|
|
// CHECK31-NEXT: [[TMP52:%.*]] = load double, double* [[ARRAYIDX97]], align 8, !llvm.access.group !16
|
|
// CHECK31-NEXT: [[ADD98:%.*]] = fadd double [[TMP52]], 1.000000e+00
|
|
// CHECK31-NEXT: store double [[ADD98]], double* [[ARRAYIDX97]], align 8, !llvm.access.group !16
|
|
// CHECK31-NEXT: [[TMP53:%.*]] = mul nsw i32 1, [[TMP2]]
|
|
// CHECK31-NEXT: [[ARRAYIDX99:%.*]] = getelementptr inbounds double, double* [[VLA1]], i32 [[TMP53]]
|
|
// CHECK31-NEXT: [[ARRAYIDX100:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX99]], i32 3
|
|
// CHECK31-NEXT: [[TMP54:%.*]] = load double, double* [[ARRAYIDX100]], align 8, !llvm.access.group !16
|
|
// CHECK31-NEXT: [[ADD101:%.*]] = fadd double [[TMP54]], 1.000000e+00
|
|
// CHECK31-NEXT: store double [[ADD101]], double* [[ARRAYIDX100]], align 8, !llvm.access.group !16
|
|
// CHECK31-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0
|
|
// CHECK31-NEXT: [[TMP55:%.*]] = load i64, i64* [[X]], align 4, !llvm.access.group !16
|
|
// CHECK31-NEXT: [[ADD102:%.*]] = add nsw i64 [[TMP55]], 1
|
|
// CHECK31-NEXT: store i64 [[ADD102]], i64* [[X]], align 4, !llvm.access.group !16
|
|
// CHECK31-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1
|
|
// CHECK31-NEXT: [[TMP56:%.*]] = load i8, i8* [[Y]], align 4, !llvm.access.group !16
|
|
// CHECK31-NEXT: [[CONV103:%.*]] = sext i8 [[TMP56]] to i32
|
|
// CHECK31-NEXT: [[ADD104:%.*]] = add nsw i32 [[CONV103]], 1
|
|
// CHECK31-NEXT: [[CONV105:%.*]] = trunc i32 [[ADD104]] to i8
|
|
// CHECK31-NEXT: store i8 [[CONV105]], i8* [[Y]], align 4, !llvm.access.group !16
|
|
// CHECK31-NEXT: br label [[OMP_BODY_CONTINUE106:%.*]]
|
|
// CHECK31: omp.body.continue106:
|
|
// CHECK31-NEXT: br label [[OMP_INNER_FOR_INC107:%.*]]
|
|
// CHECK31: omp.inner.for.inc107:
|
|
// CHECK31-NEXT: [[TMP57:%.*]] = load i32, i32* [[DOTOMP_IV80]], align 4, !llvm.access.group !16
|
|
// CHECK31-NEXT: [[ADD108:%.*]] = add nsw i32 [[TMP57]], 1
|
|
// CHECK31-NEXT: store i32 [[ADD108]], i32* [[DOTOMP_IV80]], align 4, !llvm.access.group !16
|
|
// CHECK31-NEXT: br label [[OMP_INNER_FOR_COND82]], !llvm.loop [[LOOP17:![0-9]+]]
|
|
// CHECK31: omp.inner.for.end109:
|
|
// CHECK31-NEXT: store i8 96, i8* [[IT81]], align 1
|
|
// CHECK31-NEXT: [[TMP58:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK31-NEXT: [[TMP59:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
|
|
// CHECK31-NEXT: call void @llvm.stackrestore(i8* [[TMP59]])
|
|
// CHECK31-NEXT: ret i32 [[TMP58]]
|
|
//
|
|
//
|
|
// CHECK31-LABEL: define {{[^@]+}}@_Z3bari
|
|
// CHECK31-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
|
|
// CHECK31-NEXT: entry:
|
|
// CHECK31-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK31-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK31-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4
|
|
// CHECK31-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK31-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK31-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK31-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]])
|
|
// CHECK31-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK31-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
|
|
// CHECK31-NEXT: store i32 [[ADD]], i32* [[A]], align 4
|
|
// CHECK31-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK31-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]])
|
|
// CHECK31-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK31-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
|
|
// CHECK31-NEXT: store i32 [[ADD2]], i32* [[A]], align 4
|
|
// CHECK31-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK31-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]])
|
|
// CHECK31-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK31-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
|
|
// CHECK31-NEXT: store i32 [[ADD4]], i32* [[A]], align 4
|
|
// CHECK31-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK31-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]])
|
|
// CHECK31-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK31-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
|
|
// CHECK31-NEXT: store i32 [[ADD6]], i32* [[A]], align 4
|
|
// CHECK31-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK31-NEXT: ret i32 [[TMP8]]
|
|
//
|
|
//
|
|
// CHECK31-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
|
|
// CHECK31-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 {
|
|
// CHECK31-NEXT: entry:
|
|
// CHECK31-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
|
|
// CHECK31-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK31-NEXT: [[B:%.*]] = alloca i32, align 4
|
|
// CHECK31-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4
|
|
// CHECK31-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4
|
|
// CHECK31-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
|
|
// CHECK31-NEXT: [[TMP:%.*]] = alloca i64, align 4
|
|
// CHECK31-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
|
|
// CHECK31-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
|
|
// CHECK31-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
|
|
// CHECK31-NEXT: [[IT:%.*]] = alloca i64, align 8
|
|
// CHECK31-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK31-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK31-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK31-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK31-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
|
|
// CHECK31-NEXT: store i32 [[ADD]], i32* [[B]], align 4
|
|
// CHECK31-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK31-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave()
|
|
// CHECK31-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4
|
|
// CHECK31-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]]
|
|
// CHECK31-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2
|
|
// CHECK31-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4
|
|
// CHECK31-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK31-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 60
|
|
// CHECK31-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8
|
|
// CHECK31-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
|
|
// CHECK31-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK31-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK31-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK31-NEXT: store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK31-NEXT: [[TMP6:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
|
|
// CHECK31-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP6]] to i1
|
|
// CHECK31-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
|
|
// CHECK31: omp_if.then:
|
|
// CHECK31-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK31: omp.inner.for.cond:
|
|
// CHECK31-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !19
|
|
// CHECK31-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !19
|
|
// CHECK31-NEXT: [[CMP2:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]]
|
|
// CHECK31-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK31: omp.inner.for.body:
|
|
// CHECK31-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !19
|
|
// CHECK31-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400
|
|
// CHECK31-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]
|
|
// CHECK31-NEXT: store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !19
|
|
// CHECK31-NEXT: [[TMP10:%.*]] = load i32, i32* [[B]], align 4, !llvm.access.group !19
|
|
// CHECK31-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP10]] to double
|
|
// CHECK31-NEXT: [[ADD3:%.*]] = fadd double [[CONV]], 1.500000e+00
|
|
// CHECK31-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
|
|
// CHECK31-NEXT: store double [[ADD3]], double* [[A]], align 4, !nontemporal !20, !llvm.access.group !19
|
|
// CHECK31-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
|
|
// CHECK31-NEXT: [[TMP11:%.*]] = load double, double* [[A4]], align 4, !nontemporal !20, !llvm.access.group !19
|
|
// CHECK31-NEXT: [[INC:%.*]] = fadd double [[TMP11]], 1.000000e+00
|
|
// CHECK31-NEXT: store double [[INC]], double* [[A4]], align 4, !nontemporal !20, !llvm.access.group !19
|
|
// CHECK31-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16
|
|
// CHECK31-NEXT: [[TMP12:%.*]] = mul nsw i32 1, [[TMP1]]
|
|
// CHECK31-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP12]]
|
|
// CHECK31-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
|
|
// CHECK31-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2, !llvm.access.group !19
|
|
// CHECK31-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK31: omp.body.continue:
|
|
// CHECK31-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK31: omp.inner.for.inc:
|
|
// CHECK31-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !19
|
|
// CHECK31-NEXT: [[ADD7:%.*]] = add i64 [[TMP13]], 1
|
|
// CHECK31-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !19
|
|
// CHECK31-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]]
|
|
// CHECK31: omp.inner.for.end:
|
|
// CHECK31-NEXT: br label [[OMP_IF_END:%.*]]
|
|
// CHECK31: omp_if.else:
|
|
// CHECK31-NEXT: br label [[OMP_INNER_FOR_COND8:%.*]]
|
|
// CHECK31: omp.inner.for.cond8:
|
|
// CHECK31-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK31-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK31-NEXT: [[CMP9:%.*]] = icmp ule i64 [[TMP14]], [[TMP15]]
|
|
// CHECK31-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY10:%.*]], label [[OMP_INNER_FOR_END24:%.*]]
|
|
// CHECK31: omp.inner.for.body10:
|
|
// CHECK31-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK31-NEXT: [[MUL11:%.*]] = mul i64 [[TMP16]], 400
|
|
// CHECK31-NEXT: [[SUB12:%.*]] = sub i64 2000, [[MUL11]]
|
|
// CHECK31-NEXT: store i64 [[SUB12]], i64* [[IT]], align 8
|
|
// CHECK31-NEXT: [[TMP17:%.*]] = load i32, i32* [[B]], align 4
|
|
// CHECK31-NEXT: [[CONV13:%.*]] = sitofp i32 [[TMP17]] to double
|
|
// CHECK31-NEXT: [[ADD14:%.*]] = fadd double [[CONV13]], 1.500000e+00
|
|
// CHECK31-NEXT: [[A15:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
|
|
// CHECK31-NEXT: store double [[ADD14]], double* [[A15]], align 4
|
|
// CHECK31-NEXT: [[A16:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
|
|
// CHECK31-NEXT: [[TMP18:%.*]] = load double, double* [[A16]], align 4
|
|
// CHECK31-NEXT: [[INC17:%.*]] = fadd double [[TMP18]], 1.000000e+00
|
|
// CHECK31-NEXT: store double [[INC17]], double* [[A16]], align 4
|
|
// CHECK31-NEXT: [[CONV18:%.*]] = fptosi double [[INC17]] to i16
|
|
// CHECK31-NEXT: [[TMP19:%.*]] = mul nsw i32 1, [[TMP1]]
|
|
// CHECK31-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP19]]
|
|
// CHECK31-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX19]], i32 1
|
|
// CHECK31-NEXT: store i16 [[CONV18]], i16* [[ARRAYIDX20]], align 2
|
|
// CHECK31-NEXT: br label [[OMP_BODY_CONTINUE21:%.*]]
|
|
// CHECK31: omp.body.continue21:
|
|
// CHECK31-NEXT: br label [[OMP_INNER_FOR_INC22:%.*]]
|
|
// CHECK31: omp.inner.for.inc22:
|
|
// CHECK31-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK31-NEXT: [[ADD23:%.*]] = add i64 [[TMP20]], 1
|
|
// CHECK31-NEXT: store i64 [[ADD23]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK31-NEXT: br label [[OMP_INNER_FOR_COND8]], !llvm.loop [[LOOP23:![0-9]+]]
|
|
// CHECK31: omp.inner.for.end24:
|
|
// CHECK31-NEXT: br label [[OMP_IF_END]]
|
|
// CHECK31: omp_if.end:
|
|
// CHECK31-NEXT: store i64 400, i64* [[IT]], align 8
|
|
// CHECK31-NEXT: [[TMP21:%.*]] = mul nsw i32 1, [[TMP1]]
|
|
// CHECK31-NEXT: [[ARRAYIDX25:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP21]]
|
|
// CHECK31-NEXT: [[ARRAYIDX26:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX25]], i32 1
|
|
// CHECK31-NEXT: [[TMP22:%.*]] = load i16, i16* [[ARRAYIDX26]], align 2
|
|
// CHECK31-NEXT: [[CONV27:%.*]] = sext i16 [[TMP22]] to i32
|
|
// CHECK31-NEXT: [[TMP23:%.*]] = load i32, i32* [[B]], align 4
|
|
// CHECK31-NEXT: [[ADD28:%.*]] = add nsw i32 [[CONV27]], [[TMP23]]
|
|
// CHECK31-NEXT: [[TMP24:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
|
|
// CHECK31-NEXT: call void @llvm.stackrestore(i8* [[TMP24]])
|
|
// CHECK31-NEXT: ret i32 [[ADD28]]
|
|
//
|
|
//
|
|
// CHECK31-LABEL: define {{[^@]+}}@_ZL7fstatici
|
|
// CHECK31-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
|
|
// CHECK31-NEXT: entry:
|
|
// CHECK31-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK31-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK31-NEXT: [[AA:%.*]] = alloca i16, align 2
|
|
// CHECK31-NEXT: [[AAA:%.*]] = alloca i8, align 1
|
|
// CHECK31-NEXT: [[B:%.*]] = alloca [10 x i32], align 4
|
|
// CHECK31-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK31-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK31-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK31-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK31-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK31-NEXT: store i16 0, i16* [[AA]], align 2
|
|
// CHECK31-NEXT: store i8 0, i8* [[AAA]], align 1
|
|
// CHECK31-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK31-NEXT: store i32 429496720, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK31-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK31-NEXT: ret i32 [[TMP0]]
|
|
//
|
|
//
|
|
// CHECK31-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
|
|
// CHECK31-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat {
|
|
// CHECK31-NEXT: entry:
|
|
// CHECK31-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK31-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK31-NEXT: [[AA:%.*]] = alloca i16, align 2
|
|
// CHECK31-NEXT: [[B:%.*]] = alloca [10 x i32], align 4
|
|
// CHECK31-NEXT: [[TMP:%.*]] = alloca i64, align 4
|
|
// CHECK31-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
|
|
// CHECK31-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
|
|
// CHECK31-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
|
|
// CHECK31-NEXT: [[I:%.*]] = alloca i64, align 8
|
|
// CHECK31-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK31-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK31-NEXT: store i16 0, i16* [[AA]], align 2
|
|
// CHECK31-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK31-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK31-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK31-NEXT: store i64 [[TMP0]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK31-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK31: omp.inner.for.cond:
|
|
// CHECK31-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !25
|
|
// CHECK31-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !25
|
|
// CHECK31-NEXT: [[CMP:%.*]] = icmp sle i64 [[TMP1]], [[TMP2]]
|
|
// CHECK31-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK31: omp.inner.for.body:
|
|
// CHECK31-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !25
|
|
// CHECK31-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP3]], 3
|
|
// CHECK31-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
|
|
// CHECK31-NEXT: store i64 [[ADD]], i64* [[I]], align 8, !llvm.access.group !25
|
|
// CHECK31-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !25
|
|
// CHECK31-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1
|
|
// CHECK31-NEXT: store i32 [[ADD1]], i32* [[A]], align 4, !llvm.access.group !25
|
|
// CHECK31-NEXT: [[TMP5:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !25
|
|
// CHECK31-NEXT: [[CONV:%.*]] = sext i16 [[TMP5]] to i32
|
|
// CHECK31-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 1
|
|
// CHECK31-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
|
|
// CHECK31-NEXT: store i16 [[CONV3]], i16* [[AA]], align 2, !llvm.access.group !25
|
|
// CHECK31-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2
|
|
// CHECK31-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !25
|
|
// CHECK31-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP6]], 1
|
|
// CHECK31-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !25
|
|
// CHECK31-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK31: omp.body.continue:
|
|
// CHECK31-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK31: omp.inner.for.inc:
|
|
// CHECK31-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !25
|
|
// CHECK31-NEXT: [[ADD5:%.*]] = add nsw i64 [[TMP7]], 1
|
|
// CHECK31-NEXT: store i64 [[ADD5]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !25
|
|
// CHECK31-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP26:![0-9]+]]
|
|
// CHECK31: omp.inner.for.end:
|
|
// CHECK31-NEXT: store i64 11, i64* [[I]], align 8
|
|
// CHECK31-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK31-NEXT: ret i32 [[TMP8]]
|
|
//
|
|
//
|
|
// CHECK32-LABEL: define {{[^@]+}}@_Z7get_valv
|
|
// CHECK32-SAME: () #[[ATTR0:[0-9]+]] {
|
|
// CHECK32-NEXT: entry:
|
|
// CHECK32-NEXT: ret i64 0
|
|
//
|
|
//
|
|
// CHECK32-LABEL: define {{[^@]+}}@_Z3fooi
|
|
// CHECK32-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
|
|
// CHECK32-NEXT: entry:
|
|
// CHECK32-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK32-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK32-NEXT: [[AA:%.*]] = alloca i16, align 2
|
|
// CHECK32-NEXT: [[B:%.*]] = alloca [10 x float], align 4
|
|
// CHECK32-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4
|
|
// CHECK32-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4
|
|
// CHECK32-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8
|
|
// CHECK32-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4
|
|
// CHECK32-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4
|
|
// CHECK32-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK32-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK32-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK32-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK32-NEXT: [[I:%.*]] = alloca i32, align 4
|
|
// CHECK32-NEXT: [[K:%.*]] = alloca i64, align 8
|
|
// CHECK32-NEXT: [[_TMP3:%.*]] = alloca i32, align 4
|
|
// CHECK32-NEXT: [[DOTOMP_LB4:%.*]] = alloca i32, align 4
|
|
// CHECK32-NEXT: [[DOTOMP_UB5:%.*]] = alloca i32, align 4
|
|
// CHECK32-NEXT: [[DOTOMP_IV6:%.*]] = alloca i32, align 4
|
|
// CHECK32-NEXT: [[DOTLINEAR_START:%.*]] = alloca i64, align 8
|
|
// CHECK32-NEXT: [[I7:%.*]] = alloca i32, align 4
|
|
// CHECK32-NEXT: [[K8:%.*]] = alloca i64, align 8
|
|
// CHECK32-NEXT: [[LIN:%.*]] = alloca i32, align 4
|
|
// CHECK32-NEXT: [[_TMP21:%.*]] = alloca i64, align 4
|
|
// CHECK32-NEXT: [[DOTOMP_LB22:%.*]] = alloca i64, align 8
|
|
// CHECK32-NEXT: [[DOTOMP_UB23:%.*]] = alloca i64, align 8
|
|
// CHECK32-NEXT: [[DOTOMP_IV24:%.*]] = alloca i64, align 8
|
|
// CHECK32-NEXT: [[DOTLINEAR_START25:%.*]] = alloca i32, align 4
|
|
// CHECK32-NEXT: [[DOTLINEAR_START26:%.*]] = alloca i32, align 4
|
|
// CHECK32-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8
|
|
// CHECK32-NEXT: [[IT:%.*]] = alloca i64, align 8
|
|
// CHECK32-NEXT: [[LIN28:%.*]] = alloca i32, align 4
|
|
// CHECK32-NEXT: [[A29:%.*]] = alloca i32, align 4
|
|
// CHECK32-NEXT: [[_TMP58:%.*]] = alloca i16, align 2
|
|
// CHECK32-NEXT: [[DOTOMP_LB59:%.*]] = alloca i32, align 4
|
|
// CHECK32-NEXT: [[DOTOMP_UB60:%.*]] = alloca i32, align 4
|
|
// CHECK32-NEXT: [[DOTOMP_IV61:%.*]] = alloca i32, align 4
|
|
// CHECK32-NEXT: [[IT62:%.*]] = alloca i16, align 2
|
|
// CHECK32-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
|
// CHECK32-NEXT: [[_TMP77:%.*]] = alloca i8, align 1
|
|
// CHECK32-NEXT: [[DOTOMP_LB78:%.*]] = alloca i32, align 4
|
|
// CHECK32-NEXT: [[DOTOMP_UB79:%.*]] = alloca i32, align 4
|
|
// CHECK32-NEXT: [[DOTOMP_IV80:%.*]] = alloca i32, align 4
|
|
// CHECK32-NEXT: [[IT81:%.*]] = alloca i8, align 1
|
|
// CHECK32-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK32-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK32-NEXT: store i16 0, i16* [[AA]], align 2
|
|
// CHECK32-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK32-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave()
|
|
// CHECK32-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4
|
|
// CHECK32-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4
|
|
// CHECK32-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4
|
|
// CHECK32-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK32-NEXT: [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]]
|
|
// CHECK32-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8
|
|
// CHECK32-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4
|
|
// CHECK32-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK32-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK32-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK32-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK32-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK32: omp.inner.for.cond:
|
|
// CHECK32-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
|
|
// CHECK32-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !3
|
|
// CHECK32-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
|
|
// CHECK32-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK32: omp.inner.for.body:
|
|
// CHECK32-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
|
|
// CHECK32-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5
|
|
// CHECK32-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]]
|
|
// CHECK32-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !3
|
|
// CHECK32-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK32: omp.body.continue:
|
|
// CHECK32-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK32: omp.inner.for.inc:
|
|
// CHECK32-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
|
|
// CHECK32-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
|
|
// CHECK32-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
|
|
// CHECK32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]
|
|
// CHECK32: omp.inner.for.end:
|
|
// CHECK32-NEXT: store i32 33, i32* [[I]], align 4
|
|
// CHECK32-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv()
|
|
// CHECK32-NEXT: store i64 [[CALL]], i64* [[K]], align 8
|
|
// CHECK32-NEXT: store i32 0, i32* [[DOTOMP_LB4]], align 4
|
|
// CHECK32-NEXT: store i32 8, i32* [[DOTOMP_UB5]], align 4
|
|
// CHECK32-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_LB4]], align 4
|
|
// CHECK32-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV6]], align 4
|
|
// CHECK32-NEXT: [[TMP10:%.*]] = load i64, i64* [[K]], align 8
|
|
// CHECK32-NEXT: store i64 [[TMP10]], i64* [[DOTLINEAR_START]], align 8
|
|
// CHECK32-NEXT: br label [[OMP_INNER_FOR_COND9:%.*]]
|
|
// CHECK32: omp.inner.for.cond9:
|
|
// CHECK32-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !7
|
|
// CHECK32-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB5]], align 4, !llvm.access.group !7
|
|
// CHECK32-NEXT: [[CMP10:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]]
|
|
// CHECK32-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY11:%.*]], label [[OMP_INNER_FOR_END19:%.*]]
|
|
// CHECK32: omp.inner.for.body11:
|
|
// CHECK32-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !7
|
|
// CHECK32-NEXT: [[MUL12:%.*]] = mul nsw i32 [[TMP13]], 1
|
|
// CHECK32-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL12]]
|
|
// CHECK32-NEXT: store i32 [[SUB]], i32* [[I7]], align 4, !llvm.access.group !7
|
|
// CHECK32-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8, !llvm.access.group !7
|
|
// CHECK32-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !7
|
|
// CHECK32-NEXT: [[MUL13:%.*]] = mul nsw i32 [[TMP15]], 3
|
|
// CHECK32-NEXT: [[CONV:%.*]] = sext i32 [[MUL13]] to i64
|
|
// CHECK32-NEXT: [[ADD14:%.*]] = add nsw i64 [[TMP14]], [[CONV]]
|
|
// CHECK32-NEXT: store i64 [[ADD14]], i64* [[K8]], align 8, !llvm.access.group !7
|
|
// CHECK32-NEXT: [[TMP16:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !7
|
|
// CHECK32-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP16]], 1
|
|
// CHECK32-NEXT: store i32 [[ADD15]], i32* [[A]], align 4, !llvm.access.group !7
|
|
// CHECK32-NEXT: br label [[OMP_BODY_CONTINUE16:%.*]]
|
|
// CHECK32: omp.body.continue16:
|
|
// CHECK32-NEXT: br label [[OMP_INNER_FOR_INC17:%.*]]
|
|
// CHECK32: omp.inner.for.inc17:
|
|
// CHECK32-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !7
|
|
// CHECK32-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP17]], 1
|
|
// CHECK32-NEXT: store i32 [[ADD18]], i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !7
|
|
// CHECK32-NEXT: br label [[OMP_INNER_FOR_COND9]], !llvm.loop [[LOOP8:![0-9]+]]
|
|
// CHECK32: omp.inner.for.end19:
|
|
// CHECK32-NEXT: store i32 1, i32* [[I7]], align 4
|
|
// CHECK32-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8
|
|
// CHECK32-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP18]], 27
|
|
// CHECK32-NEXT: store i64 [[ADD20]], i64* [[K]], align 8
|
|
// CHECK32-NEXT: store i32 12, i32* [[LIN]], align 4
|
|
// CHECK32-NEXT: store i64 0, i64* [[DOTOMP_LB22]], align 8
|
|
// CHECK32-NEXT: store i64 3, i64* [[DOTOMP_UB23]], align 8
|
|
// CHECK32-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_LB22]], align 8
|
|
// CHECK32-NEXT: store i64 [[TMP19]], i64* [[DOTOMP_IV24]], align 8
|
|
// CHECK32-NEXT: [[TMP20:%.*]] = load i32, i32* [[LIN]], align 4
|
|
// CHECK32-NEXT: store i32 [[TMP20]], i32* [[DOTLINEAR_START25]], align 4
|
|
// CHECK32-NEXT: [[TMP21:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK32-NEXT: store i32 [[TMP21]], i32* [[DOTLINEAR_START26]], align 4
|
|
// CHECK32-NEXT: [[CALL27:%.*]] = call i64 @_Z7get_valv()
|
|
// CHECK32-NEXT: store i64 [[CALL27]], i64* [[DOTLINEAR_STEP]], align 8
|
|
// CHECK32-NEXT: br label [[OMP_INNER_FOR_COND30:%.*]]
|
|
// CHECK32: omp.inner.for.cond30:
|
|
// CHECK32-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !10
|
|
// CHECK32-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_UB23]], align 8, !llvm.access.group !10
|
|
// CHECK32-NEXT: [[CMP31:%.*]] = icmp ule i64 [[TMP22]], [[TMP23]]
|
|
// CHECK32-NEXT: br i1 [[CMP31]], label [[OMP_INNER_FOR_BODY32:%.*]], label [[OMP_INNER_FOR_END49:%.*]]
|
|
// CHECK32: omp.inner.for.body32:
|
|
// CHECK32-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !10
|
|
// CHECK32-NEXT: [[MUL33:%.*]] = mul i64 [[TMP24]], 400
|
|
// CHECK32-NEXT: [[SUB34:%.*]] = sub i64 2000, [[MUL33]]
|
|
// CHECK32-NEXT: store i64 [[SUB34]], i64* [[IT]], align 8, !llvm.access.group !10
|
|
// CHECK32-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTLINEAR_START25]], align 4, !llvm.access.group !10
|
|
// CHECK32-NEXT: [[CONV35:%.*]] = sext i32 [[TMP25]] to i64
|
|
// CHECK32-NEXT: [[TMP26:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !10
|
|
// CHECK32-NEXT: [[TMP27:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !10
|
|
// CHECK32-NEXT: [[MUL36:%.*]] = mul i64 [[TMP26]], [[TMP27]]
|
|
// CHECK32-NEXT: [[ADD37:%.*]] = add i64 [[CONV35]], [[MUL36]]
|
|
// CHECK32-NEXT: [[CONV38:%.*]] = trunc i64 [[ADD37]] to i32
|
|
// CHECK32-NEXT: store i32 [[CONV38]], i32* [[LIN28]], align 4, !llvm.access.group !10
|
|
// CHECK32-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTLINEAR_START26]], align 4, !llvm.access.group !10
|
|
// CHECK32-NEXT: [[CONV39:%.*]] = sext i32 [[TMP28]] to i64
|
|
// CHECK32-NEXT: [[TMP29:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !10
|
|
// CHECK32-NEXT: [[TMP30:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !10
|
|
// CHECK32-NEXT: [[MUL40:%.*]] = mul i64 [[TMP29]], [[TMP30]]
|
|
// CHECK32-NEXT: [[ADD41:%.*]] = add i64 [[CONV39]], [[MUL40]]
|
|
// CHECK32-NEXT: [[CONV42:%.*]] = trunc i64 [[ADD41]] to i32
|
|
// CHECK32-NEXT: store i32 [[CONV42]], i32* [[A29]], align 4, !llvm.access.group !10
|
|
// CHECK32-NEXT: [[TMP31:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !10
|
|
// CHECK32-NEXT: [[CONV43:%.*]] = sext i16 [[TMP31]] to i32
|
|
// CHECK32-NEXT: [[ADD44:%.*]] = add nsw i32 [[CONV43]], 1
|
|
// CHECK32-NEXT: [[CONV45:%.*]] = trunc i32 [[ADD44]] to i16
|
|
// CHECK32-NEXT: store i16 [[CONV45]], i16* [[AA]], align 2, !llvm.access.group !10
|
|
// CHECK32-NEXT: br label [[OMP_BODY_CONTINUE46:%.*]]
|
|
// CHECK32: omp.body.continue46:
|
|
// CHECK32-NEXT: br label [[OMP_INNER_FOR_INC47:%.*]]
|
|
// CHECK32: omp.inner.for.inc47:
|
|
// CHECK32-NEXT: [[TMP32:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !10
|
|
// CHECK32-NEXT: [[ADD48:%.*]] = add i64 [[TMP32]], 1
|
|
// CHECK32-NEXT: store i64 [[ADD48]], i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !10
|
|
// CHECK32-NEXT: br label [[OMP_INNER_FOR_COND30]], !llvm.loop [[LOOP11:![0-9]+]]
|
|
// CHECK32: omp.inner.for.end49:
|
|
// CHECK32-NEXT: store i64 400, i64* [[IT]], align 8
|
|
// CHECK32-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTLINEAR_START25]], align 4
|
|
// CHECK32-NEXT: [[CONV50:%.*]] = sext i32 [[TMP33]] to i64
|
|
// CHECK32-NEXT: [[TMP34:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
|
|
// CHECK32-NEXT: [[MUL51:%.*]] = mul i64 4, [[TMP34]]
|
|
// CHECK32-NEXT: [[ADD52:%.*]] = add i64 [[CONV50]], [[MUL51]]
|
|
// CHECK32-NEXT: [[CONV53:%.*]] = trunc i64 [[ADD52]] to i32
|
|
// CHECK32-NEXT: store i32 [[CONV53]], i32* [[LIN]], align 4
|
|
// CHECK32-NEXT: [[TMP35:%.*]] = load i32, i32* [[DOTLINEAR_START26]], align 4
|
|
// CHECK32-NEXT: [[CONV54:%.*]] = sext i32 [[TMP35]] to i64
|
|
// CHECK32-NEXT: [[TMP36:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
|
|
// CHECK32-NEXT: [[MUL55:%.*]] = mul i64 4, [[TMP36]]
|
|
// CHECK32-NEXT: [[ADD56:%.*]] = add i64 [[CONV54]], [[MUL55]]
|
|
// CHECK32-NEXT: [[CONV57:%.*]] = trunc i64 [[ADD56]] to i32
|
|
// CHECK32-NEXT: store i32 [[CONV57]], i32* [[A]], align 4
|
|
// CHECK32-NEXT: store i32 0, i32* [[DOTOMP_LB59]], align 4
|
|
// CHECK32-NEXT: store i32 3, i32* [[DOTOMP_UB60]], align 4
|
|
// CHECK32-NEXT: [[TMP37:%.*]] = load i32, i32* [[DOTOMP_LB59]], align 4
|
|
// CHECK32-NEXT: store i32 [[TMP37]], i32* [[DOTOMP_IV61]], align 4
|
|
// CHECK32-NEXT: br label [[OMP_INNER_FOR_COND63:%.*]]
|
|
// CHECK32: omp.inner.for.cond63:
|
|
// CHECK32-NEXT: [[TMP38:%.*]] = load i32, i32* [[DOTOMP_IV61]], align 4, !llvm.access.group !13
|
|
// CHECK32-NEXT: [[TMP39:%.*]] = load i32, i32* [[DOTOMP_UB60]], align 4, !llvm.access.group !13
|
|
// CHECK32-NEXT: [[CMP64:%.*]] = icmp sle i32 [[TMP38]], [[TMP39]]
|
|
// CHECK32-NEXT: br i1 [[CMP64]], label [[OMP_INNER_FOR_BODY65:%.*]], label [[OMP_INNER_FOR_END76:%.*]]
|
|
// CHECK32: omp.inner.for.body65:
|
|
// CHECK32-NEXT: [[TMP40:%.*]] = load i32, i32* [[DOTOMP_IV61]], align 4, !llvm.access.group !13
|
|
// CHECK32-NEXT: [[MUL66:%.*]] = mul nsw i32 [[TMP40]], 4
|
|
// CHECK32-NEXT: [[ADD67:%.*]] = add nsw i32 6, [[MUL66]]
|
|
// CHECK32-NEXT: [[CONV68:%.*]] = trunc i32 [[ADD67]] to i16
|
|
// CHECK32-NEXT: store i16 [[CONV68]], i16* [[IT62]], align 2, !llvm.access.group !13
|
|
// CHECK32-NEXT: [[TMP41:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !13
|
|
// CHECK32-NEXT: [[ADD69:%.*]] = add nsw i32 [[TMP41]], 1
|
|
// CHECK32-NEXT: store i32 [[ADD69]], i32* [[A]], align 4, !llvm.access.group !13
|
|
// CHECK32-NEXT: [[TMP42:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !13
|
|
// CHECK32-NEXT: [[CONV70:%.*]] = sext i16 [[TMP42]] to i32
|
|
// CHECK32-NEXT: [[ADD71:%.*]] = add nsw i32 [[CONV70]], 1
|
|
// CHECK32-NEXT: [[CONV72:%.*]] = trunc i32 [[ADD71]] to i16
|
|
// CHECK32-NEXT: store i16 [[CONV72]], i16* [[AA]], align 2, !llvm.access.group !13
|
|
// CHECK32-NEXT: br label [[OMP_BODY_CONTINUE73:%.*]]
|
|
// CHECK32: omp.body.continue73:
|
|
// CHECK32-NEXT: br label [[OMP_INNER_FOR_INC74:%.*]]
|
|
// CHECK32: omp.inner.for.inc74:
|
|
// CHECK32-NEXT: [[TMP43:%.*]] = load i32, i32* [[DOTOMP_IV61]], align 4, !llvm.access.group !13
|
|
// CHECK32-NEXT: [[ADD75:%.*]] = add nsw i32 [[TMP43]], 1
|
|
// CHECK32-NEXT: store i32 [[ADD75]], i32* [[DOTOMP_IV61]], align 4, !llvm.access.group !13
|
|
// CHECK32-NEXT: br label [[OMP_INNER_FOR_COND63]], !llvm.loop [[LOOP14:![0-9]+]]
|
|
// CHECK32: omp.inner.for.end76:
|
|
// CHECK32-NEXT: store i16 22, i16* [[IT62]], align 2
|
|
// CHECK32-NEXT: [[TMP44:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK32-NEXT: store i32 [[TMP44]], i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK32-NEXT: store i32 0, i32* [[DOTOMP_LB78]], align 4
|
|
// CHECK32-NEXT: store i32 25, i32* [[DOTOMP_UB79]], align 4
|
|
// CHECK32-NEXT: [[TMP45:%.*]] = load i32, i32* [[DOTOMP_LB78]], align 4
|
|
// CHECK32-NEXT: store i32 [[TMP45]], i32* [[DOTOMP_IV80]], align 4
|
|
// CHECK32-NEXT: br label [[OMP_INNER_FOR_COND82:%.*]]
|
|
// CHECK32: omp.inner.for.cond82:
|
|
// CHECK32-NEXT: [[TMP46:%.*]] = load i32, i32* [[DOTOMP_IV80]], align 4, !llvm.access.group !16
|
|
// CHECK32-NEXT: [[TMP47:%.*]] = load i32, i32* [[DOTOMP_UB79]], align 4, !llvm.access.group !16
|
|
// CHECK32-NEXT: [[CMP83:%.*]] = icmp sle i32 [[TMP46]], [[TMP47]]
|
|
// CHECK32-NEXT: br i1 [[CMP83]], label [[OMP_INNER_FOR_BODY84:%.*]], label [[OMP_INNER_FOR_END109:%.*]]
|
|
// CHECK32: omp.inner.for.body84:
|
|
// CHECK32-NEXT: [[TMP48:%.*]] = load i32, i32* [[DOTOMP_IV80]], align 4, !llvm.access.group !16
|
|
// CHECK32-NEXT: [[MUL85:%.*]] = mul nsw i32 [[TMP48]], 1
|
|
// CHECK32-NEXT: [[SUB86:%.*]] = sub nsw i32 122, [[MUL85]]
|
|
// CHECK32-NEXT: [[CONV87:%.*]] = trunc i32 [[SUB86]] to i8
|
|
// CHECK32-NEXT: store i8 [[CONV87]], i8* [[IT81]], align 1, !llvm.access.group !16
|
|
// CHECK32-NEXT: [[TMP49:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !16
|
|
// CHECK32-NEXT: [[ADD88:%.*]] = add nsw i32 [[TMP49]], 1
|
|
// CHECK32-NEXT: store i32 [[ADD88]], i32* [[A]], align 4, !llvm.access.group !16
|
|
// CHECK32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 2
|
|
// CHECK32-NEXT: [[TMP50:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !16
|
|
// CHECK32-NEXT: [[CONV89:%.*]] = fpext float [[TMP50]] to double
|
|
// CHECK32-NEXT: [[ADD90:%.*]] = fadd double [[CONV89]], 1.000000e+00
|
|
// CHECK32-NEXT: [[CONV91:%.*]] = fptrunc double [[ADD90]] to float
|
|
// CHECK32-NEXT: store float [[CONV91]], float* [[ARRAYIDX]], align 4, !llvm.access.group !16
|
|
// CHECK32-NEXT: [[ARRAYIDX92:%.*]] = getelementptr inbounds float, float* [[VLA]], i32 3
|
|
// CHECK32-NEXT: [[TMP51:%.*]] = load float, float* [[ARRAYIDX92]], align 4, !llvm.access.group !16
|
|
// CHECK32-NEXT: [[CONV93:%.*]] = fpext float [[TMP51]] to double
|
|
// CHECK32-NEXT: [[ADD94:%.*]] = fadd double [[CONV93]], 1.000000e+00
|
|
// CHECK32-NEXT: [[CONV95:%.*]] = fptrunc double [[ADD94]] to float
|
|
// CHECK32-NEXT: store float [[CONV95]], float* [[ARRAYIDX92]], align 4, !llvm.access.group !16
|
|
// CHECK32-NEXT: [[ARRAYIDX96:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i32 0, i32 1
|
|
// CHECK32-NEXT: [[ARRAYIDX97:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX96]], i32 0, i32 2
|
|
// CHECK32-NEXT: [[TMP52:%.*]] = load double, double* [[ARRAYIDX97]], align 8, !llvm.access.group !16
|
|
// CHECK32-NEXT: [[ADD98:%.*]] = fadd double [[TMP52]], 1.000000e+00
|
|
// CHECK32-NEXT: store double [[ADD98]], double* [[ARRAYIDX97]], align 8, !llvm.access.group !16
|
|
// CHECK32-NEXT: [[TMP53:%.*]] = mul nsw i32 1, [[TMP2]]
|
|
// CHECK32-NEXT: [[ARRAYIDX99:%.*]] = getelementptr inbounds double, double* [[VLA1]], i32 [[TMP53]]
|
|
// CHECK32-NEXT: [[ARRAYIDX100:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX99]], i32 3
|
|
// CHECK32-NEXT: [[TMP54:%.*]] = load double, double* [[ARRAYIDX100]], align 8, !llvm.access.group !16
|
|
// CHECK32-NEXT: [[ADD101:%.*]] = fadd double [[TMP54]], 1.000000e+00
|
|
// CHECK32-NEXT: store double [[ADD101]], double* [[ARRAYIDX100]], align 8, !llvm.access.group !16
|
|
// CHECK32-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0
|
|
// CHECK32-NEXT: [[TMP55:%.*]] = load i64, i64* [[X]], align 4, !llvm.access.group !16
|
|
// CHECK32-NEXT: [[ADD102:%.*]] = add nsw i64 [[TMP55]], 1
|
|
// CHECK32-NEXT: store i64 [[ADD102]], i64* [[X]], align 4, !llvm.access.group !16
|
|
// CHECK32-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1
|
|
// CHECK32-NEXT: [[TMP56:%.*]] = load i8, i8* [[Y]], align 4, !llvm.access.group !16
|
|
// CHECK32-NEXT: [[CONV103:%.*]] = sext i8 [[TMP56]] to i32
|
|
// CHECK32-NEXT: [[ADD104:%.*]] = add nsw i32 [[CONV103]], 1
|
|
// CHECK32-NEXT: [[CONV105:%.*]] = trunc i32 [[ADD104]] to i8
|
|
// CHECK32-NEXT: store i8 [[CONV105]], i8* [[Y]], align 4, !llvm.access.group !16
|
|
// CHECK32-NEXT: br label [[OMP_BODY_CONTINUE106:%.*]]
|
|
// CHECK32: omp.body.continue106:
|
|
// CHECK32-NEXT: br label [[OMP_INNER_FOR_INC107:%.*]]
|
|
// CHECK32: omp.inner.for.inc107:
|
|
// CHECK32-NEXT: [[TMP57:%.*]] = load i32, i32* [[DOTOMP_IV80]], align 4, !llvm.access.group !16
|
|
// CHECK32-NEXT: [[ADD108:%.*]] = add nsw i32 [[TMP57]], 1
|
|
// CHECK32-NEXT: store i32 [[ADD108]], i32* [[DOTOMP_IV80]], align 4, !llvm.access.group !16
|
|
// CHECK32-NEXT: br label [[OMP_INNER_FOR_COND82]], !llvm.loop [[LOOP17:![0-9]+]]
|
|
// CHECK32: omp.inner.for.end109:
|
|
// CHECK32-NEXT: store i8 96, i8* [[IT81]], align 1
|
|
// CHECK32-NEXT: [[TMP58:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK32-NEXT: [[TMP59:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
|
|
// CHECK32-NEXT: call void @llvm.stackrestore(i8* [[TMP59]])
|
|
// CHECK32-NEXT: ret i32 [[TMP58]]
|
|
//
|
|
//
|
|
// CHECK32-LABEL: define {{[^@]+}}@_Z3bari
|
|
// CHECK32-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
|
|
// CHECK32-NEXT: entry:
|
|
// CHECK32-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK32-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK32-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4
|
|
// CHECK32-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK32-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK32-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK32-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]])
|
|
// CHECK32-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK32-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
|
|
// CHECK32-NEXT: store i32 [[ADD]], i32* [[A]], align 4
|
|
// CHECK32-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK32-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]])
|
|
// CHECK32-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK32-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
|
|
// CHECK32-NEXT: store i32 [[ADD2]], i32* [[A]], align 4
|
|
// CHECK32-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK32-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]])
|
|
// CHECK32-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK32-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
|
|
// CHECK32-NEXT: store i32 [[ADD4]], i32* [[A]], align 4
|
|
// CHECK32-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK32-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]])
|
|
// CHECK32-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK32-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
|
|
// CHECK32-NEXT: store i32 [[ADD6]], i32* [[A]], align 4
|
|
// CHECK32-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK32-NEXT: ret i32 [[TMP8]]
|
|
//
|
|
//
|
|
// CHECK32-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
|
|
// CHECK32-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 {
|
|
// CHECK32-NEXT: entry:
|
|
// CHECK32-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
|
|
// CHECK32-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK32-NEXT: [[B:%.*]] = alloca i32, align 4
|
|
// CHECK32-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4
|
|
// CHECK32-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4
|
|
// CHECK32-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
|
|
// CHECK32-NEXT: [[TMP:%.*]] = alloca i64, align 4
|
|
// CHECK32-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
|
|
// CHECK32-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
|
|
// CHECK32-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
|
|
// CHECK32-NEXT: [[IT:%.*]] = alloca i64, align 8
|
|
// CHECK32-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK32-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK32-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK32-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK32-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
|
|
// CHECK32-NEXT: store i32 [[ADD]], i32* [[B]], align 4
|
|
// CHECK32-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK32-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave()
|
|
// CHECK32-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4
|
|
// CHECK32-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]]
|
|
// CHECK32-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2
|
|
// CHECK32-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4
|
|
// CHECK32-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK32-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 60
|
|
// CHECK32-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8
|
|
// CHECK32-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
|
|
// CHECK32-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK32-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK32-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK32-NEXT: store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK32-NEXT: [[TMP6:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
|
|
// CHECK32-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP6]] to i1
|
|
// CHECK32-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
|
|
// CHECK32: omp_if.then:
|
|
// CHECK32-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK32: omp.inner.for.cond:
|
|
// CHECK32-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !19
|
|
// CHECK32-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !19
|
|
// CHECK32-NEXT: [[CMP2:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]]
|
|
// CHECK32-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK32: omp.inner.for.body:
|
|
// CHECK32-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !19
|
|
// CHECK32-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400
|
|
// CHECK32-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]
|
|
// CHECK32-NEXT: store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !19
|
|
// CHECK32-NEXT: [[TMP10:%.*]] = load i32, i32* [[B]], align 4, !llvm.access.group !19
|
|
// CHECK32-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP10]] to double
|
|
// CHECK32-NEXT: [[ADD3:%.*]] = fadd double [[CONV]], 1.500000e+00
|
|
// CHECK32-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
|
|
// CHECK32-NEXT: store double [[ADD3]], double* [[A]], align 4, !nontemporal !20, !llvm.access.group !19
|
|
// CHECK32-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
|
|
// CHECK32-NEXT: [[TMP11:%.*]] = load double, double* [[A4]], align 4, !nontemporal !20, !llvm.access.group !19
|
|
// CHECK32-NEXT: [[INC:%.*]] = fadd double [[TMP11]], 1.000000e+00
|
|
// CHECK32-NEXT: store double [[INC]], double* [[A4]], align 4, !nontemporal !20, !llvm.access.group !19
|
|
// CHECK32-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16
|
|
// CHECK32-NEXT: [[TMP12:%.*]] = mul nsw i32 1, [[TMP1]]
|
|
// CHECK32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP12]]
|
|
// CHECK32-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
|
|
// CHECK32-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2, !llvm.access.group !19
|
|
// CHECK32-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK32: omp.body.continue:
|
|
// CHECK32-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK32: omp.inner.for.inc:
|
|
// CHECK32-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !19
|
|
// CHECK32-NEXT: [[ADD7:%.*]] = add i64 [[TMP13]], 1
|
|
// CHECK32-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !19
|
|
// CHECK32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]]
|
|
// CHECK32: omp.inner.for.end:
|
|
// CHECK32-NEXT: br label [[OMP_IF_END:%.*]]
|
|
// CHECK32: omp_if.else:
|
|
// CHECK32-NEXT: br label [[OMP_INNER_FOR_COND8:%.*]]
|
|
// CHECK32: omp.inner.for.cond8:
|
|
// CHECK32-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK32-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK32-NEXT: [[CMP9:%.*]] = icmp ule i64 [[TMP14]], [[TMP15]]
|
|
// CHECK32-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY10:%.*]], label [[OMP_INNER_FOR_END24:%.*]]
|
|
// CHECK32: omp.inner.for.body10:
|
|
// CHECK32-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK32-NEXT: [[MUL11:%.*]] = mul i64 [[TMP16]], 400
|
|
// CHECK32-NEXT: [[SUB12:%.*]] = sub i64 2000, [[MUL11]]
|
|
// CHECK32-NEXT: store i64 [[SUB12]], i64* [[IT]], align 8
|
|
// CHECK32-NEXT: [[TMP17:%.*]] = load i32, i32* [[B]], align 4
|
|
// CHECK32-NEXT: [[CONV13:%.*]] = sitofp i32 [[TMP17]] to double
|
|
// CHECK32-NEXT: [[ADD14:%.*]] = fadd double [[CONV13]], 1.500000e+00
|
|
// CHECK32-NEXT: [[A15:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
|
|
// CHECK32-NEXT: store double [[ADD14]], double* [[A15]], align 4
|
|
// CHECK32-NEXT: [[A16:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
|
|
// CHECK32-NEXT: [[TMP18:%.*]] = load double, double* [[A16]], align 4
|
|
// CHECK32-NEXT: [[INC17:%.*]] = fadd double [[TMP18]], 1.000000e+00
|
|
// CHECK32-NEXT: store double [[INC17]], double* [[A16]], align 4
|
|
// CHECK32-NEXT: [[CONV18:%.*]] = fptosi double [[INC17]] to i16
|
|
// CHECK32-NEXT: [[TMP19:%.*]] = mul nsw i32 1, [[TMP1]]
|
|
// CHECK32-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP19]]
|
|
// CHECK32-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX19]], i32 1
|
|
// CHECK32-NEXT: store i16 [[CONV18]], i16* [[ARRAYIDX20]], align 2
|
|
// CHECK32-NEXT: br label [[OMP_BODY_CONTINUE21:%.*]]
|
|
// CHECK32: omp.body.continue21:
|
|
// CHECK32-NEXT: br label [[OMP_INNER_FOR_INC22:%.*]]
|
|
// CHECK32: omp.inner.for.inc22:
|
|
// CHECK32-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK32-NEXT: [[ADD23:%.*]] = add i64 [[TMP20]], 1
|
|
// CHECK32-NEXT: store i64 [[ADD23]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK32-NEXT: br label [[OMP_INNER_FOR_COND8]], !llvm.loop [[LOOP23:![0-9]+]]
|
|
// CHECK32: omp.inner.for.end24:
|
|
// CHECK32-NEXT: br label [[OMP_IF_END]]
|
|
// CHECK32: omp_if.end:
|
|
// CHECK32-NEXT: store i64 400, i64* [[IT]], align 8
|
|
// CHECK32-NEXT: [[TMP21:%.*]] = mul nsw i32 1, [[TMP1]]
|
|
// CHECK32-NEXT: [[ARRAYIDX25:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP21]]
|
|
// CHECK32-NEXT: [[ARRAYIDX26:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX25]], i32 1
|
|
// CHECK32-NEXT: [[TMP22:%.*]] = load i16, i16* [[ARRAYIDX26]], align 2
|
|
// CHECK32-NEXT: [[CONV27:%.*]] = sext i16 [[TMP22]] to i32
|
|
// CHECK32-NEXT: [[TMP23:%.*]] = load i32, i32* [[B]], align 4
|
|
// CHECK32-NEXT: [[ADD28:%.*]] = add nsw i32 [[CONV27]], [[TMP23]]
|
|
// CHECK32-NEXT: [[TMP24:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
|
|
// CHECK32-NEXT: call void @llvm.stackrestore(i8* [[TMP24]])
|
|
// CHECK32-NEXT: ret i32 [[ADD28]]
|
|
//
|
|
//
|
|
// CHECK32-LABEL: define {{[^@]+}}@_ZL7fstatici
|
|
// CHECK32-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
|
|
// CHECK32-NEXT: entry:
|
|
// CHECK32-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK32-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK32-NEXT: [[AA:%.*]] = alloca i16, align 2
|
|
// CHECK32-NEXT: [[AAA:%.*]] = alloca i8, align 1
|
|
// CHECK32-NEXT: [[B:%.*]] = alloca [10 x i32], align 4
|
|
// CHECK32-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK32-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK32-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK32-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK32-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK32-NEXT: store i16 0, i16* [[AA]], align 2
|
|
// CHECK32-NEXT: store i8 0, i8* [[AAA]], align 1
|
|
// CHECK32-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK32-NEXT: store i32 429496720, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK32-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK32-NEXT: ret i32 [[TMP0]]
|
|
//
|
|
//
|
|
// CHECK32-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
|
|
// CHECK32-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat {
|
|
// CHECK32-NEXT: entry:
|
|
// CHECK32-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK32-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK32-NEXT: [[AA:%.*]] = alloca i16, align 2
|
|
// CHECK32-NEXT: [[B:%.*]] = alloca [10 x i32], align 4
|
|
// CHECK32-NEXT: [[TMP:%.*]] = alloca i64, align 4
|
|
// CHECK32-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
|
|
// CHECK32-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
|
|
// CHECK32-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
|
|
// CHECK32-NEXT: [[I:%.*]] = alloca i64, align 8
|
|
// CHECK32-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK32-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK32-NEXT: store i16 0, i16* [[AA]], align 2
|
|
// CHECK32-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK32-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK32-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK32-NEXT: store i64 [[TMP0]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK32-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK32: omp.inner.for.cond:
|
|
// CHECK32-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !25
|
|
// CHECK32-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !25
|
|
// CHECK32-NEXT: [[CMP:%.*]] = icmp sle i64 [[TMP1]], [[TMP2]]
|
|
// CHECK32-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK32: omp.inner.for.body:
|
|
// CHECK32-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !25
|
|
// CHECK32-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP3]], 3
|
|
// CHECK32-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
|
|
// CHECK32-NEXT: store i64 [[ADD]], i64* [[I]], align 8, !llvm.access.group !25
|
|
// CHECK32-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !25
|
|
// CHECK32-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1
|
|
// CHECK32-NEXT: store i32 [[ADD1]], i32* [[A]], align 4, !llvm.access.group !25
|
|
// CHECK32-NEXT: [[TMP5:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !25
|
|
// CHECK32-NEXT: [[CONV:%.*]] = sext i16 [[TMP5]] to i32
|
|
// CHECK32-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 1
|
|
// CHECK32-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
|
|
// CHECK32-NEXT: store i16 [[CONV3]], i16* [[AA]], align 2, !llvm.access.group !25
|
|
// CHECK32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2
|
|
// CHECK32-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !25
|
|
// CHECK32-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP6]], 1
|
|
// CHECK32-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !25
|
|
// CHECK32-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK32: omp.body.continue:
|
|
// CHECK32-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK32: omp.inner.for.inc:
|
|
// CHECK32-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !25
|
|
// CHECK32-NEXT: [[ADD5:%.*]] = add nsw i64 [[TMP7]], 1
|
|
// CHECK32-NEXT: store i64 [[ADD5]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !25
|
|
// CHECK32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP26:![0-9]+]]
|
|
// CHECK32: omp.inner.for.end:
|
|
// CHECK32-NEXT: store i64 11, i64* [[I]], align 8
|
|
// CHECK32-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4
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// CHECK32-NEXT: ret i32 [[TMP8]]
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//
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