llvm/mlir/tools
AlexEichenberger 01641197ee [MLIR] Remove TableGen redundant calls to native calls when creating new operations in DRR TableGen files
Summary:
Currently, the TableGen rewrite generates redundant native calls in MLIR DRR files. This is a problem as some native calls may involve significant computations (e.g. when performing constant propagation where every values in a large tensor is touched).

The pattern was as follow:

```c++
if (native-call(args)) tblgen_attrs.emplace_back(rewriter, attribute, native-call(args))
```

The replacement pattern compute `native-call(args)` once and then use it both in the `if` condition and the `emplace_back` call.

Differential Revision: https://reviews.llvm.org/D82101
2020-06-22 08:12:04 -07:00
..
mlir-cpu-runner
mlir-cuda-runner Unbreak the build of mlir-cuda-runner 2020-05-29 12:18:48 +02:00
mlir-linalg-ods-gen [mlir][Linalg] Retire C++ MatmulOp in favor of a linalg-ods-gen'd op. 2020-06-16 10:46:35 -04:00
mlir-opt [mlir] Add support for lowering tanh to LLVMIR. 2020-06-18 10:42:13 -07:00
mlir-rocm-runner [mlir][mlir-rocm-runner] Detect HIP version and AMD ISA version. 2020-06-05 22:15:23 -05:00
mlir-shlib
mlir-tblgen [MLIR] Remove TableGen redundant calls to native calls when creating new operations in DRR TableGen files 2020-06-22 08:12:04 -07:00
mlir-translate
mlir-vulkan-runner [mlir][vulkan-runner] add support for memref of i8, i16 types in vulkan runner 2020-06-18 13:24:51 -07:00
CMakeLists.txt [mlir][gpu] Introduce mlir-rocm-runner. 2020-06-05 09:46:39 -05:00