Commit graph

416134 commits

Author SHA1 Message Date
Damian Rouson 95fd0dbaf0 [flang] add semantics test for sync memory
Test a range of acceptable forms of SYNC MEMORY statements,
including combinations with and without the stat-variable
and errmsg-variable present.  Also test that several invalid
forms of SYNC MEMORY call generate the correct error messages.

Differential Revision: https://reviews.llvm.org/D120097
2022-02-24 11:04:00 -08:00
Momchil Velikov 17e85cd410 [AArch64] Async unwind - Always place the first LDP at the end when ReverseCSRRestoreSeq is true
This patch is in preparation for the async unwind CFI.

Put the first `LDP` the end, so that the load-store optimizer can run
and merge the `LDP` and the `ADD` into a post-index `LDP`.

Do this always and as early as at the time of the initial creation of
the CSR restore instructions, even if that `LDP` is not guaranteed to
be mergeable with a subsequent `SP` increment.

This greatly simplifies the CFI generation for prologue, as otherwise
we have to take extra steps to ensure reordering does not cross CFI
instructions.

Reviewed By: danielkiss

Differential Revision: https://reviews.llvm.org/D112328
2022-02-24 18:48:07 +00:00
Stanislav Mekhanoshin cefa1c5ca9 [AMDGPU] Fix combined MMO in load-store merge
Loads and stores can be out of order in the SILoadStoreOptimizer.
When combining MachineMemOperands of two instructions operands are
sent in the IR order into the combineKnownAdjacentMMOs. At the
moment it picks the first operand and just replaces its offset and
size. This essentially loses alignment information and may generally
result in an incorrect base pointer to be used.

Use a base pointer in memory addresses order instead and only adjust
size.

Differential Revision: https://reviews.llvm.org/D120370
2022-02-24 10:47:57 -08:00
Amir Ayupov e38fc14c43 [X86] Introduce x86-cmov-converter-force-all
Introduce an option to expand all CMOV groups into hammocks, matching GCC's
`-fno-if-conversion2` flag. The motivation is to leave CMOV conversion
opportunities to a binary optimizer that can make the decision based on branch
misprediction rate (available e.g. in Intel's LBR).

Reviewed By: MaskRay, skan

Differential Revision: https://reviews.llvm.org/D119777
2022-02-24 10:47:22 -08:00
Benjamin Kramer dc7a624e38 [tblgen] Compress CompositeSequences to 1/8th of its size. NFCI. 2022-02-24 19:31:33 +01:00
Craig Topper 2aa1c6fca1 [RISCV] Add Zbb RUN lines to neg-abs.ll. 2022-02-24 10:21:10 -08:00
Momchil Velikov 25e92920c9 [AArch64] Async unwind - helper functions to decide on CFI emission
Reviewed By: efriedma

Differential Revision: https://reviews.llvm.org/D112327
2022-02-24 18:16:50 +00:00
Fangrui Song ecff9b65b5 [analyzer] Just use default capture after 7fd60ee6e0 2022-02-24 10:06:11 -08:00
Thomas Raoux b1357fe618 [mlir][memref] Add transformation to do loop multi-buffering
This transformation is useful to break dependency between consecutive loop
iterations by increasing the size of a temporary buffer. This is usually
combined with heavy software pipelining.

Differential Revision: https://reviews.llvm.org/D119406
2022-02-24 09:41:21 -08:00
Craig Topper f69078b77f [RISCV] Update some tests to use floating point ABI where it makes sense.
Trying to reduce the diffs from D118333 for cases where it makes
more sense to use an FP ABI.

Reviewed By: asb, kito-cheng

Differential Revision: https://reviews.llvm.org/D120447
2022-02-24 09:27:57 -08:00
Momchil Velikov fd7e59f0e7 [AArch64] Async unwind - do not schedule frame setup/destroy
The PostRA scheduler can reorder non-CFI instructions in a way that
makes the unwind info not instruction precise.

Reviewed By: efriedma

Differential Revision: https://reviews.llvm.org/D112326
2022-02-24 17:24:04 +00:00
Craig Topper a975ca97c3 [RISCV] Fold (sext_inreg (fmv_x_anyexth X), i16) -> (fmv_x_signexth X).
Add a new ISD opcode to represent the sign extending behavior of
vmv.x.h. Keep the previous anyext opcode to allow the existing
(fmv_x_anyexth (fmv_h_x X)) combine to keep working without needing
to generate a sign extend.

For fmv.x.w we are able to match the sext_inreg in an isel pattern,
but a 16-bit sext_inreg is lowered to a shift pair before isel. This
seemed like a larger match than we should do in isel.

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D118974
2022-02-24 09:19:01 -08:00
Valentin Clement 2a59ead118
[flang] Lower allocatable assignment for scalar
Add lowering for simple assignement on allocatable
scalars.

This patch is part of the upstreaming effort from fir-dev branch.

Depends on D120483

Reviewed By: PeteSteinfeld

Differential Revision: https://reviews.llvm.org/D120488

Co-authored-by: Eric Schweitz <eschweitz@nvidia.com>
Co-authored-by: Jean Perier <jperier@nvidia.com>
2022-02-24 18:13:18 +01:00
Stanislav Gatev baa0f221d6 [clang][dataflow] Update StructValue child when assigning a value
When assigning a value to a storage location of a struct member we
need to also update the value in the corresponding `StructValue`.

This is part of the implementation of the dataflow analysis framework.
See "[RFC] A dataflow analysis framework for Clang AST" on cfe-dev.

Reviewed-by: ymandel, xazax.hun

Differential Revision: https://reviews.llvm.org/D120414
2022-02-24 16:41:48 +00:00
Sven van Haastregt ba18c360b2 [clang-tidy] Remove opencl-c.h inclusion from tests
After D120254 some clang-tidy tests started failing on release builds.

clang-tidy has been using the `-fdeclare-opencl-builtins` functionality
since this became the default in clang, so there is no need to include
`opencl-c.h`.

Differential Revision: https://reviews.llvm.org/D120470
2022-02-24 16:28:52 +00:00
Sanjay Patel 4a3708cd6b [SDAG] remove shift that is redundant with part of funnel shift
This is the SDAG translation of D120253 :
https://alive2.llvm.org/ce/z/qHpmNn

The SDAG nodes can have different operand types than the result value.
We can see an example of that with AArch64 - the funnel shift amount
is an i64 rather than i32.

We may need to make that match even more flexible to handle
post-legalization nodes, but I have not stepped into that yet.

Differential Revision: https://reviews.llvm.org/D120264
2022-02-24 11:25:46 -05:00
Valentin Clement 914061bbcf
[flang] Handle allocatable dummy arguments
This patch handles allocatable dummy argument lowering
in function and subroutines.

This patch is part of the upstreaming effort from fir-dev branch.

Reviewed By: schweitz

Differential Revision: https://reviews.llvm.org/D120483

Co-authored-by: Jean Perier <jperier@nvidia.com>
2022-02-24 17:16:55 +01:00
Anton Korobeynikov 64cc8b2756 Disable Mailgun click tracking 2022-02-24 19:03:43 +03:00
Aaron Ballman 003924963f Remove useless RUN lines in the middle of the file and pipe to FileCheck; NFC 2022-02-24 11:01:33 -05:00
Joseph Huber 7aef8b3754 [OpenMP] Make section variable external to prevent collisions
Summary:
We use a section to embed offloading code into the host for later
linking. This is normally unique to the translation unit as it is thrown
away during linking. However, if the user performs a relocatable link
the sections will be merged and we won't be able to access the files
stored inside. This patch changes the section variables to have external
linkage and a name defined by the section name, so if two sections are
combined during linking we get an error.
2022-02-24 10:57:09 -05:00
Sanjay Patel 5379f76e63 [InstCombine] try harder to preserve 'nsz' in fneg-of-select transform
The corner case where 'nsz' needs to be removed is very narrow
as discussed here:
https://reviews.llvm.org/rG3cdd05e519dd

If the select condition is not undef, there's no problem with
propagating 'nsz':
https://alive2.llvm.org/ce/z/4GWJdq
2022-02-24 10:43:53 -05:00
Sanjay Patel 788b08a58c [InstCombine] add test for fneg of select with FMF; NFC 2022-02-24 10:42:25 -05:00
Jay Foad 719bac55df [MIRParser] Diagnose too large align values in MachineMemOperands
When parsing MachineMemOperands, MIRParser treated the "align" keyword
the same as "basealign". Really "basealign" should specify the
alignment of the MachinePointerInfo base value, and "align" should
specify the alignment of that base value plus the offset.

This worked OK when the specified alignment was no larger than the
alignment of the offset, but in cases like this it just caused
confusion:

    STW killed %18, 4, %stack.1.ap2.i.i :: (store (s32) into %stack.1.ap2.i.i + 4, align 8)

MIRPrinter would never have printed this, with an offset of 4 but an
align of 8, so it must have been written by hand. MIRParser would
interpret "align 8" as "basealign 8", but I think it is better to give
an error and force the user to write "basealign 8" if that is what they
really meant.

Differential Revision: https://reviews.llvm.org/D120400

Change-Id: I7eeeefc55c2df3554ba8d89f8809a2f45ada32d8
2022-02-24 15:32:08 +00:00
Marius Brehler 1fa1251116 [mlir][emitc] Add a variable op
This adds a variable op, emitted as C/C++ locale variable, which can be
used if the `emitc.constant` op is not sufficient.

As an example, the canonicalization pass would transform
```mlir
%0 = "emitc.constant"() {value = 0 : i32} : () -> i32
%1 = "emitc.constant"() {value = 0 : i32} : () -> i32
%2 = emitc.apply "&"(%0) : (i32) -> !emitc.ptr<i32>
%3 = emitc.apply "&"(%1) : (i32) -> !emitc.ptr<i32>
emitc.call "write"(%2, %3) : (!emitc.ptr<i32>, !emitc.ptr<i32>) -> ()
```
into
```mlir
%0 = "emitc.constant"() {value = 0 : i32} : () -> i32
%1 = emitc.apply "&"(%0) : (i32) -> !emitc.ptr<i32>
%2 = emitc.apply "&"(%0) : (i32) -> !emitc.ptr<i32>
emitc.call "write"(%1, %2) : (!emitc.ptr<i32>, !emitc.ptr<i32>) -> ()
```
resulting in pointer aliasing, as %1 and %2 point to the same address.
In such a case, the `emitc.variable` operation can be used instead.

Reviewed By: jpienaar

Differential Revision: https://reviews.llvm.org/D120098
2022-02-24 15:25:21 +00:00
Corentin Jabot 70b1f6de53 [clang] Warn on unqualified calls to std::move and std::forward
This adds a diagnostic when an unqualified call is resolved
to std::move or std::forward.

This follows some C++ committee discussions where some
people where concerns that this might be an usual anti pattern
particularly britle worth warning about - both because move
is a common name and because these functions accept any values.

This warns inconditionnally of whether the current context is in
std:: or not, as implementations probably want to always qualify
these calls too, to avoid triggering adl accidentally.

Differential Revision: https://reviews.llvm.org/D119670
2022-02-24 07:23:39 -08:00
Sven van Haastregt 28cdcf8e3c [OpenCL] Handle TypeExtensions in OpenCLBuiltinFileEmitter
Until now, any types that had TypeExtensions attached to them were not
guarded with those extensions.  Extend the OpenCLBuiltinFileEmitter
such that all required extensions are emitted for the types of a
builtin function.

The `clang-tblgen -gen-clang-opencl-builtin-tests` emitter will now
produce e.g.:

  #if defined(cl_khr_fp16) && defined(cl_khr_fp64)
  half8 test11802_convert_half8_rtp(double8 arg1) {
    return convert_half8_rtp(arg1);
  }
  #endif // TypeExtension

Differential Revision: https://reviews.llvm.org/D120262
2022-02-24 15:17:24 +00:00
Florian Hahn 5910150140
[AArch64] Simplify and extend tests added in 0c5ea01b20. 2022-02-24 14:51:43 +00:00
Simon Pilgrim a636801a36 [X86] LowerRotate - enable v8i16 ROTL/ROTR on all pre-SSE41 targets
We're still better off expanding this once we have PMOVZX
2022-02-24 14:14:08 +00:00
Simon Pilgrim 0ea50bee83 [X86] SimplifyDemandedVectorEltsForTargetNode - add X86ISD::ANDNP handling 2022-02-24 13:51:51 +00:00
Shraiysh Vaishay f9fbaabe0f [mlir][OpenMP][NFC] Remove unused binary operator enum
This patch removes binary operator enum which was introduced with `omp.atomic.update`. Now the update operation handles update in a region so this is no longer required.

Reviewed By: kiranchandramohan

Differential Revision: https://reviews.llvm.org/D120458
2022-02-24 19:06:10 +05:30
Benjamin Kramer 1e396affca [Symbolizer] Move ctor/dtor into .cpp file
On some standard library configurations these have a dependency on the
complete type of SymbolizableModule. They also do a lot of
copying/freeing so no point in inlining them.
2022-02-24 14:20:15 +01:00
Alex Zinenko 5146067578 [mlir] Document creation of Python bindings for a dialect
Documentation exists about the details of the API but is missing a
description of the overall structure per dialect.

Reviewed By: shabalin

Differential Revision: https://reviews.llvm.org/D117002
2022-02-24 14:18:56 +01:00
Benjamin Kramer 92cf9f1481 [mlir][linalg] Cast back to the original type after making linalg.generic outputs more static
This codepath was entirely untested.

Differential Revision: https://reviews.llvm.org/D120473
2022-02-24 13:35:54 +01:00
Roman Lebedev 67388b0013
[NFC][SROA] Update tests for D113520 2022-02-24 15:31:12 +03:00
serge-sans-paille fc97efa409 Cleanup includes: ProfileData
Estimation of the impact on preprocessor output:

before: 1067349756
after: 1065940348

Discourse thread: https://discourse.llvm.org/t/include-what-you-use-include-cleanup
Differential Revision: https://reviews.llvm.org/D120434
2022-02-24 13:25:11 +01:00
serge-sans-paille db29f4374d Cleanup include: DebugInfo/Symbolize
Estimation of the impact on preprocessor output
after: 1067349756
before:1067487786

Discourse thread: https://discourse.llvm.org/t/include-what-you-use-include-cleanup
Differential Revision: https://reviews.llvm.org/D120433
2022-02-24 13:25:11 +01:00
Jay Foad aa1e5fbc9b [AMDGPU] Fix permissions on test files 2022-02-24 12:17:54 +00:00
Florian Hahn 0c5ea01b20
[AArch64] Add vector select test showing redundant operations.
The tests show sub-optimal lowering of extend/cmp/select chains starting
with v16i8 vectors.
2022-02-24 12:12:21 +00:00
Shao-Ce SUN 78b5f0fb05 [NFC][RISCV] Reuse ISD::NodeType in float extension
Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D120412
2022-02-24 19:57:55 +08:00
Sven van Haastregt 88182e2dfd [OpenCL] opencl-c.h: remove arg names for image builtins
This simplifies completeness comparisons against OpenCLBuiltins.td and
also makes the header no longer "claim" the identifiers "image",
"image_array", "coord", "sampler", "sample", "gradientX", "gradientY",
"lod", and "color".

Continues the direction set out in D119560.
2022-02-24 11:52:32 +00:00
Pavel Labath a85d3b66cb [lldb] Fix macos build for D120425 2022-02-24 12:47:43 +01:00
Javier Setoain cd0d21b47b [mlir][LLVM] Allow scalable vectors in ShuffleVectorOp
The current implementation of ShuffleVectorOp assumes all vectors are
scalable. LLVM IR allows shufflevector operations on scalable vectors,
and the current translation between LLVM Dialect and LLVM IR does the
rigth thing when the shuffle mask is all zeroes. This is required to
do a splat operation on a scalable vector, but it doesn't make sense
for scalable vectors outside of that operation, i.e.: with non-all zero
masks.

Differential Revision: https://reviews.llvm.org/D118371
2022-02-24 11:24:34 +00:00
Simon Pilgrim e41a138520 [X86] LowerShiftByScalarVariable - use getSplatSourceVector for vXi8 shift expansion
Using getSplatValue causes poor codegen due to not always being able to remove the EXTRACT_VECTOR_ELT created inside getSplatValue.

The vXi16 shifts/rotates are still showing occasional regressions but vXi8 is a definite improvement.
2022-02-24 11:24:06 +00:00
Nikita Popov c7fe6f9c92 Revert "[RISCV] add the MC layer support of Zfinx extension"
This reverts commit 7798ecca9c.

As reported in https://reviews.llvm.org/D93298#3331641 and
following, this causes assertion failures with inline assembly.
2022-02-24 12:14:31 +01:00
Shao-Ce SUN a8b4b9104c [NFC][clang] Simplify isOneOf function
Reviewed By: tmatheson

Differential Revision: https://reviews.llvm.org/D117740
2022-02-24 19:12:34 +08:00
Pavel Labath b5eeb8873a [lldb] One more fix for the MonitorChildProcess patch (D120425) 2022-02-24 12:06:42 +01:00
Matthias Springer 25bc684603 [mlir][linalg][bufferize] Always bufferize in-place with "out" operands by default
In D115022, we introduced an optimization where OpResults of a `linalg.generic` may bufferize in-place with an "in" OpOperand if the corresponding "out" OpOperand is not used in the computation.

This optimization can lead to unexpected behavior if the newly chosen OpOperand is in the same alias set as another OpOperand (that is used in the computation). In that case, the newly chosen OpOperand must bufferize out-of-place. This can be confusing to users, as always choosing the "out" OpOperand (regardless of whether it is used) would be expected when having the notion of "destination-passing style" in mind.

With this change, we go back to always bufferizing in-place with "out" OpOperands by default, but letting users override the behavior with a bufferization option.

Differential Revision: https://reviews.llvm.org/D120182
2022-02-24 19:58:05 +09:00
Pavel Labath c64dbb66d9 [lldb] Fix windows build for D120425 2022-02-24 11:50:54 +01:00
Andrzej Warzynski 19b6e70554 [flang][docs] Update the top "doc" page
* Added a note about "Classic Flang"
* sorted entries in ToC

Differential Revision: https://reviews.llvm.org/D120067
2022-02-24 10:41:53 +00:00
Pavel Labath 12c9c4a885 [lldb/host] Remove monitor_signals argument from process monitoring functions
All current callers set the argument to false. monitor_signals=true used
to be used in the Process plugins (which needed to know when the
debugged process gets a signal), but this implementation has several
serious issues, which means that individual process plugins now
orchestrate the monitoring of debugged processes themselves.

This allows us to simplify the implementation (no need to play with
process groups), and the interface (we only catch fatal events, so the
callback is always called just once).

Differential Revision: https://reviews.llvm.org/D120425
2022-02-24 11:12:59 +01:00