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421156 commits

Author SHA1 Message Date
Nathan Sidwell 201c4b9cc4 [demangler] Rust demangler buffer return
The rust demangler has some odd buffer handling code, which will copy
the demangled string into the provided buffer, if it will fit.
Otherwise it uses the allocated buffer it made.  But the length of the
incoming buffer will have come from a previous call, which was the
length of the demangled string -- not the buffer size.  And of course,
we're unconditionally allocating a temporary buffer in the first
place.  So we don't actually get buffer reuse, and we get a memcpy in
somecases.

However, nothing in LLVM ever passes in a non-null pointer.  Neither
does anything pass in a status pointer that is then made use of.  The
only exercise these have is in the test suite.

So let's just make the rust demangler have the same API as the dlang
demangler.

Reviewed By: tmiasko

Differential Revision: https://reviews.llvm.org/D123420
2022-04-13 08:50:04 -07:00
Jay Foad ccaf6dabcc [AMDGPU] Initialize a couple more Subtarget fields
This is just for consistency. The fields are never actually used
so it is NFC.
2022-04-13 16:36:10 +01:00
Xing Xue 9c0152cda3 [libunwind][AIX] implementation of the unwinder for AIX
Summary:
This is an add-on patch to address comments.
- Replace #elif in file <assembly.h> with #else as suggested;
- Reversed the indentation changes in the main patch.

Differential Revision: https://reviews.llvm.org/D100132
2022-04-13 11:29:37 -04:00
Florian Hahn 4bf3b7dc92
Recommit "[LICM] Only create load in pre-header when promoting load."
This reverts the revert commit 1ddc719680.

This version of the patch sets the initial available value to poison,
which resolves an issue with the SSAUpdater breaking LCSSA form.
2022-04-13 17:20:39 +02:00
LLVM GN Syncbot 1203a24764 [gn build] Port a85da649b9 2022-04-13 15:05:20 +00:00
Xing Xue a85da649b9 [libunwind][AIX] implementation of the unwinder for AIX
Summary:
This patch contains the implementation of the unwinder for IBM AIX.

AIX does not support the eh_frame section. Instead, the traceback table located at the end of each function provides the information for stack unwinding and EH. In this patch macro _LIBUNWIND_SUPPORT_TBTAB_UNWIND is used to guard code for AIX traceback table based unwinding. Function getInfoFromTBTable() and stepWithTBTable() are added to get the EH information from the traceback table and to step up the stack respectively.

There are two kinds of LSDA information for EH on AIX, the state table and the range table. The state table is used by the previous version of the IBM XL compiler, i.e., xlC and xlclang++. The DWARF based range table is used by AIX clang++. The traceback table has flags to differentiate these cases. For the range table, relative addresses are calculated using a base of DW_EH_PE_datarel, which is the TOC base of the module where the function of the current frame belongs.

Two personality routines are employed to handle these two different LSDAs, __xlcxx_personality_v0() for the state table and __xlcxx_personality_v1() for the range table. Since the traceback table does not have the information of the personality for the state table approach, its personality __xlcxx_personality_v0() is dynamically resolved as the handler for the state table. For the range table, the locations of the LSDA and its associated personality routine are found in the traceback table.

Assembly code for 32- and 64-bit PowerPC in UnwindRegistersRestore.S and UnwindRegistersSave.S are modified so that it can be consumed by the GNU flavor assembler and the AIX assembler. The restoration of vector registers does not check VRSAVE on AIX because VRSAVE is not used in the AIX ABI.

Reviewed by: MaskRay, compnerd, cebowleratibm, sfertile, libunwind

Differential Revision: https://reviews.llvm.org/D100132
2022-04-13 11:01:59 -04:00
Yaxun (Sam) Liu 0424b5115c [CUDA][HIP] Fix host used external kernel in archive
For -fgpu-rdc, a host function may call an external kernel
which is defined in an archive of bitcode. Since this external
kernel is only referenced in host function, the device
bitcode does not contain reference to this external
kernel, then the linker will not try to resolve this external
kernel in the archive.

To fix this issue, host-used external kernels and device
variables are tracked. A global array containing pointers
to these external kernels and variables is emitted which
serves as an artificial references to the external kernels
and variables used by host.

Reviewed by: Artem Belevich

Differential Revision: https://reviews.llvm.org/D123441
2022-04-13 10:47:16 -04:00
Nikita Popov 8c74169990 [SimplifyLibCalls] Don't mark memchr() memory as fully dereferenceable
C11 specifies memchr() as follows:

> The memchr function locates the first occurrence of c (converted
> to an unsigned char) in the initial n characters (each interpreted
> as unsigned char) of the object pointed to by s. The implementation
> shall behave as if it reads the characters sequentially and stops
> as soon as a matching character is found.

In particular, it is well-defined to specify a memchr size larger
than the underlying object, as long as the character is found before
the end of the object.

Differential Revision: https://reviews.llvm.org/D123665
2022-04-13 16:46:18 +02:00
Marek Kurdej b58616c2cd [clang-format] Fix SeparateDefinitionBlocks breaking up function-try-block.
Fixes https://github.com/llvm/llvm-project/issues/54536.

Reviewed By: HazardyKnusperkeks, owenpan

Differential Revision: https://reviews.llvm.org/D122468
2022-04-13 16:44:04 +02:00
Tobias Hieta 837d16fb4c [NFC] Simplify /noimplib argument logic 2022-04-13 16:40:30 +02:00
Tobias Hieta 2af4385477 [LLD][COFF] Add support for /noimplib
Mostly for compatibility reasons with link.exe this flag
makes sure we don't write a implib - not even when /implib
is also passed, that's how link.exe works.

Differential Revision: https://reviews.llvm.org/D123591
2022-04-13 16:40:29 +02:00
chenglin.bi fd0641b58c [SimplifyCFG] add tests for switch to select; NFC
Baseline tests for D122485 (issue #39957)
2022-04-13 22:35:25 +08:00
chenglin.bi dfc98d0c9c Revert "[SimplifyCFG] add tests for switch to select; NFC"
This reverts commit e2d77a160c.
2022-04-13 22:35:25 +08:00
PeixinQiao 8964a17dad [OpenMP] Lowering to MLIR of ordered threads directive
This patch supports lowering parse-tree to MLIR of ordered threads
directive following Section 2.19.9 of the OpenMP 5.1 standard.

This is part of the upstreaming effort from the fir-dev branch in [1].
[1] https://github.com/flang-compiler/f18-llvm-project

Reviewed By: shraiysh

Differential Revision: https://reviews.llvm.org/D123590
2022-04-13 22:30:52 +08:00
PeixinQiao 154135c11c [flang][OpenMP] Add semantic checks of nesting of region about ordered construct
This patch supports the following checks for ORDERED construct:

```
[5.1] 2.19.9 ORDERED Construct
The worksharing-loop or worksharing-loop SIMD region to which an ordered
region corresponding to an ordered construct without a depend clause
binds must have an ordered clause without the parameter specified on the
corresponding worksharing-loop or worksharing-loop SIMD directive.
The worksharing-loop region to which an ordered region that corresponds
to an ordered construct with any depend clauses binds must have an
ordered clause with the parameter specified on the corresponding
worksharing-loop directive.
An ordered construct with the depend clause specified must be closely
nested inside a worksharing-loop (or parallel worksharing-loop)
construct.
An ordered region that corresponds to an ordered construct with the simd
clause specified must be closely nested inside a simd or
worksharing-loop SIMD region.
```

Reviewed By: kiranchandramohan, shraiysh, NimishMishra

Differential Revision: https://reviews.llvm.org/D113399
2022-04-13 22:27:58 +08:00
Marius Brehler f71f105901 [mlir][docs] Fix broken links 2022-04-13 16:18:20 +02:00
Louis Dionne 1352ea4ea1 [libc++] Mark completed paper as complete 2022-04-13 10:16:44 -04:00
LLVM GN Syncbot d1e5854805 [gn build] Port 2fb026ee4d 2022-04-13 13:52:22 +00:00
Louis Dionne db6421ec58 [libc++] Post-commit adjustments after rebasing D117656 2022-04-13 09:51:43 -04:00
Arthur O'Dwyer 2fb026ee4d Implement move_sentinel and C++20 move_iterator.
Differential Revision: https://reviews.llvm.org/D117656
2022-04-13 09:51:43 -04:00
Pavel Labath 7d70b1a405 [lldb] Fixup af921006d3 for non-linux platforms 2022-04-13 15:38:36 +02:00
chenglin.bi e2d77a160c [SimplifyCFG] add tests for switch to select; NFC
Baseline tests for D122968(issue #54649)
2022-04-13 21:27:06 +08:00
LLVM GN Syncbot 0242ffd9c0 [gn build] Port 2b424f4ea8 2022-04-13 13:04:50 +00:00
Louis Dionne 2b424f4ea8 [libc++] Implement ranges::filter_view
Differential Revision: https://reviews.llvm.org/D109086
2022-04-13 09:03:46 -04:00
Jonas Paulsson 27e8c50a4c [SystemZ] Implement adjustInliningThreshold().
This patch boosts the inlining threshold for a particular type of functions
that are using an incoming argument only as a memcpy source.

Review: Ulrich Weigand

Differential Revision: https://reviews.llvm.org/D121341
2022-04-13 14:48:10 +02:00
Sam McCall f407c9ed10 [clangd] Export preamble AST and serialized size as metrics
Differential Revision: https://reviews.llvm.org/D123672
2022-04-13 14:43:06 +02:00
Pavel Labath af921006d3 [lldb] Remove the global platform list
This patch moves the platform creation and selection logic into the
per-debugger platform lists. I've tried to keep functional changes to a
minimum -- the main (only) observable difference in this change is that
APIs, which select a platform by name (e.g.,
Debugger::SetCurrentPlatform) will not automatically pick up a platform
associated with another debugger (or no debugger at all).

I've also added several tests for this functionality -- one of the
pleasant consequences of the debugger isolation is that it is now
possible to test the platform selection and creation logic.

This is a product of the discussion at
<https://discourse.llvm.org/t/multiple-platforms-with-the-same-name/59594>.

Differential Revision: https://reviews.llvm.org/D120810
2022-04-13 14:41:13 +02:00
Nico Weber ba4537b227 [compiler-rt] Don't explictly ad-hoc sign dylibs on APPLE if ld is new enough
ld64 implicitly ad-hoc code-signs as of Xcode 12, and `strip` and friends know
how keep this special ad-hoc signature valid.

So this should have no effective behavior change, except that you can now strip
libclang_rt.asan_osx_dynamic.dylib and it'll still have a valid ad-hoc
signature, instead of strip printing "warning: changes being made to the file
will invalidate the code signature in:" and making the ad-hoc code signature
invalid.

Differential Revision: https://reviews.llvm.org/D123475
2022-04-13 08:35:51 -04:00
Adrian Kuegel bd941c83f5 [mlir][Tensor] Fix wrong comment (NFC) 2022-04-13 14:30:55 +02:00
Aaron Ballman 385e7df330 Correctly diagnose prototype redeclaration errors in C
We did not implement C99 6.7.5.3p15 fully in that we missed the rule
for compatible function types where a prior declaration has a prototype
and a subsequent definition (not just declaration) has an empty
identifier list or an identifier list with a mismatch in parameter
arity. This addresses that situation by issuing an error on code like:

void f(int);
void f() {} // type conflicts with previous declaration

(Note: we already diagnose the other type conflict situations
appropriately, this was the only situation we hadn't covered that I
could find.)
2022-04-13 08:21:31 -04:00
Liu, Chen3 bf60a5af0a [X86] Covert unsigned int 0 to float-point with FILD instruction.
unsinged int 0 will be convert to float/double -0.0 when the rounding
mode is set to 'FE_DOWNWARD'. Using FILD instruction instead of SSE
instructions on 32-bit target if the strictfp is enabled.

Differential Revision: https://reviews.llvm.org/D123660
2022-04-13 20:06:15 +08:00
Simon Pilgrim fef221bf1f [DAG] Enable SimplifyVBinOp folds on add/sub sat intrinsics 2022-04-13 12:53:23 +01:00
Dmitry Preobrazhensky 5c0bf1303e [AMDGPU][MC][GFX10] Removed unsupported 64bit DPP opcodes
Removed 64bit DPP opcodes from asm matcher tables.

Differential Revision: https://reviews.llvm.org/D123611
2022-04-13 14:43:40 +03:00
Simon Pilgrim d9986fbfb6 [X86] Add tests showing failure to pull common shuffles through add/sub sat intrinsics 2022-04-13 12:35:38 +01:00
Sanjay Patel cd0d0d633b [SimplifyCFG] make a debug option for case max when converting switch to select
This should be "NFC" as written, but it will make D122485 smaller
and give us more flexibility to experiment with optimization level
vs. compile-time.

Differential Revision: https://reviews.llvm.org/D123625
2022-04-13 06:55:13 -04:00
Jonas Paulsson 46f83caebc [InlineAsm] Add support for address operands ("p").
This patch adds support for inline assembly address operands using the "p"
constraint on X86 and SystemZ.

This was in fact broken on X86 (see example at
https://reviews.llvm.org/D110267, Nov 23).

These operands should probably be treated the same as memory operands by
CodeGenPrepare, which have been commented with "TODO" there.

Review: Xiang Zhang and Ulrich Weigand

Differential Revision: https://reviews.llvm.org/D122220
2022-04-13 12:50:21 +02:00
Andrzej Warzynski 6d3224d93f [flang][nfc] Simplify TargetMachine initialisation 2022-04-13 10:49:24 +00:00
Dmitry Preobrazhensky ab18e1a533 [AMDGPU][GFX10] Enabled op_sel for v_add_nc_u16 and v_sub_nc_u16
Differential Revision: https://reviews.llvm.org/D123594
2022-04-13 13:48:42 +03:00
Vladislav Khmelevsky caf9eb6e4d [BOLT] Fix two aarch64 tests
tls-lld test might be broken since compiler might optimize plt function
call and use address directly from got table. The test is removed since
plt-gnu-ld checks the same functionality + versioning symbol matching,
no need to keep both of the tests.
The toolchain might optimize relocations in runtime-relocs test, replace
the test compilation with yaml files.

Differential Revision: https://reviews.llvm.org/D123332
2022-04-13 13:38:32 +03:00
Simon Pilgrim cfb3ee2185 [DAG] Add non-uniform vector support to (shl (srl x, c1), c2) -> (and (shift x, c3))
Another part of D77804 yak shaving

Differential Revision: https://reviews.llvm.org/D123523
2022-04-13 11:37:33 +01:00
Andrzej Warzynski dd56939a4b [flang][driver] Add support for generating LLVM bytecode files
Support for generating LLVM BC files is added in Flang's compiler and
frontend drivers. This requires the `BitcodeWriterPass` pass to be run
on the input LLVM IR module and is implemented as a dedicated frontend
aciton. The new functionality as seen by the user (compiler driver):
```
flang-new -c -emit-llvm file.90
```
or (frontend driver):
```
flang-new -fc1 -emit-llvm-bc file.f90
```

The new behaviour is consistent with `clang` and `clang -cc1`.

Differential Revision: https://reviews.llvm.org/D123211
2022-04-13 10:19:56 +00:00
Ping Deng 9d2350fd19 [RISCV][NFC] Reorganize check prefixes in some tests to reduce redundant lines
Reviewed By: benshi001, craig.topper, frasercrmck

Differential Revision: https://reviews.llvm.org/D123176
2022-04-13 10:01:07 +00:00
Alex Richardson ee44896cf4 [AArch64] Add missing HasNEON predicate in scalar FABD patterns
I was trying to compile with -march=+nosimd and hit the following assertion:
`Attempting to emit FABD64 instruction but the Feature_HasNEON predicate(s) are not met`.
This adds a HasNEON predicate to the patterns which was omitted in commit
21d9b33d62 for some reason.
The new code generation matches GCC with -mcpu=<cpu>+nosimd:
https://godbolt.org/z/n1Y7xh5jo

Differential Revision: https://reviews.llvm.org/D123491
2022-04-13 09:30:11 +00:00
Alex Richardson 32a353a5e0 [AArch64] Baseline test for D123491 2022-04-13 09:30:11 +00:00
Alex Richardson 9107cd632d [AutoUpgrade] Don't lose attributes when upgrading mem intrinsics
The original AutoUpgrade code from 1e68724d24
did not retain existing attributes. I noticed this in some downstream test
cases, but it turns out there are also two affected testcase upstream.

Differential Revision: https://reviews.llvm.org/D121971
2022-04-13 09:30:10 +00:00
David Sherwood 44271e7c55 [AArch64][SVE] Fix lowering of "fcmp ueq/one" when using SVE
We were previously lowering to the incorrect instructions for the
setcc DAG node when using the SETUEQ and SETONE floating point
condition codes. I have fixed this by marking the SETONE code
as Expand and letting the SETUNE code be legal. I have also
fixed up the patterns for FCMNE_PPzZZ and FCMNE_PPzZ0 to use
the correct opcode.

Differential Revision: https://reviews.llvm.org/D121905
2022-04-13 10:24:03 +01:00
Liqin Weng 8265679018 [RISCV][NFC] Refactor the type promotion of fsl/fsr/becompress/bdecompress/bfp
Reviewed By: asb, jrtc27, craig.topper, frasercrmck

Differential Revision: https://reviews.llvm.org/D123181
2022-04-13 08:52:04 +00:00
Dmitry Makogon 2603dcdd8d [Test] Add tests showing duplicate PHIs generated by RS4GC (NFC) 2022-04-13 15:51:17 +07:00
Nikita Popov 0d86fc65ba [LTO] Remove legacy PM support
We don't have any places setting NewPM=false anymore, so drop the
support code in LTOBackend.
2022-04-13 10:48:08 +02:00
Nikita Popov 69fcf6a79e Revert "[ubsan] Simplify ubsan_GetStackTrace"
This reverts commit 63f2d1f4d4.

I don't quite understand why, but this causes a linker error for
me and a number of buildbots:

/home/npopov/repos/llvm-project/compiler-rt/lib/ubsan/../sanitizer_common/sanitizer_stacktrace.h:130: error: undefined reference to '__sanitizer::BufferedStackTrace::UnwindImpl(unsigned long, unsigned long, void*, bool, unsigned int)'
2022-04-13 10:41:23 +02:00