[AMDGPU] gfx940 VALU hazard recognizer
Differntial Revision: https://reviews.llvm.org/D122339
This commit is contained in:
Stanislav Mekhanoshin
parent
267d1873fa
commit
f311f934e1
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@ -813,13 +813,136 @@ GCNHazardRecognizer::checkVALUHazardsHelper(const MachineOperand &Def,
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}
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int GCNHazardRecognizer::checkVALUHazards(MachineInstr *VALU) {
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int WaitStatesNeeded = 0;
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if (ST.hasTransForwardingHazard() && !SIInstrInfo::isTRANS(*VALU)) {
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const int TransDefWaitstates = 1;
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auto IsTransDefFn = [this, VALU](const MachineInstr &MI) {
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if (!SIInstrInfo::isTRANS(MI))
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return false;
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const SIRegisterInfo *TRI = ST.getRegisterInfo();
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const SIInstrInfo *TII = ST.getInstrInfo();
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Register Def = TII->getNamedOperand(MI, AMDGPU::OpName::vdst)->getReg();
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for (const MachineOperand &Use : VALU->explicit_uses()) {
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if (Use.isReg() && TRI->regsOverlap(Def, Use.getReg()))
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return true;
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}
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return false;
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};
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int WaitStatesNeededForDef =
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TransDefWaitstates -
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getWaitStatesSince(IsTransDefFn, TransDefWaitstates);
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WaitStatesNeeded = std::max(WaitStatesNeeded, WaitStatesNeededForDef);
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}
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if (ST.hasDstSelForwardingHazard()) {
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const int Shift16DefWaitstates = 1;
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auto IsShift16BitDefFn = [this, VALU](const MachineInstr &MI) {
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if (!SIInstrInfo::isVALU(MI))
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return false;
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const SIInstrInfo *TII = ST.getInstrInfo();
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if (SIInstrInfo::isSDWA(MI)) {
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if (auto *DstSel = TII->getNamedOperand(MI, AMDGPU::OpName::dst_sel))
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if (DstSel->getImm() == AMDGPU::SDWA::DWORD)
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return false;
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} else {
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if ((AMDGPU::getNamedOperandIdx(MI.getOpcode(),
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AMDGPU::OpName::op_sel) == -1) ||
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!(TII->getNamedOperand(MI, AMDGPU::OpName::src0_modifiers)
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->getImm() &
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SISrcMods::DST_OP_SEL))
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return false;
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}
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const SIRegisterInfo *TRI = ST.getRegisterInfo();
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if (auto *Dst = TII->getNamedOperand(MI, AMDGPU::OpName::vdst)) {
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Register Def = Dst->getReg();
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for (const MachineOperand &Use : VALU->explicit_uses()) {
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if (Use.isReg() && TRI->regsOverlap(Def, Use.getReg()))
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return true;
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}
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}
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return false;
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};
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int WaitStatesNeededForDef =
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Shift16DefWaitstates -
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getWaitStatesSince(IsShift16BitDefFn, Shift16DefWaitstates);
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WaitStatesNeeded = std::max(WaitStatesNeeded, WaitStatesNeededForDef);
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}
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if (ST.hasVDecCoExecHazard()) {
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const int VALUWriteSGPRVALUReadWaitstates = 2;
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const int VALUWriteEXECRWLane = 4;
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const int VALUWriteVGPRReadlaneRead = 1;
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const SIRegisterInfo *TRI = ST.getRegisterInfo();
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const MachineRegisterInfo &MRI = MF.getRegInfo();
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Register UseReg;
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auto IsVALUDefSGPRFn = [&UseReg, TRI](const MachineInstr &MI) {
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if (!SIInstrInfo::isVALU(MI))
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return false;
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return MI.modifiesRegister(UseReg, TRI);
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};
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for (const MachineOperand &Use : VALU->explicit_uses()) {
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if (!Use.isReg())
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continue;
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UseReg = Use.getReg();
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if (TRI->isSGPRReg(MRI, UseReg)) {
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int WaitStatesNeededForDef =
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VALUWriteSGPRVALUReadWaitstates -
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getWaitStatesSince(IsVALUDefSGPRFn,
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VALUWriteSGPRVALUReadWaitstates);
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WaitStatesNeeded = std::max(WaitStatesNeeded, WaitStatesNeededForDef);
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}
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}
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if (VALU->readsRegister(AMDGPU::VCC, TRI)) {
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UseReg = AMDGPU::VCC;
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int WaitStatesNeededForDef =
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VALUWriteSGPRVALUReadWaitstates -
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getWaitStatesSince(IsVALUDefSGPRFn, VALUWriteSGPRVALUReadWaitstates);
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WaitStatesNeeded = std::max(WaitStatesNeeded, WaitStatesNeededForDef);
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}
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switch (VALU->getOpcode()) {
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case AMDGPU::V_READLANE_B32:
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case AMDGPU::V_READFIRSTLANE_B32: {
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MachineOperand *Src = TII.getNamedOperand(*VALU, AMDGPU::OpName::src0);
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UseReg = Src->getReg();
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int WaitStatesNeededForDef =
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VALUWriteVGPRReadlaneRead -
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getWaitStatesSince(IsVALUDefSGPRFn, VALUWriteVGPRReadlaneRead);
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WaitStatesNeeded = std::max(WaitStatesNeeded, WaitStatesNeededForDef);
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}
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LLVM_FALLTHROUGH;
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case AMDGPU::V_WRITELANE_B32: {
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UseReg = AMDGPU::EXEC;
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int WaitStatesNeededForDef =
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VALUWriteEXECRWLane -
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getWaitStatesSince(IsVALUDefSGPRFn, VALUWriteEXECRWLane);
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WaitStatesNeeded = std::max(WaitStatesNeeded, WaitStatesNeededForDef);
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break;
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}
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default:
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break;
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}
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}
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// This checks for the hazard where VMEM instructions that store more than
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// 8 bytes can have there store data over written by the next instruction.
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if (!ST.has12DWordStoreHazard())
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return 0;
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return WaitStatesNeeded;
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const MachineRegisterInfo &MRI = MF.getRegInfo();
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int WaitStatesNeeded = 0;
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for (const MachineOperand &Def : VALU->defs()) {
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WaitStatesNeeded = std::max(WaitStatesNeeded, checkVALUHazardsHelper(Def, MRI));
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@ -966,8 +966,19 @@ public:
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return HasLdsBranchVmemWARHazard;
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}
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// Has one cycle hazard on transcendental instruction feeding a
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// non transcendental VALU.
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bool hasTransForwardingHazard() const { return GFX940Insts; }
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// Has one cycle hazard on a VALU instruction partially writing dst with
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// a shift of result bits feeding another VALU instruction.
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bool hasDstSelForwardingHazard() const { return GFX940Insts; }
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// Cannot use op_sel with v_dot instructions.
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bool hasDOTOpSelHazard() const {
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bool hasDOTOpSelHazard() const { return GFX940Insts; }
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// Does not have HW interlocs for VALU writing and then reading SGPRs.
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bool hasVDecCoExecHazard() const {
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return GFX940Insts;
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}
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217
llvm/test/CodeGen/AMDGPU/gfx940-hazards.mir
Normal file
217
llvm/test/CodeGen/AMDGPU/gfx940-hazards.mir
Normal file
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@ -0,0 +1,217 @@
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# RUN: llc -march=amdgcn -mcpu=gfx940 -verify-machineinstrs -run-pass post-RA-hazard-rec %s -o - | FileCheck -check-prefix=GCN %s
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# GCN-LABEL: name: trans32_write_non_trans32_read
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# GCN: V_RCP_F32
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# GCN-NEXT: S_NOP 0
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# GCN-NEXT: V_MUL_F32
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name: trans32_write_non_trans32_read
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body: |
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bb.0:
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$vgpr1 = V_RCP_F32_e32 $vgpr0, implicit $mode, implicit $exec
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$vgpr2 = V_MUL_F32_e32 $vgpr1, $vgpr2, implicit $mode, implicit $exec
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...
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# GCN-LABEL: name: trans32_write_trans_read
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# GCN: V_SIN_F32
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# GCN-NEXT: V_COS_F32
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name: trans32_write_trans_read
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body: |
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bb.0:
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$vgpr0 = V_SIN_F32_e32 $vgpr1, implicit $mode, implicit $exec
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$vgpr2 = V_COS_F32_e32 $vgpr0, implicit $mode, implicit $exec
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...
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# GCN-LABEL: name: trans64_write_non_trans_read
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# GCN: V_RCP_F64
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# GCN-NEXT: S_NOP 0
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# GCN-NEXT: V_OR_B32
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name: trans64_write_non_trans_read
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body: |
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bb.0:
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$vgpr0_vgpr1 = V_RCP_F64_e32 $vgpr2_vgpr3, implicit $mode, implicit $exec
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$vgpr4 = V_OR_B32_e32 $vgpr1, $vgpr5, implicit $mode, implicit $exec
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...
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# GCN-LABEL: name: trans32_write_non_trans64_read
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# GCN: V_EXP_F32
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# GCN-NEXT: S_NOP 0
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# GCN-NEXT: V_MUL_F64
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name: trans32_write_non_trans64_read
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body: |
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bb.0:
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$vgpr1 = V_EXP_F32_e32 $vgpr0, implicit $mode, implicit $exec
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$vgpr2_vgpr3 = V_MUL_F64_e64 0, $vgpr0_vgpr1, 0, $vgpr2_vgpr3, 0, 0, implicit $mode, implicit $exec
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...
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# GCN-LABEL: name: opsel_hi16_write_valu_read
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# GCN: V_ADD_I16
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# GCN-NEXT: S_NOP 0
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# GCN-NEXT: V_MUL_F64
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name: opsel_hi16_write_valu_read
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body: |
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bb.0:
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$vgpr0 = V_ADD_I16_e64 8, $vgpr1, 0, $vgpr2, 0, 0, implicit $exec
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$vgpr4_vgpr5 = V_MUL_F64_e64 0, $vgpr0_vgpr1, 0, $vgpr2_vgpr3, 0, 0, implicit $mode, implicit $exec
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...
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# GCN-LABEL: name: opsel_lo16_write_valu_read
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# GCN: V_ADD_I16
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# GCN-NEXT: V_MUL_F64
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name: opsel_lo16_write_valu_read
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body: |
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bb.0:
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$vgpr0 = V_ADD_I16_e64 0, $vgpr1, 0, $vgpr2, 0, 0, implicit $exec
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$vgpr4_vgpr5 = V_MUL_F64_e64 0, $vgpr0_vgpr1, 0, $vgpr2_vgpr3, 0, 0, implicit $mode, implicit $exec
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...
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# GCN-LABEL: name: sdwa_hi16_write_valu_read
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# GCN: V_MOV_B32_sdwa
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# GCN-NEXT: S_NOP 0
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# GCN-NEXT: V_MOV_B32_e32
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name: sdwa_hi16_write_valu_read
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body: |
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bb.0:
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$vgpr0 = V_MOV_B32_sdwa 0, $vgpr1, 0, 5, 2, 5, implicit $vgpr0(tied-def 0), implicit $exec
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$vgpr3 = V_MOV_B32_e32 $vgpr0, implicit $exec
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...
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# GCN-LABEL: name: sdwa_lo16_write_valu_read
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# GCN: V_MOV_B32_sdwa
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# GCN-NEXT: S_NOP 0
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# GCN-NEXT: V_MOV_B32_e32
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name: sdwa_lo16_write_valu_read
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body: |
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bb.0:
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$vgpr0 = V_MOV_B32_sdwa 0, $vgpr1, 0, 4, 2, 5, implicit $vgpr0(tied-def 0), implicit $exec
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$vgpr3 = V_MOV_B32_e32 $vgpr0, implicit $exec
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...
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# GCN-LABEL: name: sdwa_dword_write_valu_read
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# GCN: V_MOV_B32_sdwa
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# GCN-NEXT: V_MOV_B32_e32
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name: sdwa_dword_write_valu_read
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body: |
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bb.0:
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$vgpr0 = V_MOV_B32_sdwa 0, $vgpr1, 0, 6, 2, 5, implicit $vgpr0(tied-def 0), implicit $exec
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$vgpr3 = V_MOV_B32_e32 $vgpr0, implicit $exec
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...
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# GCN-LABEL: name: sdwa_lo16_no_write_valu_read
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# GCN: V_CMP_EQ_U32_sdwa
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# GCN-NEXT: V_MOV_B32_e32
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name: sdwa_lo16_no_write_valu_read
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body: |
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bb.0:
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$vcc = V_CMP_EQ_U32_sdwa 0, $vgpr1, 0, $vgpr0, 0, 5, 2, implicit $exec
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$vgpr3 = V_MOV_B32_e32 $vgpr0, implicit $exec
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...
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# GCN-LABEL: name: valu_write_sgpr_valu_read_as_constant
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# GCN: V_READFIRSTLANE_B32
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# GCN-NEXT: S_NOP 1
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# GCN-NEXT: V_MOV_B32_e32
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name: valu_write_sgpr_valu_read_as_constant
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body: |
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bb.0:
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$sgpr0 = V_READFIRSTLANE_B32 $vgpr0, implicit $exec
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$vgpr1 = V_MOV_B32_e32 $sgpr0, implicit $exec
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...
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# GCN-LABEL: name: valu_write_vcc_valu_read_as_constant
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# GCN: V_CMP_NE_U32_e32
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# GCN-NEXT: S_NOP 1
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# GCN-NEXT: V_ADDC_U32_e32
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name: valu_write_vcc_valu_read_as_constant
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body: |
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bb.0:
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V_CMP_NE_U32_e32 0, $vgpr0, implicit-def $vcc, implicit $exec
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$vgpr1 = V_ADDC_U32_e32 0, $vgpr1, implicit-def $vcc, implicit $vcc, implicit $exec
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...
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# GCN-LABEL: name: valu_write_sgpr_readlane_read_as_laneselect
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# GCN: V_READFIRSTLANE_B32
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# GCN-NEXT: S_NOP 3
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# GCN-NEXT: V_READLANE_B32
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name: valu_write_sgpr_readlane_read_as_laneselect
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body: |
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bb.0:
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$sgpr0 = V_READFIRSTLANE_B32 $vgpr0, implicit $exec
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$sgpr1 = V_READLANE_B32 $vgpr1, $sgpr0, implicit $exec
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...
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# GCN-LABEL: name: valu_write_sgpr_writelane_read_as_laneselect
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# GCN: V_ADD_CO_U32_e64
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# GCN-NEXT: S_NOP 3
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# GCN-NEXT: V_WRITELANE_B32
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name: valu_write_sgpr_writelane_read_as_laneselect
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body: |
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bb.0:
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$vgpr0, $sgpr0_sgpr1 = V_ADD_CO_U32_e64 $vgpr0, 1, 0, implicit $exec
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$vgpr1 = V_WRITELANE_B32 0, $sgpr0, $vgpr1, implicit $exec
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...
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# GCN-LABEL: name: vcmpx_write_exec_valu_read_as_constant
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# GCN: V_CMPX_EQ_I32_e32
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# GCN-NEXT: S_NOP 1
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# GCN-NEXT: V_MOV_B32_e32
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name: vcmpx_write_exec_valu_read_as_constant
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body: |
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bb.0:
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implicit $exec, implicit $vcc = V_CMPX_EQ_I32_e32 $vgpr0, $vgpr1, implicit $exec
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$vgpr1 = V_MOV_B32_e32 $exec_lo, implicit $exec
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...
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# GCN-LABEL: name: vcmpx_write_exec_readlane
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# GCN: V_CMPX_EQ_I32_e32
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# GCN-NEXT: S_NOP 3
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# GCN-NEXT: V_READLANE_B32
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name: vcmpx_write_exec_readlane
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body: |
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bb.0:
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implicit $exec, implicit $vcc = V_CMPX_EQ_I32_e32 $vgpr0, $vgpr1, implicit $exec
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$sgpr1 = V_READLANE_B32 $vgpr1, 0, implicit $exec
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...
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# GCN-LABEL: name: vcmpx_write_exec_readfirstlane
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# GCN: V_CMPX_EQ_I32_e32
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# GCN-NEXT: S_NOP 3
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# GCN-NEXT: V_READFIRSTLANE_B32
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name: vcmpx_write_exec_readfirstlane
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body: |
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bb.0:
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implicit $exec, implicit $vcc = V_CMPX_EQ_I32_e32 $vgpr0, $vgpr1, implicit $exec
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$sgpr1 = V_READFIRSTLANE_B32 $vgpr1, implicit $exec
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...
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# GCN-LABEL: name: vcmpx_write_exec_writelane
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# GCN: V_CMPX_EQ_I32_e32
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# GCN-NEXT: S_NOP 3
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# GCN-NEXT: V_WRITELANE_B32
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name: vcmpx_write_exec_writelane
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body: |
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bb.0:
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implicit $exec, implicit $vcc = V_CMPX_EQ_I32_e32 $vgpr0, $vgpr1, implicit $exec
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$vgpr1 = V_WRITELANE_B32 0, $sgpr0, $vgpr1, implicit $exec
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...
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# GCN-LABEL: name: valu_write_vgpr_readlane_read
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# GCN: V_ADD_CO_U32_e32
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# GCN-NEXT: S_NOP 0
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# GCN-NEXT: V_READLANE_B32
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name: valu_write_vgpr_readlane_read
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body: |
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bb.0:
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$vgpr1 = V_ADD_CO_U32_e32 $vgpr0, $vgpr0, implicit-def $vcc, implicit $exec
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$sgpr1 = V_READLANE_B32 $vgpr1, $sgpr0, implicit $exec
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...
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# GCN-LABEL: name: valu_write_vgpr_readfirstlane_read
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# GCN: V_ADD_CO_U32_e32
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# GCN-NEXT: S_NOP 0
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# GCN-NEXT: V_READFIRSTLANE_B32
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name: valu_write_vgpr_readfirstlane_read
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body: |
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bb.0:
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$vgpr1 = V_ADD_CO_U32_e32 $vgpr0, $vgpr0, implicit-def $vcc, implicit $exec
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$sgpr1 = V_READFIRSTLANE_B32 $vgpr1, implicit $exec
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...
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