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[DAG] Fix GT -> GE condition when creating SetCC

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79845ed6df folded some setcc(ashr) conditions to setcc, but got
the condition for NE incorrect, using GT where it should be using GE.
This commit is contained in:
David Green 2021-09-08 12:41:51 +01:00
parent a1e8b754eb
commit d8d24c64fe
7 changed files with 11 additions and 11 deletions
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2
llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
View file

@ -3918,7 +3918,7 @@ SDValue TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
N1C && N1C->isAllOnesValue()) {
return DAG.getSetCC(dl, VT, N0.getOperand(0),
DAG.getConstant(0, dl, OpVT),
Cond == ISD::SETEQ ? ISD::SETLT : ISD::SETGT);
Cond == ISD::SETEQ ? ISD::SETLT : ISD::SETGE);
}
if (SDValue V =

2
llvm/test/CodeGen/AArch64/select-constant-xor.ll
View file

@ -111,7 +111,7 @@ define i32 @icmpasrne(i32 %input, i32 %a, i32 %b) {
; CHECK-LABEL: icmpasrne:
; CHECK: // %bb.0:
; CHECK-NEXT: cmp w0, #0
; CHECK-NEXT: csel w0, w1, w2, gt
; CHECK-NEXT: csel w0, w1, w2, ge
; CHECK-NEXT: ret
%sh = ashr i32 %input, 31
%c = icmp ne i32 %sh, -1

2
llvm/test/CodeGen/AMDGPU/select-constant-xor.ll
View file

@ -131,7 +131,7 @@ define i32 @icmpasrne(i32 %input, i32 %a, i32 %b) {
; CHECK: ; %bb.0:
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT: s_waitcnt_vscnt null, 0x0
; CHECK-NEXT: v_cmp_lt_i32_e32 vcc_lo, 0, v0
; CHECK-NEXT: v_cmp_lt_i32_e32 vcc_lo, -1, v0
; CHECK-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc_lo
; CHECK-NEXT: s_setpc_b64 s[30:31]
%sh = ashr i32 %input, 31

8
llvm/test/CodeGen/ARM/select-constant-xor.ll
View file

@ -320,7 +320,7 @@ define i32 @icmpasreq(i32 %input, i32 %a, i32 %b) {
define i32 @icmpasrne(i32 %input, i32 %a, i32 %b) {
; CHECK7A-LABEL: icmpasrne:
; CHECK7A: @ %bb.0:
; CHECK7A-NEXT: cmp r0, #0
; CHECK7A-NEXT: cmn r0, #1
; CHECK7A-NEXT: movle r1, r2
; CHECK7A-NEXT: mov r0, r1
; CHECK7A-NEXT: bx lr
@ -328,7 +328,7 @@ define i32 @icmpasrne(i32 %input, i32 %a, i32 %b) {
; CHECK6M-LABEL: icmpasrne:
; CHECK6M: @ %bb.0:
; CHECK6M-NEXT: cmp r0, #0
; CHECK6M-NEXT: bgt .LBB9_2
; CHECK6M-NEXT: bge .LBB9_2
; CHECK6M-NEXT: @ %bb.1:
; CHECK6M-NEXT: mov r1, r2
; CHECK6M-NEXT: .LBB9_2:
@ -337,7 +337,7 @@ define i32 @icmpasrne(i32 %input, i32 %a, i32 %b) {
;
; CHECK7M-LABEL: icmpasrne:
; CHECK7M: @ %bb.0:
; CHECK7M-NEXT: cmp r0, #0
; CHECK7M-NEXT: cmp.w r0, #-1
; CHECK7M-NEXT: it le
; CHECK7M-NEXT: movle r1, r2
; CHECK7M-NEXT: mov r0, r1
@ -345,7 +345,7 @@ define i32 @icmpasrne(i32 %input, i32 %a, i32 %b) {
;
; CHECK81M-LABEL: icmpasrne:
; CHECK81M: @ %bb.0:
; CHECK81M-NEXT: cmp r0, #0
; CHECK81M-NEXT: cmp.w r0, #-1
; CHECK81M-NEXT: csel r0, r1, r2, gt
; CHECK81M-NEXT: bx lr
%sh = ashr i32 %input, 31

2
llvm/test/CodeGen/PowerPC/select-constant-xor.ll
View file

@ -117,7 +117,7 @@ define i32 @icmpasreq(i32 %input, i32 %a, i32 %b) {
define i32 @icmpasrne(i32 %input, i32 %a, i32 %b) {
; CHECK-LABEL: icmpasrne:
; CHECK: # %bb.0:
; CHECK-NEXT: cmpwi 3, 0
; CHECK-NEXT: cmpwi 3, -1
; CHECK-NEXT: iselgt 3, 4, 5
; CHECK-NEXT: blr
%sh = ashr i32 %input, 31

4
llvm/test/CodeGen/RISCV/select-constant-xor.ll
View file

@ -188,7 +188,7 @@ define i32 @icmpasreq(i32 %input, i32 %a, i32 %b) {
define i32 @icmpasrne(i32 %input, i32 %a, i32 %b) {
; CHECK32-LABEL: icmpasrne:
; CHECK32: # %bb.0:
; CHECK32-NEXT: bgtz a0, .LBB9_2
; CHECK32-NEXT: bgez a0, .LBB9_2
; CHECK32-NEXT: # %bb.1:
; CHECK32-NEXT: mv a1, a2
; CHECK32-NEXT: .LBB9_2:
@ -199,7 +199,7 @@ define i32 @icmpasrne(i32 %input, i32 %a, i32 %b) {
; CHECK64: # %bb.0:
; CHECK64-NEXT: sext.w a3, a0
; CHECK64-NEXT: mv a0, a1
; CHECK64-NEXT: bgtz a3, .LBB9_2
; CHECK64-NEXT: bgez a3, .LBB9_2
; CHECK64-NEXT: # %bb.1:
; CHECK64-NEXT: mv a0, a2
; CHECK64-NEXT: .LBB9_2:

2
llvm/test/CodeGen/X86/select-constant-xor.ll
View file

@ -124,7 +124,7 @@ define i32 @icmpasrne(i32 %input, i32 %a, i32 %b) {
; CHECK: # %bb.0:
; CHECK-NEXT: movl %esi, %eax
; CHECK-NEXT: testl %edi, %edi
; CHECK-NEXT: cmovlel %edx, %eax
; CHECK-NEXT: cmovsl %edx, %eax
; CHECK-NEXT: retq
%sh = ashr i32 %input, 31
%c = icmp ne i32 %sh, -1