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[AArch64] Pass Reg instead of MI to tryToFindRenameRegister (NFC).

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FirstMI is only used to get the load/store operand and the machine
function. Pass the MF and register explicitly, so the helper can be used
to find rename registers for other instructions in the future.
This commit is contained in:
Florian Hahn 2022-03-01 14:02:02 +00:00
parent 7c080e4649
commit d2c8aa0bf4
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GPG key ID: EEF712BB5E80EBBA
1 changed files with 11 additions and 9 deletions
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20
llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
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@ -1468,18 +1468,19 @@ canRenameUpToDef(MachineInstr &FirstMI, LiveRegUnits &UsedInBetween,
return true;
}
// Check if we can find a physical register for renaming. This register must:
// * not be defined up to FirstMI (checking DefinedInBB)
// * not used between the MI and the defining instruction of the register to
// rename (checked using UsedInBetween).
// Check if we can find a physical register for renaming \p Reg. This register
// must:
// * not be defined already in \p DefinedInBB; DefinedInBB must contain all
// defined registers up to the point where the renamed register will be used,
// * not used in \p UsedInBetween; UsedInBetween must contain all accessed
// registers in the range the rename register will be used,
// * is available in all used register classes (checked using RequiredClasses).
static Optional<MCPhysReg> tryToFindRegisterToRename(
MachineInstr &FirstMI, LiveRegUnits &DefinedInBB,
const MachineFunction &MF, Register Reg, LiveRegUnits &DefinedInBB,
LiveRegUnits &UsedInBetween,
SmallPtrSetImpl<const TargetRegisterClass *> &RequiredClasses,
const TargetRegisterInfo *TRI) {
auto &MF = *FirstMI.getParent()->getParent();
MachineRegisterInfo &RegInfo = MF.getRegInfo();
const MachineRegisterInfo &RegInfo = MF.getRegInfo();
// Checks if any sub- or super-register of PR is callee saved.
auto AnySubOrSuperRegCalleePreserved = [&MF, TRI](MCPhysReg PR) {
@ -1500,7 +1501,7 @@ static Optional<MCPhysReg> tryToFindRegisterToRename(
});
};
auto *RegClass = TRI->getMinimalPhysRegClass(getLdStRegOp(FirstMI).getReg());
auto *RegClass = TRI->getMinimalPhysRegClass(Reg);
for (const MCPhysReg &PR : *RegClass) {
if (DefinedInBB.available(PR) && UsedInBetween.available(PR) &&
!RegInfo.isReserved(PR) && !AnySubOrSuperRegCalleePreserved(PR) &&
@ -1723,7 +1724,8 @@ AArch64LoadStoreOpt::findMatchingInsn(MachineBasicBlock::iterator I,
if (*MaybeCanRename) {
Optional<MCPhysReg> MaybeRenameReg = tryToFindRegisterToRename(
FirstMI, DefinedInBB, UsedInBetween, RequiredClasses, TRI);
*FirstMI.getParent()->getParent(), Reg, DefinedInBB,
UsedInBetween, RequiredClasses, TRI);
if (MaybeRenameReg) {
Flags.setRenameReg(*MaybeRenameReg);
Flags.setMergeForward(true);