[PowerPC] Enable fast-isel on AIX 64 subtarget
This patch basically enables fast-isel for AIX 64-bit subtarget (previously enabled only for ELF 64). The initial motivation is to introduce branch folding to AIX generated code for correct debug behavior. I also saw some compiling time improvement in a few LLVM test-suite benchmarks. (toast, dbms, cjpeg, burg, etc.) Reviewed By: jsji Differential Revision: https://reviews.llvm.org/D98844
This commit is contained in:
Qiu Chaofan
parent
34badc409c
commit
d0f9553ef5
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@ -2467,9 +2467,9 @@ namespace llvm {
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// Create the fast instruction selector for PowerPC64 ELF.
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FastISel *PPC::createFastISel(FunctionLoweringInfo &FuncInfo,
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const TargetLibraryInfo *LibInfo) {
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// Only available on 64-bit ELF for now.
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// Only available on 64-bit for now.
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const PPCSubtarget &Subtarget = FuncInfo.MF->getSubtarget<PPCSubtarget>();
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if (Subtarget.is64BitELFABI())
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if (Subtarget.isPPC64())
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return new PPCFastISel(FuncInfo, LibInfo);
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return nullptr;
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}
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@ -1,4 +1,5 @@
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; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s --check-prefix=ELF64
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; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s --check-prefix=PPC64
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; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64-ibm-aix-xcoff -mcpu=pwr7 | FileCheck %s --check-prefix=PPC64
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%struct.A = type { i32, [2 x [2 x i32]], i8, [3 x [3 x [3 x i32]]] }
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%struct.B = type { i32, [2 x [2 x [2 x %struct.A]]] }
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@ -9,40 +10,40 @@
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define i32* @t1() nounwind {
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entry:
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; ELF64: t1
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; PPC64: t1
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%addr = alloca i32*, align 4
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store i32* getelementptr inbounds ([2 x [2 x [2 x [2 x [2 x i32]]]]], [2 x [2 x [2 x [2 x [2 x i32]]]]]* @arr, i32 0, i32 1, i32 1, i32 1, i32 1, i32 1), i32** %addr, align 4
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; ELF64: addi {{[0-9]+}}, {{[0-9]+}}, 124
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; PPC64: addi {{[0-9]+}}, {{[0-9]+}}, 124
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%0 = load i32*, i32** %addr, align 4
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ret i32* %0
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}
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define i32* @t2() nounwind {
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entry:
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; ELF64: t2
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; PPC64: t2
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%addr = alloca i32*, align 4
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store i32* getelementptr inbounds ([3 x [3 x %struct.A]], [3 x [3 x %struct.A]]* @A, i32 0, i32 2, i32 2, i32 3, i32 1, i32 2, i32 2), i32** %addr, align 4
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; ELF64: addi {{[0-9]+}}, {{[0-9]+}}, 1148
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; PPC64: addi {{[0-9]+}}, {{[0-9]+}}, 1148
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%0 = load i32*, i32** %addr, align 4
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ret i32* %0
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}
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define i32* @t3() nounwind {
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entry:
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; ELF64: t3
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; PPC64: t3
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%addr = alloca i32*, align 4
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store i32* getelementptr inbounds ([3 x [3 x %struct.A]], [3 x [3 x %struct.A]]* @A, i32 0, i32 0, i32 1, i32 1, i32 0, i32 1), i32** %addr, align 4
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; ELF64: addi {{[0-9]+}}, {{[0-9]+}}, 140
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; PPC64: addi {{[0-9]+}}, {{[0-9]+}}, 140
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%0 = load i32*, i32** %addr, align 4
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ret i32* %0
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}
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define i32* @t4() nounwind {
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entry:
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; ELF64: t4
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; PPC64: t4
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%addr = alloca i32*, align 4
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store i32* getelementptr inbounds ([2 x [2 x [2 x %struct.B]]], [2 x [2 x [2 x %struct.B]]]* @B, i32 0, i32 0, i32 0, i32 1, i32 1, i32 0, i32 0, i32 1, i32 3, i32 1, i32 2, i32 1), i32** %addr, align 4
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; ELF64: addi {{[0-9]+}}, {{[0-9]+}}, 1284
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; PPC64: addi {{[0-9]+}}, {{[0-9]+}}, 1284
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%0 = load i32*, i32** %addr, align 4
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ret i32* %0
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}
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@ -1,43 +1,44 @@
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; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s --check-prefix=ELF64
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; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s --check-prefix=PPC64
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; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64-ibm-aix-xcoff -mcpu=pwr7 | FileCheck %s --check-prefix=PPC64
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; Test add with non-legal types
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define void @add_i8(i8 %a, i8 %b) nounwind {
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entry:
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; ELF64: add_i8
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; PPC64: add_i8
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%a.addr = alloca i8, align 4
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%0 = add i8 %a, %b
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; ELF64: add
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; PPC64: add
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store i8 %0, i8* %a.addr, align 4
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ret void
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}
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define void @add_i8_imm(i8 %a) nounwind {
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entry:
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; ELF64: add_i8_imm
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; PPC64: add_i8_imm
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%a.addr = alloca i8, align 4
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%0 = add i8 %a, 22;
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; ELF64: addi
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; PPC64: addi
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store i8 %0, i8* %a.addr, align 4
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ret void
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}
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define void @add_i16(i16 %a, i16 %b) nounwind {
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entry:
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; ELF64: add_i16
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; PPC64: add_i16
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%a.addr = alloca i16, align 4
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%0 = add i16 %a, %b
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; ELF64: add
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; PPC64: add
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store i16 %0, i16* %a.addr, align 4
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ret void
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}
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define void @add_i16_imm(i16 %a, i16 %b) nounwind {
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entry:
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; ELF64: add_i16_imm
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; PPC64: add_i16_imm
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%a.addr = alloca i16, align 4
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%0 = add i16 %a, 243;
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; ELF64: addi
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; PPC64: addi
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store i16 %0, i16* %a.addr, align 4
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ret void
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}
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@ -46,40 +47,40 @@ entry:
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define void @or_i8(i8 %a, i8 %b) nounwind {
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entry:
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; ELF64: or_i8
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; PPC64: or_i8
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%a.addr = alloca i8, align 4
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%0 = or i8 %a, %b
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; ELF64: or
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; PPC64: or
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store i8 %0, i8* %a.addr, align 4
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ret void
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}
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define void @or_i8_imm(i8 %a) nounwind {
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entry:
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; ELF64: or_i8_imm
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; PPC64: or_i8_imm
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%a.addr = alloca i8, align 4
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%0 = or i8 %a, -13;
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; ELF64: ori
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; PPC64: ori
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store i8 %0, i8* %a.addr, align 4
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ret void
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}
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define void @or_i16(i16 %a, i16 %b) nounwind {
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entry:
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; ELF64: or_i16
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; PPC64: or_i16
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%a.addr = alloca i16, align 4
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%0 = or i16 %a, %b
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; ELF64: or
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; PPC64: or
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store i16 %0, i16* %a.addr, align 4
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ret void
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}
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define void @or_i16_imm(i16 %a) nounwind {
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entry:
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; ELF64: or_i16_imm
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; PPC64: or_i16_imm
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%a.addr = alloca i16, align 4
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%0 = or i16 %a, 273;
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; ELF64: ori
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; PPC64: ori
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store i16 %0, i16* %a.addr, align 4
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ret void
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}
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@ -88,50 +89,50 @@ entry:
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define void @sub_i8(i8 %a, i8 %b) nounwind {
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entry:
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; ELF64: sub_i8
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; PPC64: sub_i8
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%a.addr = alloca i8, align 4
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%0 = sub i8 %a, %b
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; ELF64: sub
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; PPC64: sub
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store i8 %0, i8* %a.addr, align 4
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ret void
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}
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define void @sub_i8_imm(i8 %a) nounwind {
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entry:
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; ELF64: sub_i8_imm
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; PPC64: sub_i8_imm
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%a.addr = alloca i8, align 4
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%0 = sub i8 %a, 22;
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; ELF64: addi
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; PPC64: addi
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store i8 %0, i8* %a.addr, align 4
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ret void
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}
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define void @sub_i16(i16 %a, i16 %b) nounwind {
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entry:
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; ELF64: sub_i16
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; PPC64: sub_i16
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%a.addr = alloca i16, align 4
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%0 = sub i16 %a, %b
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; ELF64: sub
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; PPC64: sub
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store i16 %0, i16* %a.addr, align 4
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ret void
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}
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define void @sub_i16_imm(i16 %a) nounwind {
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entry:
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; ELF64: sub_i16_imm
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; PPC64: sub_i16_imm
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%a.addr = alloca i16, align 4
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%0 = sub i16 %a, 247;
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; ELF64: addi
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; PPC64: addi
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store i16 %0, i16* %a.addr, align 4
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ret void
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}
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define void @sub_i16_badimm(i16 %a) nounwind {
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entry:
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; ELF64: sub_i16_imm
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; PPC64: sub_i16_imm
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%a.addr = alloca i16, align 4
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%0 = sub i16 %a, -32768;
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; ELF64: sub
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; PPC64: sub
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store i16 %0, i16* %a.addr, align 4
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ret void
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}
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105
llvm/test/CodeGen/PowerPC/fast-isel-branch.ll
Normal file
105
llvm/test/CodeGen/PowerPC/fast-isel-branch.ll
Normal file
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@ -0,0 +1,105 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s -check-prefix=ELF64
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; RUN: llc -mtriple=powerpc64-ibm-aix-xcoff < %s | FileCheck %s -check-prefix=AIX64
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@x = global i32 1000, align 4
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define signext i32 @bar() #0 {
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; ELF64-LABEL: bar:
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; ELF64: # %bb.0: # %entry
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; ELF64-NEXT: mflr 0
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; ELF64-NEXT: std 0, 16(1)
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; ELF64-NEXT: stdu 1, -48(1)
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; ELF64-NEXT: .cfi_def_cfa_offset 48
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; ELF64-NEXT: .cfi_offset lr, 16
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; ELF64-NEXT: li 3, 0
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; ELF64-NEXT: stw 3, 44(1)
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; ELF64-NEXT: li 3, 0
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; ELF64-NEXT: stw 3, 40(1)
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; ELF64-NEXT: .LBB0_1: # %for.cond
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; ELF64-NEXT: #
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; ELF64-NEXT: lwz 3, 40(1)
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; ELF64-NEXT: addis 4, 2, .LC0@toc@ha
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; ELF64-NEXT: ld 4, .LC0@toc@l(4)
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; ELF64-NEXT: lwz 4, 0(4)
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; ELF64-NEXT: cmpw 3, 4
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; ELF64-NEXT: bge 0, .LBB0_4
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; ELF64-NEXT: # %bb.2: # %for.body
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; ELF64-NEXT: #
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; ELF64-NEXT: bl foo
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; ELF64-NEXT: nop
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; ELF64-NEXT: # %bb.3: # %for.inc
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; ELF64-NEXT: #
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; ELF64-NEXT: lwz 3, 40(1)
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; ELF64-NEXT: addi 3, 3, 1
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; ELF64-NEXT: stw 3, 40(1)
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; ELF64-NEXT: b .LBB0_1
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; ELF64-NEXT: .LBB0_4: # %for.end
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; ELF64-NEXT: li 3, 0
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; ELF64-NEXT: addi 1, 1, 48
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; ELF64-NEXT: ld 0, 16(1)
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; ELF64-NEXT: mtlr 0
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; ELF64-NEXT: blr
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;
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; AIX64-LABEL: bar:
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; AIX64: # %bb.0: # %entry
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; AIX64-NEXT: mflr 0
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; AIX64-NEXT: std 0, 16(1)
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; AIX64-NEXT: stdu 1, -128(1)
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; AIX64-NEXT: li 3, 0
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; AIX64-NEXT: stw 3, 124(1)
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; AIX64-NEXT: li 3, 0
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; AIX64-NEXT: stw 3, 120(1)
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; AIX64-NEXT: L..BB0_1: # %for.cond
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; AIX64-NEXT: #
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; AIX64-NEXT: lwz 3, 120(1)
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; AIX64-NEXT: ld 4, L..C0(2)
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; AIX64-NEXT: lwz 4, 0(4)
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; AIX64-NEXT: cmpw 3, 4
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; AIX64-NEXT: bge 0, L..BB0_4
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; AIX64-NEXT: # %bb.2: # %for.body
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; AIX64-NEXT: #
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; AIX64-NEXT: bl .foo[PR]
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; AIX64-NEXT: nop
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; AIX64-NEXT: # %bb.3: # %for.inc
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; AIX64-NEXT: #
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; AIX64-NEXT: lwz 3, 120(1)
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; AIX64-NEXT: addi 3, 3, 1
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; AIX64-NEXT: stw 3, 120(1)
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; AIX64-NEXT: b L..BB0_1
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; AIX64-NEXT: L..BB0_4: # %for.end
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; AIX64-NEXT: li 3, 0
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; AIX64-NEXT: addi 1, 1, 128
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; AIX64-NEXT: ld 0, 16(1)
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; AIX64-NEXT: mtlr 0
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; AIX64-NEXT: blr
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entry:
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%retval = alloca i32, align 4
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%i = alloca i32, align 4
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store i32 0, i32* %retval, align 4
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store i32 0, i32* %i, align 4
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br label %for.cond
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for.cond:
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%0 = load i32, i32* %i, align 4
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%1 = load i32, i32* @x, align 4
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%cmp = icmp slt i32 %0, %1
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br i1 %cmp, label %for.body, label %for.end
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for.body:
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call void bitcast (void (...)* @foo to void ()*)()
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br label %for.inc
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for.inc:
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%2 = load i32, i32* %i, align 4
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%inc = add nsw i32 %2, 1
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store i32 %inc, i32* %i, align 4
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br label %for.cond
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for.end:
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ret i32 0
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}
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declare void @foo(...)
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attributes #0 = { optnone noinline }
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@ -1,27 +1,28 @@
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; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s --check-prefix=ELF64
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; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s --check-prefix=PPC64
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; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64-ibm-aix-xcoff -mcpu=pwr7 | FileCheck %s --check-prefix=PPC64
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define zeroext i1 @testi1(i8 %in) nounwind {
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entry:
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%c = icmp eq i8 %in, 5
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br i1 %c, label %true, label %false
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; ELF64-LABEL: @testi1
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; PPC64-LABEL: @testi1
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true:
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br label %end
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; ELF64-NOT: li {{[0-9]+}}, -1
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; ELF64: li {{[0-9]+}}, 1
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; PPC64-NOT: li {{[0-9]+}}, -1
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; PPC64: li {{[0-9]+}}, 1
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false:
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br label %end
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; ELF64: li {{[0-9]+}}, 0
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; PPC64: li {{[0-9]+}}, 0
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end:
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%r = phi i1 [ 0, %false], [ 1, %true ]
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ret i1 %r
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; ELF64: blr
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; PPC64: blr
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}
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@ -1,4 +1,5 @@
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; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7
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; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64-ibm-aix-xcoff -mcpu=pwr7
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; Ensure this doesn't crash.
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@ -1,75 +1,76 @@
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; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s --check-prefix=ELF64
|
||||
; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s --check-prefix=PPC64
|
||||
; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64-ibm-aix-xcoff -mcpu=pwr7 | FileCheck %s --check-prefix=PPC64
|
||||
|
||||
; zext
|
||||
|
||||
define i32 @zext_8_32(i8 %a) nounwind {
|
||||
; ELF64: zext_8_32
|
||||
; PPC64: zext_8_32
|
||||
%r = zext i8 %a to i32
|
||||
; ELF64: clrlwi {{[0-9]+}}, {{[0-9]+}}, 24
|
||||
; PPC64: clrlwi {{[0-9]+}}, {{[0-9]+}}, 24
|
||||
ret i32 %r
|
||||
}
|
||||
|
||||
define i32 @zext_16_32(i16 %a) nounwind {
|
||||
; ELF64: zext_16_32
|
||||
; PPC64: zext_16_32
|
||||
%r = zext i16 %a to i32
|
||||
; ELF64: clrlwi {{[0-9]+}}, {{[0-9]+}}, 16
|
||||
; PPC64: clrlwi {{[0-9]+}}, {{[0-9]+}}, 16
|
||||
ret i32 %r
|
||||
}
|
||||
|
||||
define i64 @zext_8_64(i8 %a) nounwind {
|
||||
; ELF64: zext_8_64
|
||||
; PPC64: zext_8_64
|
||||
%r = zext i8 %a to i64
|
||||
; ELF64: clrldi {{[0-9]+}}, {{[0-9]+}}, 56
|
||||
; PPC64: clrldi {{[0-9]+}}, {{[0-9]+}}, 56
|
||||
ret i64 %r
|
||||
}
|
||||
|
||||
define i64 @zext_16_64(i16 %a) nounwind {
|
||||
; ELF64: zext_16_64
|
||||
; PPC64: zext_16_64
|
||||
%r = zext i16 %a to i64
|
||||
; ELF64: clrldi {{[0-9]+}}, {{[0-9]+}}, 48
|
||||
; PPC64: clrldi {{[0-9]+}}, {{[0-9]+}}, 48
|
||||
ret i64 %r
|
||||
}
|
||||
|
||||
define i64 @zext_32_64(i32 %a) nounwind {
|
||||
; ELF64: zext_32_64
|
||||
; PPC64: zext_32_64
|
||||
%r = zext i32 %a to i64
|
||||
; ELF64: clrldi {{[0-9]+}}, {{[0-9]+}}, 32
|
||||
; PPC64: clrldi {{[0-9]+}}, {{[0-9]+}}, 32
|
||||
ret i64 %r
|
||||
}
|
||||
|
||||
; sext
|
||||
|
||||
define i32 @sext_8_32(i8 %a) nounwind {
|
||||
; ELF64: sext_8_32
|
||||
; PPC64: sext_8_32
|
||||
%r = sext i8 %a to i32
|
||||
; ELF64: extsb
|
||||
; PPC64: extsb
|
||||
ret i32 %r
|
||||
}
|
||||
|
||||
define i32 @sext_16_32(i16 %a) nounwind {
|
||||
; ELF64: sext_16_32
|
||||
; PPC64: sext_16_32
|
||||
%r = sext i16 %a to i32
|
||||
; ELF64: extsh
|
||||
; PPC64: extsh
|
||||
ret i32 %r
|
||||
}
|
||||
|
||||
define i64 @sext_8_64(i8 %a) nounwind {
|
||||
; ELF64: sext_8_64
|
||||
; PPC64: sext_8_64
|
||||
%r = sext i8 %a to i64
|
||||
; ELF64: extsb
|
||||
; PPC64: extsb
|
||||
ret i64 %r
|
||||
}
|
||||
|
||||
define i64 @sext_16_64(i16 %a) nounwind {
|
||||
; ELF64: sext_16_64
|
||||
; PPC64: sext_16_64
|
||||
%r = sext i16 %a to i64
|
||||
; ELF64: extsh
|
||||
; PPC64: extsh
|
||||
ret i64 %r
|
||||
}
|
||||
|
||||
define i64 @sext_32_64(i32 %a) nounwind {
|
||||
; ELF64: sext_32_64
|
||||
; PPC64: sext_32_64
|
||||
%r = sext i32 %a to i64
|
||||
; ELF64: extsw
|
||||
; PPC64: extsw
|
||||
ret i64 %r
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,36 +1,37 @@
|
|||
; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s --check-prefix=ELF64
|
||||
; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s --check-prefix=PPC64
|
||||
; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64-ibm-aix-xcoff -mcpu=pwr7 | FileCheck %s --check-prefix=PPC64
|
||||
|
||||
@a = global i8 1, align 1
|
||||
@b = global i16 2, align 2
|
||||
@c = global i32 4, align 4
|
||||
|
||||
define void @t1() nounwind {
|
||||
; ELF64: t1
|
||||
; PPC64: t1
|
||||
%1 = load i8, i8* @a, align 1
|
||||
call void @foo1(i8 zeroext %1)
|
||||
; ELF64: lbz
|
||||
; ELF64-NOT: rldicl
|
||||
; ELF64-NOT: rlwinm
|
||||
; PPC64: lbz
|
||||
; PPC64-NOT: rldicl
|
||||
; PPC64-NOT: rlwinm
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @t2() nounwind {
|
||||
; ELF64: t2
|
||||
; PPC64: t2
|
||||
%1 = load i16, i16* @b, align 2
|
||||
call void @foo2(i16 zeroext %1)
|
||||
; ELF64: lhz
|
||||
; ELF64-NOT: rldicl
|
||||
; ELF64-NOT: rlwinm
|
||||
; PPC64: lhz
|
||||
; PPC64-NOT: rldicl
|
||||
; PPC64-NOT: rlwinm
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @t2a() nounwind {
|
||||
; ELF64: t2a
|
||||
; PPC64: t2a
|
||||
%1 = load i32, i32* @c, align 4
|
||||
call void @foo3(i32 zeroext %1)
|
||||
; ELF64: lwz
|
||||
; ELF64-NOT: rldicl
|
||||
; ELF64-NOT: rlwinm
|
||||
; PPC64: lwz
|
||||
; PPC64-NOT: rldicl
|
||||
; PPC64-NOT: rlwinm
|
||||
ret void
|
||||
}
|
||||
|
||||
|
|
@ -39,91 +40,91 @@ declare void @foo2(i16 zeroext)
|
|||
declare void @foo3(i32 zeroext)
|
||||
|
||||
define i32 @t3() nounwind {
|
||||
; ELF64: t3
|
||||
; PPC64: t3
|
||||
%1 = load i8, i8* @a, align 1
|
||||
%2 = zext i8 %1 to i32
|
||||
; ELF64: lbz
|
||||
; ELF64-NOT: rlwinm
|
||||
; PPC64: lbz
|
||||
; PPC64-NOT: rlwinm
|
||||
ret i32 %2
|
||||
}
|
||||
|
||||
define i32 @t4() nounwind {
|
||||
; ELF64: t4
|
||||
; PPC64: t4
|
||||
%1 = load i16, i16* @b, align 2
|
||||
%2 = zext i16 %1 to i32
|
||||
; ELF64: lhz
|
||||
; ELF64-NOT: rlwinm
|
||||
; PPC64: lhz
|
||||
; PPC64-NOT: rlwinm
|
||||
ret i32 %2
|
||||
}
|
||||
|
||||
define i32 @t5() nounwind {
|
||||
; ELF64: t5
|
||||
; PPC64: t5
|
||||
%1 = load i16, i16* @b, align 2
|
||||
%2 = sext i16 %1 to i32
|
||||
; ELF64: lha
|
||||
; ELF64-NOT: rlwinm
|
||||
; PPC64: lha
|
||||
; PPC64-NOT: rlwinm
|
||||
ret i32 %2
|
||||
}
|
||||
|
||||
define i32 @t6() nounwind {
|
||||
; ELF64: t6
|
||||
; PPC64: t6
|
||||
%1 = load i8, i8* @a, align 2
|
||||
%2 = sext i8 %1 to i32
|
||||
; ELF64: lbz
|
||||
; ELF64-NOT: rlwinm
|
||||
; PPC64: lbz
|
||||
; PPC64-NOT: rlwinm
|
||||
ret i32 %2
|
||||
}
|
||||
|
||||
define i64 @t7() nounwind {
|
||||
; ELF64: t7
|
||||
; PPC64: t7
|
||||
%1 = load i8, i8* @a, align 1
|
||||
%2 = zext i8 %1 to i64
|
||||
; ELF64: lbz
|
||||
; ELF64-NOT: rldicl
|
||||
; PPC64: lbz
|
||||
; PPC64-NOT: rldicl
|
||||
ret i64 %2
|
||||
}
|
||||
|
||||
define i64 @t8() nounwind {
|
||||
; ELF64: t8
|
||||
; PPC64: t8
|
||||
%1 = load i16, i16* @b, align 2
|
||||
%2 = zext i16 %1 to i64
|
||||
; ELF64: lhz
|
||||
; ELF64-NOT: rldicl
|
||||
; PPC64: lhz
|
||||
; PPC64-NOT: rldicl
|
||||
ret i64 %2
|
||||
}
|
||||
|
||||
define i64 @t9() nounwind {
|
||||
; ELF64: t9
|
||||
; PPC64: t9
|
||||
%1 = load i16, i16* @b, align 2
|
||||
%2 = sext i16 %1 to i64
|
||||
; ELF64: lha
|
||||
; ELF64-NOT: extsh
|
||||
; PPC64: lha
|
||||
; PPC64-NOT: extsh
|
||||
ret i64 %2
|
||||
}
|
||||
|
||||
define i64 @t10() nounwind {
|
||||
; ELF64: t10
|
||||
; PPC64: t10
|
||||
%1 = load i8, i8* @a, align 2
|
||||
%2 = sext i8 %1 to i64
|
||||
; ELF64: lbz
|
||||
; ELF64: extsb
|
||||
; PPC64: lbz
|
||||
; PPC64: extsb
|
||||
ret i64 %2
|
||||
}
|
||||
|
||||
define i64 @t11() nounwind {
|
||||
; ELF64: t11
|
||||
; PPC64: t11
|
||||
%1 = load i32, i32* @c, align 4
|
||||
%2 = zext i32 %1 to i64
|
||||
; ELF64: lwz
|
||||
; ELF64-NOT: rldicl
|
||||
; PPC64: lwz
|
||||
; PPC64-NOT: rldicl
|
||||
ret i64 %2
|
||||
}
|
||||
|
||||
define i64 @t12() nounwind {
|
||||
; ELF64: t12
|
||||
; PPC64: t12
|
||||
%1 = load i32, i32* @c, align 4
|
||||
%2 = sext i32 %1 to i64
|
||||
; ELF64: lwa
|
||||
; ELF64-NOT: extsw
|
||||
; PPC64: lwa
|
||||
; PPC64-NOT: extsw
|
||||
ret i64 %2
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,4 +1,5 @@
|
|||
; RUN: llc -verify-machineinstrs -mtriple powerpc64-unknown-linux-gnu -fast-isel -O0 < %s | FileCheck %s
|
||||
; RUN: llc -verify-machineinstrs -mtriple powerpc64-ibm-aix-xcoff -fast-isel -O0 < %s | FileCheck %s
|
||||
|
||||
; Verify that pointer offsets larger than 32 bits work correctly.
|
||||
|
||||
|
|
|
|||
|
|
@ -1,8 +1,9 @@
|
|||
; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s --check-prefix=ELF64
|
||||
; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s --check-prefix=PPC64
|
||||
; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64-ibm-aix-xcoff -mcpu=pwr7 | FileCheck %s --check-prefix=PPC64
|
||||
|
||||
define void @t1(i8* %x) nounwind {
|
||||
entry:
|
||||
; ELF64: t1
|
||||
; PPC64: t1
|
||||
br label %L0
|
||||
|
||||
L0:
|
||||
|
|
@ -10,6 +11,6 @@ L0:
|
|||
|
||||
L1:
|
||||
indirectbr i8* %x, [ label %L0, label %L1 ]
|
||||
; ELF64: mtctr 3
|
||||
; ELF64: bctr
|
||||
; PPC64: mtctr 3
|
||||
; PPC64: bctr
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,49 +1,50 @@
|
|||
; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s --check-prefix=ELF64
|
||||
; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s --check-prefix=PPC64
|
||||
; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64-ibm-aix-xcoff -mcpu=pwr7 | FileCheck %s --check-prefix=PPC64
|
||||
|
||||
define i32 @shl() nounwind {
|
||||
entry:
|
||||
; ELF64: shl
|
||||
; ELF64: slw
|
||||
; PPC64: shl
|
||||
; PPC64: slw
|
||||
%shl = shl i32 -1, 2
|
||||
ret i32 %shl
|
||||
}
|
||||
|
||||
define i32 @shl_reg(i32 %src1, i32 %src2) nounwind {
|
||||
entry:
|
||||
; ELF64: shl_reg
|
||||
; ELF64: slw
|
||||
; PPC64: shl_reg
|
||||
; PPC64: slw
|
||||
%shl = shl i32 %src1, %src2
|
||||
ret i32 %shl
|
||||
}
|
||||
|
||||
define i32 @lshr() nounwind {
|
||||
entry:
|
||||
; ELF64: lshr
|
||||
; ELF64: srw
|
||||
; PPC64: lshr
|
||||
; PPC64: srw
|
||||
%lshr = lshr i32 -1, 2
|
||||
ret i32 %lshr
|
||||
}
|
||||
|
||||
define i32 @lshr_reg(i32 %src1, i32 %src2) nounwind {
|
||||
entry:
|
||||
; ELF64: lshr_reg
|
||||
; ELF64: srw
|
||||
; PPC64: lshr_reg
|
||||
; PPC64: srw
|
||||
%lshr = lshr i32 %src1, %src2
|
||||
ret i32 %lshr
|
||||
}
|
||||
|
||||
define i32 @ashr() nounwind {
|
||||
entry:
|
||||
; ELF64: ashr
|
||||
; ELF64: srawi
|
||||
; PPC64: ashr
|
||||
; PPC64: srawi
|
||||
%ashr = ashr i32 -1, 2
|
||||
ret i32 %ashr
|
||||
}
|
||||
|
||||
define i32 @ashr_reg(i32 %src1, i32 %src2) nounwind {
|
||||
entry:
|
||||
; ELF64: ashr_reg
|
||||
; ELF64: sraw
|
||||
; PPC64: ashr_reg
|
||||
; PPC64: sraw
|
||||
%ashr = ashr i32 %src1, %src2
|
||||
ret i32 %ashr
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in a new issue