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AMDGPU: Fix assert if v_mov_b32_dpp is last instruction in the block

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This can happen if the use instruction is a phi.

Fixes issue 49961
This commit is contained in:
Matt Arsenault 2022-04-08 10:16:56 -04:00
parent b4ace5da45
commit c528fbf882
2 changed files with 56 additions and 1 deletions
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2
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
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@ -8071,7 +8071,7 @@ bool llvm::execMayBeModifiedBeforeAnyUse(const MachineRegisterInfo &MRI,
auto &UseInst = *Use.getParent();
// Don't bother searching between blocks, although it is possible this block
// doesn't modify exec.
if (UseInst.getParent() != DefBB)
if (UseInst.getParent() != DefBB || UseInst.isPHI())
return true;
if (++NumUse > MaxUseScan)

55
llvm/test/CodeGen/AMDGPU/dpp_combine.mir
View file

@ -883,3 +883,58 @@ body: |
%5:vgpr_32 = V_ADD_CO_U32_e32 %4.sub0, %4.sub0, implicit-def $vcc, implicit $exec
%6:vgpr_32 = V_ADDC_U32_e32 %4.sub1, %4.sub1, implicit-def $vcc, implicit $vcc, implicit $exec
...
# execMayBeModifiedBeforeAnyUse used to assert if the queried
# V_MOV_B32_dpp was the last instruction in the block.
---
name: mov_dpp_last_block_inst
tracksRegLiveness: true
body: |
; GCN-LABEL: name: mov_dpp_last_block_inst
; GCN: bb.0:
; GCN-NEXT: successors: %bb.1(0x80000000)
; GCN-NEXT: liveins: $vgpr0, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:sgpr_32 = COPY $sgpr8
; GCN-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GCN-NEXT: [[DEF1:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
; GCN-NEXT: [[DEF2:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
; GCN-NEXT: {{ $}}
; GCN-NEXT: bb.1:
; GCN-NEXT: successors: %bb.2(0x80000000)
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[PHI:%[0-9]+]]:vgpr_32 = PHI [[DEF]], %bb.0, %5, %bb.2
; GCN-NEXT: [[V_MOV_B32_dpp:%[0-9]+]]:vgpr_32 = V_MOV_B32_dpp [[DEF]], [[PHI]], 323, 15, 15, 0, implicit $exec
; GCN-NEXT: {{ $}}
; GCN-NEXT: bb.2:
; GCN-NEXT: successors: %bb.1(0x40000000), %bb.3(0x40000000)
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, [[DEF2]], implicit $exec
; GCN-NEXT: V_CMP_NE_U32_e32 1, [[V_CNDMASK_B32_e64_]], implicit-def $vcc, implicit $exec
; GCN-NEXT: S_CBRANCH_VCCNZ %bb.1, implicit $vcc
; GCN-NEXT: S_BRANCH %bb.3
; GCN-NEXT: {{ $}}
; GCN-NEXT: bb.3:
; GCN-NEXT: S_ENDPGM 0
bb.0:
liveins: $vgpr0, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8
%0:sgpr_32 = COPY $sgpr8
%1:vgpr_32 = IMPLICIT_DEF
%2:sreg_32 = IMPLICIT_DEF
%3:sreg_64_xexec = IMPLICIT_DEF
bb.1:
%4:vgpr_32 = PHI %1, %bb.0, %5, %bb.2
%5:vgpr_32 = V_MOV_B32_dpp %1, %4, 323, 15, 15, 0, implicit $exec
bb.2:
%6:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, %3, implicit $exec
V_CMP_NE_U32_e32 1, %6, implicit-def $vcc, implicit $exec
S_CBRANCH_VCCNZ %bb.1, implicit $vcc
S_BRANCH %bb.3
bb.3:
S_ENDPGM 0
...