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[MachineSink] Inline getRegUnits

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Reg unit sets are uniqued, so no need to wrap it in a set.
This commit is contained in:
Benjamin Kramer 2022-02-12 17:30:57 +01:00
parent 22e69afa3b
commit bee4531bee
1 changed files with 11 additions and 21 deletions
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32
llvm/lib/CodeGen/MachineSink.cpp
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@ -1081,8 +1081,7 @@ using MIRegs = std::pair<MachineInstr *, SmallVector<unsigned, 2>>;
/// Sink an instruction and its associated debug instructions.
static void performSink(MachineInstr &MI, MachineBasicBlock &SuccToSinkTo,
MachineBasicBlock::iterator InsertPos,
SmallVectorImpl<MIRegs> &DbgValuesToSink) {
ArrayRef<MIRegs> DbgValuesToSink) {
// If we cannot find a location to use (merge with), then we erase the debug
// location to prevent debug-info driven tools from potentially reporting
// wrong location information.
@ -1101,7 +1100,7 @@ static void performSink(MachineInstr &MI, MachineBasicBlock &SuccToSinkTo,
// DBG_VALUE location as 'undef', indicating that any earlier variable
// location should be terminated as we've optimised away the value at this
// point.
for (auto DbgValueToSink : DbgValuesToSink) {
for (const auto &DbgValueToSink : DbgValuesToSink) {
MachineInstr *DbgMI = DbgValueToSink.first;
MachineInstr *NewDbgMI = DbgMI->getMF()->CloneMachineInstr(DbgMI);
SuccToSinkTo.insert(InsertPos, NewDbgMI);
@ -1684,14 +1683,6 @@ static bool hasRegisterDependency(MachineInstr *MI,
return HasRegDependency;
}
static SmallSet<MCRegister, 4> getRegUnits(MCRegister Reg,
const TargetRegisterInfo *TRI) {
SmallSet<MCRegister, 4> RegUnits;
for (auto RI = MCRegUnitIterator(Reg, TRI); RI.isValid(); ++RI)
RegUnits.insert(*RI);
return RegUnits;
}
bool PostRAMachineSinking::tryToSinkCopy(MachineBasicBlock &CurBB,
MachineFunction &MF,
const TargetRegisterInfo *TRI,
@ -1737,14 +1728,15 @@ bool PostRAMachineSinking::tryToSinkCopy(MachineBasicBlock &CurBB,
}
// Record debug use of each reg unit.
SmallSet<MCRegister, 4> RegUnits = getRegUnits(MO.getReg(), TRI);
for (MCRegister Reg : RegUnits)
MIUnits[Reg].push_back(MO.getReg());
for (auto RI = MCRegUnitIterator(MO.getReg(), TRI); RI.isValid();
++RI)
MIUnits[*RI].push_back(MO.getReg());
}
}
if (IsValid) {
for (auto RegOps : MIUnits)
SeenDbgInstrs[RegOps.first].push_back({&MI, RegOps.second});
for (auto &RegOps : MIUnits)
SeenDbgInstrs[RegOps.first].emplace_back(&MI,
std::move(RegOps.second));
}
continue;
}
@ -1791,17 +1783,15 @@ bool PostRAMachineSinking::tryToSinkCopy(MachineBasicBlock &CurBB,
if (!MO.isReg() || !MO.isDef())
continue;
SmallSet<MCRegister, 4> Units = getRegUnits(MO.getReg(), TRI);
for (MCRegister Reg : Units) {
for (auto MIRegs : SeenDbgInstrs.lookup(Reg)) {
for (auto RI = MCRegUnitIterator(MO.getReg(), TRI); RI.isValid(); ++RI) {
for (const auto &MIRegs : SeenDbgInstrs.lookup(*RI)) {
auto &Regs = DbgValsToSinkMap[MIRegs.first];
for (unsigned Reg : MIRegs.second)
Regs.push_back(Reg);
}
}
}
SmallVector<MIRegs, 4> DbgValsToSink(DbgValsToSinkMap.begin(),
DbgValsToSinkMap.end());
auto DbgValsToSink = DbgValsToSinkMap.takeVector();
// Clear the kill flag if SrcReg is killed between MI and the end of the
// block.