[RISCV] Add test case for a vsetvli insertion bug found after D118667.
We're missing a vsetvli before a vse after a redsum in this test. This appears to be because the vmv.s.x has a VL of 1, but did not trigger a vsetvli because it is a scalar move op and any non-zero VL would work. So it looked at it the predecessors and decided it was that they all had a non-zero vl. Then the redsum was visited, it also took the VL from the predecessors since the vmv.s.x and the 4 was found compatible. Finally we visit the vse and it looks at the BBLocalInfo and sees that is compatible because it contains a VL of 1 from the vmv.s.x, the first instruction in the block. BBLocalInfo was not updated when the vredsum was visited because BBLocalInfo was valid and no vsetvli was generated. I think fundamentally the vmv.s.x optimization has the same first phase and third phase not matching problem that D118667 was trying to fix for stores. Differential Revision: https://reviews.llvm.org/D119516
This commit is contained in:
Craig Topper
parent
08f2b0dcf6
commit
ba9a7ae798
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@ -99,6 +99,31 @@
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ret void
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}
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define void @redusum_loop(i32* nocapture noundef readonly %a, i32 noundef signext %n, i32* nocapture noundef writeonly %res) #0 {
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entry:
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br label %vector.body
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vector.body: ; preds = %vector.body, %entry
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%lsr.iv1 = phi i32* [ %scevgep, %vector.body ], [ %a, %entry ]
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%lsr.iv = phi i64 [ %lsr.iv.next, %vector.body ], [ 2048, %entry ]
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%vec.phi = phi <4 x i32> [ zeroinitializer, %entry ], [ %0, %vector.body ]
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%lsr.iv12 = bitcast i32* %lsr.iv1 to <4 x i32>*
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%wide.load = load <4 x i32>, <4 x i32>* %lsr.iv12, align 4
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%0 = add <4 x i32> %wide.load, %vec.phi
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%lsr.iv.next = add nsw i64 %lsr.iv, -4
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%scevgep = getelementptr i32, i32* %lsr.iv1, i64 4
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%1 = icmp eq i64 %lsr.iv.next, 0
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br i1 %1, label %middle.block, label %vector.body
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middle.block: ; preds = %vector.body
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%2 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %0)
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store i32 %2, i32* %res, align 4
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ret void
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}
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; Function Attrs: nofree nosync nounwind readnone willreturn
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declare i32 @llvm.vector.reduce.add.v4i32(<4 x i32>)
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; Function Attrs: nounwind readnone
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declare <vscale x 1 x i64> @llvm.riscv.vadd.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, i64) #1
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@ -599,3 +624,112 @@ body: |
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PseudoRET
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...
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---
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name: redusum_loop
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alignment: 4
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tracksRegLiveness: true
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: gpr }
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- { id: 2, class: vr }
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- { id: 3, class: vr }
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- { id: 4, class: gpr }
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- { id: 5, class: gpr }
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- { id: 6, class: gpr }
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- { id: 7, class: gpr }
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- { id: 8, class: gpr }
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- { id: 9, class: gpr }
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- { id: 10, class: vr }
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- { id: 11, class: vr }
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- { id: 12, class: vr }
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- { id: 13, class: gpr }
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- { id: 14, class: vr }
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- { id: 15, class: vr }
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- { id: 16, class: vr }
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- { id: 17, class: vr }
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- { id: 18, class: gpr }
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- { id: 19, class: gpr }
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- { id: 20, class: vr }
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- { id: 21, class: vr }
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- { id: 22, class: vr }
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- { id: 23, class: vr }
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- { id: 24, class: vr }
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liveins:
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- { reg: '$x10', virtual-reg: '%6' }
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- { reg: '$x12', virtual-reg: '%8' }
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frameInfo:
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maxAlignment: 1
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machineFunctionInfo: {}
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body: |
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; CHECK-LABEL: name: redusum_loop
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; CHECK: bb.0.entry:
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; CHECK-NEXT: successors: %bb.1(0x80000000)
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; CHECK-NEXT: liveins: $x10, $x12
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x12
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x10
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; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 4, 80, implicit-def $vl, implicit-def $vtype
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; CHECK-NEXT: [[PseudoVMV_V_I_M1_:%[0-9]+]]:vr = PseudoVMV_V_I_M1 0, 4, 5, implicit $vl, implicit $vtype
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:vr = COPY [[PseudoVMV_V_I_M1_]]
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; CHECK-NEXT: [[COPY3:%[0-9]+]]:vr = COPY [[COPY2]]
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; CHECK-NEXT: [[LUI:%[0-9]+]]:gpr = LUI 1
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; CHECK-NEXT: [[ADDIW:%[0-9]+]]:gpr = ADDIW killed [[LUI]], -2048
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.1.vector.body:
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; CHECK-NEXT: successors: %bb.2(0x04000000), %bb.1(0x7c000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[PHI:%[0-9]+]]:gpr = PHI [[COPY1]], %bb.0, %5, %bb.1
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; CHECK-NEXT: [[PHI1:%[0-9]+]]:gpr = PHI [[ADDIW]], %bb.0, %4, %bb.1
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; CHECK-NEXT: [[PHI2:%[0-9]+]]:vr = PHI [[COPY3]], %bb.0, %16, %bb.1
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; CHECK-NEXT: [[PseudoVLE32_V_M1_:%[0-9]+]]:vr = PseudoVLE32_V_M1 [[PHI]], 4, 5, implicit $vl, implicit $vtype :: (load (s128) from %ir.lsr.iv12, align 4)
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; CHECK-NEXT: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 killed [[PseudoVLE32_V_M1_]], [[PHI2]], 4, 5, implicit $vl, implicit $vtype
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; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = nsw ADDI [[PHI1]], -4
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; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI [[PHI]], 16
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; CHECK-NEXT: [[COPY4:%[0-9]+]]:gpr = COPY $x0
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; CHECK-NEXT: BNE [[ADDI]], [[COPY4]], %bb.1
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; CHECK-NEXT: PseudoBR %bb.2
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.2.middle.block:
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; CHECK-NEXT: [[COPY5:%[0-9]+]]:gpr = COPY $x0
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; CHECK-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF
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; CHECK-NEXT: [[PseudoVMV_S_X_M1_:%[0-9]+]]:vr = PseudoVMV_S_X_M1 [[DEF]], [[COPY5]], 1, 5, implicit $vl, implicit $vtype
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; CHECK-NEXT: [[DEF1:%[0-9]+]]:vr = IMPLICIT_DEF
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; CHECK-NEXT: [[PseudoVREDSUM_VS_M1_:%[0-9]+]]:vr = PseudoVREDSUM_VS_M1 [[DEF1]], [[PseudoVADD_VV_M1_]], killed [[PseudoVMV_S_X_M1_]], 4, 5, implicit $vl, implicit $vtype
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; FIXME: There should be a VSETVLI here.
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; CHECK-NEXT: PseudoVSE32_V_M1 killed [[PseudoVREDSUM_VS_M1_]], [[COPY]], 1, 5, implicit $vl, implicit $vtype :: (store (s32) into %ir.res)
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; CHECK-NEXT: PseudoRET
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bb.0.entry:
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liveins: $x10, $x12
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%8:gpr = COPY $x12
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%6:gpr = COPY $x10
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%11:vr = PseudoVMV_V_I_M1 0, 4, 5
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%12:vr = COPY %11
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%10:vr = COPY %12
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%13:gpr = LUI 1
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%9:gpr = ADDIW killed %13, -2048
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bb.1.vector.body:
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successors: %bb.2(0x04000000), %bb.1(0x7c000000)
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%0:gpr = PHI %6, %bb.0, %5, %bb.1
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%1:gpr = PHI %9, %bb.0, %4, %bb.1
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%2:vr = PHI %10, %bb.0, %16, %bb.1
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%14:vr = PseudoVLE32_V_M1 %0, 4, 5 :: (load (s128) from %ir.lsr.iv12, align 4)
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%16:vr = PseudoVADD_VV_M1 killed %14, %2, 4, 5
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%4:gpr = nsw ADDI %1, -4
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%5:gpr = ADDI %0, 16
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%18:gpr = COPY $x0
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BNE %4, %18, %bb.1
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PseudoBR %bb.2
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bb.2.middle.block:
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%19:gpr = COPY $x0
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%21:vr = IMPLICIT_DEF
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%20:vr = PseudoVMV_S_X_M1 %21, %19, 1, 5
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%24:vr = IMPLICIT_DEF
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%23:vr = PseudoVREDSUM_VS_M1 %24, %16, killed %20, 4, 5
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PseudoVSE32_V_M1 killed %23, %8, 1, 5 :: (store (s32) into %ir.res)
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PseudoRET
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...
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