[RISCV] Don't combine ROTR ((GREV x, 24), 16)->(GREV x, 8) on RV64.
This miscompile was introduced in D119527. This was a special pattern for rotate+bswap on RV32. It doesn't work for RV64 since the rotate needs to be half the bitwidth. The equivalent pattern for RV64 is ROTR ((GREV x, 56), 32) so match that instead. This could be generalized further as noted in the new FIXME. Reviewed By: Chenbing.Zheng Differential Revision: https://reviews.llvm.org/D120686
This commit is contained in:
Craig Topper
parent
ac93f95861
commit
a1f8349d77
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@ -7346,45 +7346,57 @@ static SDValue transformAddShlImm(SDNode *N, SelectionDAG &DAG,
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}
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// Combine
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// ROTR ((GREV x, 24), 16) -> (GREVI x, 8)
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// ROTL ((GREV x, 24), 16) -> (GREVI x, 8)
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// RORW ((GREVW x, 24), 16) -> (GREVIW x, 8)
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// ROLW ((GREVW x, 24), 16) -> (GREVIW x, 8)
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// ROTR ((GREV x, 24), 16) -> (GREVI x, 8) for RV32
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// ROTL ((GREV x, 24), 16) -> (GREVI x, 8) for RV32
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// ROTR ((GREV x, 56), 32) -> (GREVI x, 24) for RV64
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// ROTL ((GREV x, 56), 32) -> (GREVI x, 24) for RV64
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// RORW ((GREVW x, 24), 16) -> (GREVIW x, 8) for RV64
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// ROLW ((GREVW x, 24), 16) -> (GREVIW x, 8) for RV64
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// The grev patterns represents BSWAP.
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// FIXME: This can be generalized to any GREV. We just need to toggle the MSB
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// off the grev.
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static SDValue combineROTR_ROTL_RORW_ROLW(SDNode *N, SelectionDAG &DAG,
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const RISCVSubtarget &Subtarget) {
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bool IsWInstruction =
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N->getOpcode() == RISCVISD::RORW || N->getOpcode() == RISCVISD::ROLW;
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assert((N->getOpcode() == ISD::ROTR || N->getOpcode() == ISD::ROTL ||
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N->getOpcode() == RISCVISD::RORW ||
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N->getOpcode() == RISCVISD::ROLW) &&
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IsWInstruction) &&
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"Unexpected opcode!");
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SDValue Src = N->getOperand(0);
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EVT VT = N->getValueType(0);
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SDLoc DL(N);
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unsigned Opc;
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if (!Subtarget.hasStdExtZbp())
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return SDValue();
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if ((N->getOpcode() == ISD::ROTR || N->getOpcode() == ISD::ROTL) &&
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Src.getOpcode() == RISCVISD::GREV)
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Opc = RISCVISD::GREV;
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else if ((N->getOpcode() == RISCVISD::RORW ||
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N->getOpcode() == RISCVISD::ROLW) &&
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Src.getOpcode() == RISCVISD::GREVW)
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Opc = RISCVISD::GREVW;
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else
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unsigned GrevOpc = IsWInstruction ? RISCVISD::GREVW : RISCVISD::GREV;
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if (Src.getOpcode() != GrevOpc)
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return SDValue();
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if (!isa<ConstantSDNode>(N->getOperand(1)) ||
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!isa<ConstantSDNode>(Src.getOperand(1)))
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return SDValue();
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unsigned BitWidth = IsWInstruction ? 32 : VT.getSizeInBits();
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assert(isPowerOf2_32(BitWidth) && "Expected a power of 2");
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// Needs to be a rotate by half the bitwidth for ROTR/ROTL or by 16 for
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// RORW/ROLW. And the grev should be the encoding for bswap for this width.
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unsigned ShAmt1 = N->getConstantOperandVal(1);
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unsigned ShAmt2 = Src.getConstantOperandVal(1);
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if (ShAmt1 != 16 && ShAmt2 != 24)
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if (BitWidth < 16 || ShAmt1 != (BitWidth / 2) || ShAmt2 != (BitWidth - 8))
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return SDValue();
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Src = Src.getOperand(0);
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return DAG.getNode(Opc, DL, N->getValueType(0), Src,
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DAG.getConstant(8, DL, N->getOperand(1).getValueType()));
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// Toggle bit the MSB of the shift.
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unsigned CombinedShAmt = ShAmt1 ^ ShAmt2;
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if (CombinedShAmt == 0)
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return Src;
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return DAG.getNode(
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GrevOpc, DL, VT, Src,
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DAG.getConstant(CombinedShAmt, DL, N->getOperand(1).getValueType()));
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}
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// Combine (GREVI (GREVI x, C2), C1) -> (GREVI x, C1^C2) when C1^C2 is
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@ -340,11 +340,13 @@ define i64 @grevi64(i64 %a) nounwind {
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ret i64 %tmp
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}
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; FIXME: This is miscompiled. We can't fold the rotate with the grev.
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; Make sure we don't fold this rotate with the grev. We can only fold a rotate
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; by 32.
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define i64 @grevi64_24_rotl_16(i64 %a) nounwind {
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; RV64ZBP-LABEL: grevi64_24_rotl_16:
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; RV64ZBP: # %bb.0:
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; RV64ZBP-NEXT: rev8.h a0, a0
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; RV64ZBP-NEXT: rev8.w a0, a0
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; RV64ZBP-NEXT: rori a0, a0, 48
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; RV64ZBP-NEXT: ret
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%tmp = call i64 @llvm.riscv.grev.i64(i64 %a, i64 24)
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%tmp1 = call i64 @llvm.fshl.i64(i64 %tmp, i64 %tmp, i64 16)
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@ -352,11 +354,13 @@ define i64 @grevi64_24_rotl_16(i64 %a) nounwind {
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}
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declare i64 @llvm.fshl.i64(i64, i64, i64)
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; FIXME: This is miscompiled. We can't fold the rotate with the grev.
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; Make sure we don't fold this rotate with the grev. We can only fold a rotate
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; by 32.
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define i64 @grevi64_24_rotr_16(i64 %a) nounwind {
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; RV64ZBP-LABEL: grevi64_24_rotr_16:
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; RV64ZBP: # %bb.0:
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; RV64ZBP-NEXT: rev8.h a0, a0
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; RV64ZBP-NEXT: rev8.w a0, a0
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; RV64ZBP-NEXT: rori a0, a0, 16
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; RV64ZBP-NEXT: ret
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%tmp = call i64 @llvm.riscv.grev.i64(i64 %a, i64 24)
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%tmp1 = call i64 @llvm.fshr.i64(i64 %tmp, i64 %tmp, i64 16)
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@ -2745,6 +2745,96 @@ define i32 @bswap_rotl_i32(i32 %a) {
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ret i32 %2
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}
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define i64 @bswap_rotr_i64(i64 %a) {
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; RV64I-LABEL: bswap_rotr_i64:
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; RV64I: # %bb.0:
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; RV64I-NEXT: srli a1, a0, 24
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; RV64I-NEXT: lui a2, 4080
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; RV64I-NEXT: and a1, a1, a2
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; RV64I-NEXT: srli a2, a0, 8
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; RV64I-NEXT: li a3, 255
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; RV64I-NEXT: slli a4, a3, 24
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; RV64I-NEXT: and a2, a2, a4
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; RV64I-NEXT: or a1, a2, a1
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; RV64I-NEXT: srli a2, a0, 40
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; RV64I-NEXT: lui a4, 16
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; RV64I-NEXT: addiw a4, a4, -256
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; RV64I-NEXT: and a2, a2, a4
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; RV64I-NEXT: srli a4, a0, 56
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; RV64I-NEXT: or a2, a2, a4
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; RV64I-NEXT: or a1, a1, a2
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; RV64I-NEXT: slli a2, a0, 24
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; RV64I-NEXT: slli a4, a3, 40
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; RV64I-NEXT: and a2, a2, a4
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; RV64I-NEXT: srliw a4, a0, 24
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; RV64I-NEXT: slli a4, a4, 32
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; RV64I-NEXT: or a2, a2, a4
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; RV64I-NEXT: slli a4, a0, 40
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; RV64I-NEXT: slli a3, a3, 48
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; RV64I-NEXT: and a3, a4, a3
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; RV64I-NEXT: slli a0, a0, 56
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; RV64I-NEXT: or a0, a0, a3
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; RV64I-NEXT: or a0, a0, a2
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; RV64I-NEXT: or a0, a0, a1
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; RV64I-NEXT: slli a1, a0, 32
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; RV64I-NEXT: srli a0, a0, 32
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; RV64I-NEXT: or a0, a0, a1
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; RV64I-NEXT: ret
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;
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; RV64ZBP-LABEL: bswap_rotr_i64:
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; RV64ZBP: # %bb.0:
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; RV64ZBP-NEXT: rev8.w a0, a0
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; RV64ZBP-NEXT: ret
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%1 = call i64 @llvm.bswap.i64(i64 %a)
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%2 = call i64 @llvm.fshr.i64(i64 %1, i64 %1, i64 32)
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ret i64 %2
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}
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define i64 @bswap_rotl_i64(i64 %a) {
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; RV64I-LABEL: bswap_rotl_i64:
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; RV64I: # %bb.0:
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; RV64I-NEXT: srli a1, a0, 24
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; RV64I-NEXT: lui a2, 4080
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; RV64I-NEXT: and a1, a1, a2
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; RV64I-NEXT: srli a2, a0, 8
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; RV64I-NEXT: li a3, 255
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; RV64I-NEXT: slli a4, a3, 24
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; RV64I-NEXT: and a2, a2, a4
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; RV64I-NEXT: or a1, a2, a1
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; RV64I-NEXT: srli a2, a0, 40
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; RV64I-NEXT: lui a4, 16
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; RV64I-NEXT: addiw a4, a4, -256
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; RV64I-NEXT: and a2, a2, a4
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; RV64I-NEXT: srli a4, a0, 56
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; RV64I-NEXT: or a2, a2, a4
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; RV64I-NEXT: or a1, a1, a2
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; RV64I-NEXT: slli a2, a0, 24
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; RV64I-NEXT: slli a4, a3, 40
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; RV64I-NEXT: and a2, a2, a4
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; RV64I-NEXT: srliw a4, a0, 24
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; RV64I-NEXT: slli a4, a4, 32
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; RV64I-NEXT: or a2, a2, a4
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; RV64I-NEXT: slli a4, a0, 40
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; RV64I-NEXT: slli a3, a3, 48
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; RV64I-NEXT: and a3, a4, a3
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; RV64I-NEXT: slli a0, a0, 56
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; RV64I-NEXT: or a0, a0, a3
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; RV64I-NEXT: or a0, a0, a2
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; RV64I-NEXT: or a0, a0, a1
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; RV64I-NEXT: srli a1, a0, 32
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; RV64I-NEXT: slli a0, a0, 32
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; RV64I-NEXT: or a0, a0, a1
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; RV64I-NEXT: ret
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;
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; RV64ZBP-LABEL: bswap_rotl_i64:
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; RV64ZBP: # %bb.0:
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; RV64ZBP-NEXT: rev8.w a0, a0
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; RV64ZBP-NEXT: ret
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%1 = call i64 @llvm.bswap.i64(i64 %a)
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%2 = call i64 @llvm.fshl.i64(i64 %1, i64 %1, i64 32)
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ret i64 %2
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}
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define i32 @bitreverse_bswap_i32(i32 %a) {
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; RV64I-LABEL: bitreverse_bswap_i32:
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; RV64I: # %bb.0:
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@ -2783,20 +2873,20 @@ define i32 @bitreverse_bswap_i32(i32 %a) {
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define i64 @bitreverse_bswap_i64(i64 %a) {
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; RV64I-LABEL: bitreverse_bswap_i64:
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; RV64I: # %bb.0:
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; RV64I-NEXT: lui a1, %hi(.LCPI76_0)
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; RV64I-NEXT: ld a1, %lo(.LCPI76_0)(a1)
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; RV64I-NEXT: lui a1, %hi(.LCPI78_0)
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; RV64I-NEXT: ld a1, %lo(.LCPI78_0)(a1)
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; RV64I-NEXT: srli a2, a0, 4
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; RV64I-NEXT: and a2, a2, a1
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; RV64I-NEXT: and a0, a0, a1
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; RV64I-NEXT: lui a1, %hi(.LCPI76_1)
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; RV64I-NEXT: ld a1, %lo(.LCPI76_1)(a1)
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; RV64I-NEXT: lui a1, %hi(.LCPI78_1)
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; RV64I-NEXT: ld a1, %lo(.LCPI78_1)(a1)
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; RV64I-NEXT: slli a0, a0, 4
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; RV64I-NEXT: or a0, a2, a0
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; RV64I-NEXT: srli a2, a0, 2
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; RV64I-NEXT: and a2, a2, a1
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; RV64I-NEXT: and a0, a0, a1
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; RV64I-NEXT: lui a1, %hi(.LCPI76_2)
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; RV64I-NEXT: ld a1, %lo(.LCPI76_2)(a1)
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; RV64I-NEXT: lui a1, %hi(.LCPI78_2)
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; RV64I-NEXT: ld a1, %lo(.LCPI78_2)(a1)
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; RV64I-NEXT: slli a0, a0, 2
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; RV64I-NEXT: or a0, a2, a0
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; RV64I-NEXT: srli a2, a0, 1
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@ -2850,14 +2940,14 @@ define signext i32 @shfl1_i32(i32 signext %a, i32 signext %b) nounwind {
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define i64 @shfl1_i64(i64 %a, i64 %b) nounwind {
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; RV64I-LABEL: shfl1_i64:
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; RV64I: # %bb.0:
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; RV64I-NEXT: lui a1, %hi(.LCPI78_1)
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; RV64I-NEXT: ld a1, %lo(.LCPI78_1)(a1)
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; RV64I-NEXT: lui a2, %hi(.LCPI78_0)
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; RV64I-NEXT: ld a2, %lo(.LCPI78_0)(a2)
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; RV64I-NEXT: lui a1, %hi(.LCPI80_1)
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; RV64I-NEXT: ld a1, %lo(.LCPI80_1)(a1)
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; RV64I-NEXT: lui a2, %hi(.LCPI80_0)
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; RV64I-NEXT: ld a2, %lo(.LCPI80_0)(a2)
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; RV64I-NEXT: slli a3, a0, 1
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; RV64I-NEXT: and a1, a3, a1
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; RV64I-NEXT: lui a3, %hi(.LCPI78_2)
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; RV64I-NEXT: ld a3, %lo(.LCPI78_2)(a3)
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; RV64I-NEXT: lui a3, %hi(.LCPI80_2)
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; RV64I-NEXT: ld a3, %lo(.LCPI80_2)(a3)
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; RV64I-NEXT: and a2, a0, a2
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; RV64I-NEXT: or a1, a2, a1
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; RV64I-NEXT: srli a0, a0, 1
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@ -2914,14 +3004,14 @@ define signext i32 @shfl2_i32(i32 signext %a, i32 signext %b) nounwind {
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define i64 @shfl2_i64(i64 %a, i64 %b) nounwind {
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; RV64I-LABEL: shfl2_i64:
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; RV64I: # %bb.0:
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; RV64I-NEXT: lui a1, %hi(.LCPI80_1)
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; RV64I-NEXT: ld a1, %lo(.LCPI80_1)(a1)
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; RV64I-NEXT: lui a2, %hi(.LCPI80_0)
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; RV64I-NEXT: ld a2, %lo(.LCPI80_0)(a2)
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; RV64I-NEXT: lui a1, %hi(.LCPI82_1)
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; RV64I-NEXT: ld a1, %lo(.LCPI82_1)(a1)
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; RV64I-NEXT: lui a2, %hi(.LCPI82_0)
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; RV64I-NEXT: ld a2, %lo(.LCPI82_0)(a2)
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; RV64I-NEXT: slli a3, a0, 2
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; RV64I-NEXT: and a1, a3, a1
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; RV64I-NEXT: lui a3, %hi(.LCPI80_2)
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; RV64I-NEXT: ld a3, %lo(.LCPI80_2)(a3)
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; RV64I-NEXT: lui a3, %hi(.LCPI82_2)
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; RV64I-NEXT: ld a3, %lo(.LCPI82_2)(a3)
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; RV64I-NEXT: and a2, a0, a2
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; RV64I-NEXT: or a1, a2, a1
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; RV64I-NEXT: srli a0, a0, 2
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@ -2978,13 +3068,13 @@ define signext i32 @shfl4_i32(i32 signext %a, i32 signext %b) nounwind {
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define i64 @shfl4_i64(i64 %a, i64 %b) nounwind {
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; RV64I-LABEL: shfl4_i64:
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; RV64I: # %bb.0:
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; RV64I-NEXT: lui a1, %hi(.LCPI82_0)
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; RV64I-NEXT: ld a1, %lo(.LCPI82_0)(a1)
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; RV64I-NEXT: lui a2, %hi(.LCPI82_1)
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; RV64I-NEXT: ld a2, %lo(.LCPI82_1)(a2)
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; RV64I-NEXT: lui a1, %hi(.LCPI84_0)
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; RV64I-NEXT: ld a1, %lo(.LCPI84_0)(a1)
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; RV64I-NEXT: lui a2, %hi(.LCPI84_1)
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; RV64I-NEXT: ld a2, %lo(.LCPI84_1)(a2)
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; RV64I-NEXT: slli a3, a0, 4
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; RV64I-NEXT: lui a4, %hi(.LCPI82_2)
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; RV64I-NEXT: ld a4, %lo(.LCPI82_2)(a4)
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; RV64I-NEXT: lui a4, %hi(.LCPI84_2)
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; RV64I-NEXT: ld a4, %lo(.LCPI84_2)(a4)
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; RV64I-NEXT: and a2, a3, a2
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; RV64I-NEXT: and a1, a0, a1
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; RV64I-NEXT: srli a0, a0, 4
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