[AArch64] Fix the upper limit for folded address offsets for COFF
In COFF, the immediates in IMAGE_REL_ARM64_PAGEBASE_REL21 relocations are limited to 21 bit signed, i.e. the offset has to be less than (1 << 20). The previous limit did intend to cover for this case, but had missed that the 21 bit field was signed. This fixes issue https://github.com/llvm/llvm-project/issues/54753. Differential Revision: https://reviews.llvm.org/D123160
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@ -17929,13 +17929,14 @@ static SDValue performGlobalAddressCombine(SDNode *N, SelectionDAG &DAG,
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// Check whether folding this offset is legal. It must not go out of bounds of
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// the referenced object to avoid violating the code model, and must be
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// smaller than 2^21 because this is the largest offset expressible in all
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// object formats.
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// smaller than 2^20 because this is the largest offset expressible in all
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// object formats. (The IMAGE_REL_ARM64_PAGEBASE_REL21 relocation in COFF
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// stores an immediate signed 21 bit offset.)
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//
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// This check also prevents us from folding negative offsets, which will end
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// up being treated in the same way as large positive ones. They could also
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// cause code model violations, and aren't really common enough to matter.
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if (Offset >= (1 << 21))
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if (Offset >= (1 << 20))
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return SDValue();
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const GlobalValue *GV = GN->getGlobal();
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@ -163,13 +163,14 @@ static bool matchFoldGlobalOffset(MachineInstr &MI, MachineRegisterInfo &MRI,
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// Check whether folding this offset is legal. It must not go out of bounds of
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// the referenced object to avoid violating the code model, and must be
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// smaller than 2^21 because this is the largest offset expressible in all
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// object formats.
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// smaller than 2^20 because this is the largest offset expressible in all
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// object formats. (The IMAGE_REL_ARM64_PAGEBASE_REL21 relocation in COFF
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// stores an immediate signed 21 bit offset.)
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//
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// This check also prevents us from folding negative offsets, which will end
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// up being treated in the same way as large positive ones. They could also
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// cause code model violations, and aren't really common enough to matter.
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if (NewOffset >= (1 << 21))
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if (NewOffset >= (1 << 20))
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return false;
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Type *T = GV->getValueType();
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@ -84,23 +84,23 @@ define [2 x i64] @f4() {
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define i64 @f5() {
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; CHECK-LABEL: f5:
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; CHECK: // %bb.0:
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; CHECK-NEXT: adrp x8, x2+2097144
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; CHECK-NEXT: ldr x0, [x8, :lo12:x2+2097144]
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; CHECK-NEXT: adrp x8, x2+1048568
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; CHECK-NEXT: ldr x0, [x8, :lo12:x2+1048568]
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; CHECK-NEXT: ret
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;
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; GISEL-LABEL: f5:
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; GISEL: // %bb.0:
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; GISEL-NEXT: adrp x8, x2+2097144
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; GISEL-NEXT: ldr x0, [x8, :lo12:x2+2097144]
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; GISEL-NEXT: adrp x8, x2+1048568
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; GISEL-NEXT: ldr x0, [x8, :lo12:x2+1048568]
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; GISEL-NEXT: ret
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%l = load i64, i64* getelementptr ([16777216 x i64], [16777216 x i64]* @x2, i64 0, i64 262143)
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%l = load i64, i64* getelementptr ([16777216 x i64], [16777216 x i64]* @x2, i64 0, i64 131071)
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ret i64 %l
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}
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define i64 @f6() {
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; CHECK-LABEL: f6:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w8, #2097152
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; CHECK-NEXT: mov w8, #1048576
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; CHECK-NEXT: adrp x9, x2
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; CHECK-NEXT: add x9, x9, :lo12:x2
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; CHECK-NEXT: ldr x0, [x9, x8]
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@ -108,12 +108,12 @@ define i64 @f6() {
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;
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; GISEL-LABEL: f6:
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; GISEL: // %bb.0:
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; GISEL-NEXT: mov w8, #2097152
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; GISEL-NEXT: mov w8, #1048576
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; GISEL-NEXT: adrp x9, x2
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; GISEL-NEXT: add x9, x9, :lo12:x2
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; GISEL-NEXT: ldr x0, [x9, x8]
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; GISEL-NEXT: ret
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%l = load i64, i64* getelementptr ([16777216 x i64], [16777216 x i64]* @x2, i64 0, i64 262144)
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%l = load i64, i64* getelementptr ([16777216 x i64], [16777216 x i64]* @x2, i64 0, i64 131072)
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ret i64 %l
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}
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