[VE][NFCi] Remove unused tablegen parameters
TableGen has started warning about unused template parameters in the isel patterns. Remove those. Reviewed By: kaz7 Differential Revision: https://reviews.llvm.org/D113675
This commit is contained in:
Simon Moll
parent
4e94e25c90
commit
751aa6c280
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@ -634,9 +634,7 @@ multiclass RRIm<string opcStr, bits<8>opc,
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// Special RR multiclass for 128 bits shift left instruction.
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// e.g. SLD
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let Constraints = "$hi = $sx", DisableEncoding = "$hi", hasSideEffects = 0 in
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multiclass RRILDm<string opcStr, bits<8>opc,
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RegisterClass RC, ValueType Ty,
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SDPatternOperator OpNode = null_frag> {
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multiclass RRILDm<string opcStr, bits<8>opc, RegisterClass RC> {
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def rrr : RR<opc, (outs RC:$sx), (ins RC:$hi, RC:$sz, I32:$sy),
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!strconcat(opcStr, " $sx, $sz, $sy")>;
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let cz = 0 in
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@ -653,9 +651,7 @@ multiclass RRILDm<string opcStr, bits<8>opc,
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// Special RR multiclass for 128 bits shift right instruction.
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// e.g. SRD
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let Constraints = "$low = $sx", DisableEncoding = "$low", hasSideEffects = 0 in
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multiclass RRIRDm<string opcStr, bits<8>opc,
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RegisterClass RC, ValueType Ty,
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SDPatternOperator OpNode = null_frag> {
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multiclass RRIRDm<string opcStr, bits<8>opc, RegisterClass RC> {
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def rrr : RR<opc, (outs RC:$sx), (ins RC:$sz, RC:$low, I32:$sy),
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!strconcat(opcStr, " $sx, $sz, $sy")>;
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let cz = 0 in
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@ -685,7 +681,7 @@ multiclass RRI1m<string opcStr, bits<8>opc, RegisterClass RC, ValueType Ty,
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// Special RR multiclass for MRG instruction.
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// e.g. MRG
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let Constraints = "$sx = $sd", DisableEncoding = "$sd", hasSideEffects = 0 in
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multiclass RRMRGm<string opcStr, bits<8>opc, RegisterClass RC, ValueType Ty> {
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multiclass RRMRGm<string opcStr, bits<8>opc, RegisterClass RC> {
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def rr : RR<opc, (outs RC:$sx), (ins RC:$sy, RC:$sz, RC:$sd),
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!strconcat(opcStr, " $sx, $sy, $sz")>;
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let cy = 0 in
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@ -719,7 +715,7 @@ multiclass RRSWPm<string opcStr, bits<8>opc,
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// e.g. CMOVL, CMOVW, CMOVD, and etc.
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let Constraints = "$sx = $sd", DisableEncoding = "$sd", hasSideEffects = 0,
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cfw = ? in
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multiclass RRCMOVm<string opcStr, bits<8>opc, RegisterClass RC, ValueType Ty> {
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multiclass RRCMOVm<string opcStr, bits<8>opc, RegisterClass RC> {
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def rr : RR<opc, (outs I64:$sx), (ins CCOp:$cfw, RC:$sy, I64:$sz, I64:$sd),
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!strconcat(opcStr, " $sx, $sz, $sy")>;
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let cy = 0 in
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@ -740,8 +736,8 @@ multiclass RRCMOVm<string opcStr, bits<8>opc, RegisterClass RC, ValueType Ty> {
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// e.g. CVTWDSX, CVTWDZX, CVTWSSX, and etc.
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// sz{3-0} = rounding mode
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let cz = 0, hasSideEffects = 0 in
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multiclass CVTRDm<string opcStr, bits<8> opc, RegisterClass RCo, ValueType Tyo,
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RegisterClass RCi, ValueType Tyi> {
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multiclass CVTRDm<string opcStr, bits<8> opc, RegisterClass RCo,
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RegisterClass RCi> {
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def r : RR<opc, (outs RCo:$sx), (ins RDOp:$rd, RCi:$sy),
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!strconcat(opcStr, "${rd} $sx, $sy")> {
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bits<4> rd;
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@ -1265,7 +1261,7 @@ let isReMaterializable = 1, isAsCheapAsAMove = 1 in
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defm NND : RRNCm<"nnd", 0x54, I64, i64, and_not>;
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// Section 8.5.6 - MRG (Merge)
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defm MRG : RRMRGm<"mrg", 0x56, I64, i64>;
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defm MRG : RRMRGm<"mrg", 0x56, I64>;
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// Section 8.5.7 - LDZ (Leading Zero Count)
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def ctlz_pat : PatFrags<(ops node:$src),
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@ -1297,10 +1293,10 @@ def : Pat<(i32 (bswap (i32 mimm:$src))),
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(EXTRACT_SUBREG (BSWPmi (MIMM $src), 1), sub_i32)>;
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// Section 8.5.11 - CMOV (Conditional Move)
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let cw = 0, cw2 = 0 in defm CMOVL : RRCMOVm<"cmov.l.${cfw}", 0x3B, I64, i64>;
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let cw = 1, cw2 = 0 in defm CMOVW : RRCMOVm<"cmov.w.${cfw}", 0x3B, I32, i32>;
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let cw = 0, cw2 = 1 in defm CMOVD : RRCMOVm<"cmov.d.${cfw}", 0x3B, I64, f64>;
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let cw = 1, cw2 = 1 in defm CMOVS : RRCMOVm<"cmov.s.${cfw}", 0x3B, F32, f32>;
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let cw = 0, cw2 = 0 in defm CMOVL : RRCMOVm<"cmov.l.${cfw}", 0x3B, I64>;
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let cw = 1, cw2 = 0 in defm CMOVW : RRCMOVm<"cmov.w.${cfw}", 0x3B, I32>;
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let cw = 0, cw2 = 1 in defm CMOVD : RRCMOVm<"cmov.d.${cfw}", 0x3B, I64>;
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let cw = 1, cw2 = 1 in defm CMOVS : RRCMOVm<"cmov.s.${cfw}", 0x3B, F32>;
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def : MnemonicAlias<"cmov.l", "cmov.l.at">;
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def : MnemonicAlias<"cmov.w", "cmov.w.at">;
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def : MnemonicAlias<"cmov.d", "cmov.d.at">;
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@ -1315,14 +1311,14 @@ let isReMaterializable = 1, isAsCheapAsAMove = 1 in
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defm SLL : RRIm<"sll", 0x65, I64, i64, shl>;
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// Section 8.6.2 - SLD (Shift Left Double)
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defm SLD : RRILDm<"sld", 0x64, I64, i64>;
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defm SLD : RRILDm<"sld", 0x64, I64>;
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// Section 8.6.3 - SRL (Shift Right Logical)
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let isReMaterializable = 1, isAsCheapAsAMove = 1 in
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defm SRL : RRIm<"srl", 0x75, I64, i64, srl>;
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// Section 8.6.4 - SRD (Shift Right Double)
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defm SRD : RRIRDm<"srd", 0x74, I64, i64>;
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defm SRD : RRIRDm<"srd", 0x74, I64>;
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let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
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@ -1405,16 +1401,16 @@ defm FCMPQ : RRNCbm<"fcmp.q", 0x7D, I64, f64, F128, f128, null_frag, simm7fp,
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// Section 8.7.11 - FIX (Convert to Fixed Point)
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// cx: double/float, cw: sx/zx, sz{0-3} = round
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let cx = 0, cw = 0 /* sign extend */ in
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defm CVTWDSX : CVTRDm<"cvt.w.d.sx", 0x4E, I32, i32, I64, f64>;
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defm CVTWDSX : CVTRDm<"cvt.w.d.sx", 0x4E, I32, I64>;
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let cx = 0, cw = 1 /* zero extend */ in
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defm CVTWDZX : CVTRDm<"cvt.w.d.zx", 0x4E, I32, i32, I64, f64>;
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defm CVTWDZX : CVTRDm<"cvt.w.d.zx", 0x4E, I32, I64>;
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let cx = 1, cw = 0 /* sign extend */ in
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defm CVTWSSX : CVTRDm<"cvt.w.s.sx", 0x4E, I32, i32, F32, f32>;
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defm CVTWSSX : CVTRDm<"cvt.w.s.sx", 0x4E, I32, F32>;
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let cx = 1, cw = 1 /* zero extend */ in
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defm CVTWSZX : CVTRDm<"cvt.w.s.zx", 0x4E, I32, i32, F32, f32>;
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defm CVTWSZX : CVTRDm<"cvt.w.s.zx", 0x4E, I32, F32>;
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// Section 8.7.12 - FIXX (Convert to Fixed Point)
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defm CVTLD : CVTRDm<"cvt.l.d", 0x4F, I64, i64, I64, f64>;
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defm CVTLD : CVTRDm<"cvt.l.d", 0x4F, I64, I64>;
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// Section 8.7.13 - FLT (Convert to Floating Point)
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defm CVTDW : CVTm<"cvt.d.w", 0x5E, I64, f64, I32, i32, sint_to_fp>;
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@ -1836,7 +1832,7 @@ multiclass ZXATMLDm<SDPatternOperator from, int VAL,
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def : Pat<(i64 (and (anyext (from ADDRzii:$addr)), VAL)),
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(i2l (tozii MEMzii:$addr))>;
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}
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multiclass ZXATMLD32m<SDPatternOperator from, int VAL,
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multiclass ZXATMLD32m<SDPatternOperator from,
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RM torri, RM torii,
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RM tozri, RM tozii> {
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def : Pat<(i64 (zext (from ADDRrri:$addr))),
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@ -1852,8 +1848,7 @@ defm : ZXATMLDm<atomic_load_8, 0xFF, LD1BZXrri, LD1BZXrii, LD1BZXzri,
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LD1BZXzii>;
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defm : ZXATMLDm<atomic_load_16, 0xFFFF, LD2BZXrri, LD2BZXrii, LD2BZXzri,
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LD2BZXzii>;
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defm : ZXATMLD32m<atomic_load_32, 0xFFFFFFFF, LDLZXrri, LDLZXrii, LDLZXzri,
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LDLZXzii>;
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defm : ZXATMLD32m<atomic_load_32, LDLZXrri, LDLZXrii, LDLZXzri, LDLZXzii>;
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// Atomic stores
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multiclass ATMSTm<SDPatternOperator from, ValueType ty,
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@ -1871,7 +1866,6 @@ defm : ATMSTm<atomic_store_64, i64, STrri, STrii, STzri, STzii>;
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// Optimized atomic stores with truncate
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multiclass TRATMSTm<SDPatternOperator from,
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ValueType ty,
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RM torri,
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RM torii,
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RM tozri,
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@ -1885,9 +1879,9 @@ multiclass TRATMSTm<SDPatternOperator from,
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def : Pat<(from ADDRzii:$addr, (i32 (trunc i64:$src))),
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(tozii MEMzii:$addr, (EXTRACT_SUBREG $src, sub_i32))>;
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}
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defm : TRATMSTm<atomic_store_8, i32, ST1Brri, ST1Brii, ST1Bzri, ST1Bzii>;
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defm : TRATMSTm<atomic_store_16, i32, ST2Brri, ST2Brii, ST2Bzri, ST2Bzii>;
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defm : TRATMSTm<atomic_store_32, i32, STLrri, STLrii, STLzri, STLzii>;
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defm : TRATMSTm<atomic_store_8, ST1Brri, ST1Brii, ST1Bzri, ST1Bzii>;
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defm : TRATMSTm<atomic_store_16, ST2Brri, ST2Brii, ST2Bzri, ST2Bzii>;
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defm : TRATMSTm<atomic_store_32, STLrri, STLrii, STLzri, STLzii>;
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// Atomic swaps
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def : Pat<(i32 (ts1am i64:$src, i32:$flag, i32:$new)),
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@ -20,8 +20,7 @@ include "VVPInstrInfo.td"
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multiclass VectorBinaryArith<
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SDPatternOperator OpNode,
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ValueType ScalarVT, ValueType DataVT, ValueType MaskVT,
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string OpBaseName,
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SDPatternOperator ImmOp, SDNodeXForm ImmCast> {
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string OpBaseName> {
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// No mask.
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def : Pat<(OpNode
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(any_broadcast ScalarVT:$sx),
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@ -56,10 +55,10 @@ multiclass VectorBinaryArith_ShortLong<
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ValueType ShortScalarVT, ValueType ShortDataVT, string ShortOpBaseName> {
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defm : VectorBinaryArith<OpNode,
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LongScalarVT, LongDataVT, v256i1,
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LongOpBaseName, simm7, LO7>;
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LongOpBaseName>;
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defm : VectorBinaryArith<OpNode,
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ShortScalarVT, ShortDataVT, v256i1,
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ShortOpBaseName, simm7, LO7>;
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ShortOpBaseName>;
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}
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