[Test][PhaseOrdering] Precommit test for PR52289
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llvm/test/Transforms/PhaseOrdering/X86/pr52289.ll
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54
llvm/test/Transforms/PhaseOrdering/X86/pr52289.ll
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt -O3 -S < %s | FileCheck %s
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target datalayout = "n8:16:32:64"
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define i32 @main(i32 %a) {
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; CHECK-LABEL: @main(
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; CHECK-NEXT: if.end:
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; CHECK-NEXT: [[TMP0:%.*]] = trunc i32 [[A:%.*]] to i8
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; CHECK-NEXT: [[TMP1:%.*]] = add i8 [[TMP0]], 1
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; CHECK-NEXT: [[CONV:%.*]] = and i8 [[TMP1]], 8
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; CHECK-NEXT: [[CMP_I_NOT:%.*]] = icmp eq i8 [[CONV]], 0
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; CHECK-NEXT: [[SHL_I:%.*]] = select i1 [[CMP_I_NOT]], i8 7, i8 0
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; CHECK-NEXT: [[COND_I:%.*]] = shl i8 [[CONV]], [[SHL_I]]
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; CHECK-NEXT: [[CONV1:%.*]] = sext i8 [[COND_I]] to i32
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; CHECK-NEXT: [[SEXT:%.*]] = mul i32 [[CONV1]], 1355350016
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; CHECK-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[SEXT]], 65536
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; CHECK-NEXT: tail call void @llvm.assume(i1 [[TOBOOL]])
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; CHECK-NEXT: ret i32 0
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;
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%inc = add nsw i32 %a, 1
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%and = and i32 %inc, 8
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%conv = trunc i32 %and to i8
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%call = call fastcc i8 @a(i8 %conv, i32 7)
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%conv1 = sext i8 %call to i64
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%call2 = call fastcc i64 @d(i64 %conv1)
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%mul = mul nsw i64 %call2, 20681
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%conv3 = trunc i64 %mul to i16
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%conv4 = sext i16 %conv3 to i32
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%xor = xor i32 %conv4, 1
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%tobool = icmp ne i32 %xor, 0
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br i1 %tobool, label %if.end, label %if.then
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if.then:
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call void undef()
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br label %if.end
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if.end:
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%call5 = call fastcc i8 @a(i8 0, i32 0)
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ret i32 0
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}
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define internal fastcc i8 @a(i8 %h, i32 %i) {
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%t0 = zext i8 %h to i32
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%cmp = icmp sgt i32 %t0, %i
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%shl = shl i32 %t0, %i
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%cond = select i1 %cmp, i32 %t0, i32 %shl
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%conv4 = trunc i32 %cond to i8
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ret i8 %conv4
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}
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define internal fastcc i64 @d(i64 %h) {
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ret i64 %h
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}
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