[ARM] Addition SSAT/USAT tests for min/max patterns. NFC
This commit is contained in:
David Green
parent
52577cd26f
commit
4d5b020d6e
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@ -121,3 +121,139 @@ while.body: ; preds = %while.body.prol.loo
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while.end: ; preds = %while.body, %while.body.prol.loopexit, %entry
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ret void
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}
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define void @ssat_unroll_minmax(i16* nocapture readonly %pSrcA, i16* nocapture readonly %pSrcB, i16* nocapture writeonly %pDst, i32 %blockSize) {
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; CHECK-LABEL: ssat_unroll_minmax:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: .save {r4, r5, r11, lr}
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; CHECK-NEXT: push {r4, r5, r11, lr}
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; CHECK-NEXT: cmp r3, #0
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; CHECK-NEXT: beq .LBB1_6
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; CHECK-NEXT: @ %bb.1: @ %while.body.preheader
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; CHECK-NEXT: movw r12, #32768
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; CHECK-NEXT: sub lr, r3, #1
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; CHECK-NEXT: tst r3, #1
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; CHECK-NEXT: movt r12, #65535
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; CHECK-NEXT: beq .LBB1_3
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; CHECK-NEXT: @ %bb.2: @ %while.body.prol.preheader
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; CHECK-NEXT: ldrsh r3, [r0], #2
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; CHECK-NEXT: ldrsh r4, [r1], #2
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; CHECK-NEXT: smulbb r3, r4, r3
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; CHECK-NEXT: asr r4, r3, #14
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; CHECK-NEXT: cmn r4, #32768
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; CHECK-NEXT: mov r4, r12
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; CHECK-NEXT: asrgt r4, r3, #14
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; CHECK-NEXT: movw r3, #32767
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; CHECK-NEXT: cmp r4, r3
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; CHECK-NEXT: movge r4, r3
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; CHECK-NEXT: mov r3, lr
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; CHECK-NEXT: strh r4, [r2], #2
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; CHECK-NEXT: .LBB1_3: @ %while.body.prol.loopexit
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; CHECK-NEXT: cmp lr, #0
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; CHECK-NEXT: beq .LBB1_6
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; CHECK-NEXT: @ %bb.4: @ %while.body.preheader1
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; CHECK-NEXT: movw lr, #32767
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; CHECK-NEXT: .LBB1_5: @ %while.body
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; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: ldrsh r4, [r0]
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; CHECK-NEXT: ldrsh r5, [r1]
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; CHECK-NEXT: smulbb r4, r5, r4
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; CHECK-NEXT: asr r5, r4, #14
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; CHECK-NEXT: cmn r5, #32768
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; CHECK-NEXT: mov r5, r12
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; CHECK-NEXT: asrgt r5, r4, #14
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; CHECK-NEXT: cmp r5, lr
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; CHECK-NEXT: movge r5, lr
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; CHECK-NEXT: strh r5, [r2]
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; CHECK-NEXT: ldrsh r4, [r0, #2]
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; CHECK-NEXT: add r0, r0, #4
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; CHECK-NEXT: ldrsh r5, [r1, #2]
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; CHECK-NEXT: add r1, r1, #4
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; CHECK-NEXT: smulbb r4, r5, r4
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; CHECK-NEXT: asr r5, r4, #14
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; CHECK-NEXT: cmn r5, #32768
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; CHECK-NEXT: mov r5, r12
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; CHECK-NEXT: asrgt r5, r4, #14
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; CHECK-NEXT: cmp r5, lr
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; CHECK-NEXT: movge r5, lr
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; CHECK-NEXT: subs r3, r3, #2
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; CHECK-NEXT: strh r5, [r2, #2]
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; CHECK-NEXT: add r2, r2, #4
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; CHECK-NEXT: bne .LBB1_5
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; CHECK-NEXT: .LBB1_6: @ %while.end
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; CHECK-NEXT: pop {r4, r5, r11, pc}
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entry:
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%cmp.not7 = icmp eq i32 %blockSize, 0
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br i1 %cmp.not7, label %while.end, label %while.body.preheader
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while.body.preheader: ; preds = %entry
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%0 = add i32 %blockSize, -1
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%xtraiter = and i32 %blockSize, 1
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%lcmp.mod.not = icmp eq i32 %xtraiter, 0
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br i1 %lcmp.mod.not, label %while.body.prol.loopexit, label %while.body.prol.preheader
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while.body.prol.preheader: ; preds = %while.body.preheader
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%incdec.ptr.prol = getelementptr inbounds i16, i16* %pSrcA, i64 1
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%1 = load i16, i16* %pSrcA, align 2
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%conv.prol = sext i16 %1 to i32
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%incdec.ptr1.prol = getelementptr inbounds i16, i16* %pSrcB, i64 1
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%2 = load i16, i16* %pSrcB, align 2
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%conv2.prol = sext i16 %2 to i32
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%mul.prol = mul nsw i32 %conv2.prol, %conv.prol
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%shr.prol = ashr i32 %mul.prol, 14
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%3 = call i32 @llvm.smax.i32(i32 %shr.prol, i32 -32768)
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%4 = call i32 @llvm.smin.i32(i32 %3, i32 32767)
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%conv3.prol = trunc i32 %4 to i16
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%incdec.ptr4.prol = getelementptr inbounds i16, i16* %pDst, i64 1
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store i16 %conv3.prol, i16* %pDst, align 2
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br label %while.body.prol.loopexit
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while.body.prol.loopexit: ; preds = %while.body.prol.preheader, %while.body.preheader
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%blkCnt.011.unr = phi i32 [ %blockSize, %while.body.preheader ], [ %0, %while.body.prol.preheader ]
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%pSrcA.addr.010.unr = phi i16* [ %pSrcA, %while.body.preheader ], [ %incdec.ptr.prol, %while.body.prol.preheader ]
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%pDst.addr.09.unr = phi i16* [ %pDst, %while.body.preheader ], [ %incdec.ptr4.prol, %while.body.prol.preheader ]
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%pSrcB.addr.08.unr = phi i16* [ %pSrcB, %while.body.preheader ], [ %incdec.ptr1.prol, %while.body.prol.preheader ]
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%5 = icmp eq i32 %0, 0
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br i1 %5, label %while.end, label %while.body
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while.body: ; preds = %while.body.prol.loopexit, %while.body
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%blkCnt.011 = phi i32 [ %dec.1, %while.body ], [ %blkCnt.011.unr, %while.body.prol.loopexit ]
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%pSrcA.addr.010 = phi i16* [ %incdec.ptr.1, %while.body ], [ %pSrcA.addr.010.unr, %while.body.prol.loopexit ]
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%pDst.addr.09 = phi i16* [ %incdec.ptr4.1, %while.body ], [ %pDst.addr.09.unr, %while.body.prol.loopexit ]
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%pSrcB.addr.08 = phi i16* [ %incdec.ptr1.1, %while.body ], [ %pSrcB.addr.08.unr, %while.body.prol.loopexit ]
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%incdec.ptr = getelementptr inbounds i16, i16* %pSrcA.addr.010, i64 1
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%6 = load i16, i16* %pSrcA.addr.010, align 2
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%conv = sext i16 %6 to i32
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%incdec.ptr1 = getelementptr inbounds i16, i16* %pSrcB.addr.08, i64 1
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%7 = load i16, i16* %pSrcB.addr.08, align 2
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%conv2 = sext i16 %7 to i32
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%mul = mul nsw i32 %conv2, %conv
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%shr = ashr i32 %mul, 14
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%8 = call i32 @llvm.smax.i32(i32 %shr, i32 -32768)
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%9 = call i32 @llvm.smin.i32(i32 %8, i32 32767)
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%conv3 = trunc i32 %9 to i16
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%incdec.ptr4 = getelementptr inbounds i16, i16* %pDst.addr.09, i64 1
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store i16 %conv3, i16* %pDst.addr.09, align 2
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%incdec.ptr.1 = getelementptr inbounds i16, i16* %pSrcA.addr.010, i64 2
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%10 = load i16, i16* %incdec.ptr, align 2
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%conv.1 = sext i16 %10 to i32
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%incdec.ptr1.1 = getelementptr inbounds i16, i16* %pSrcB.addr.08, i64 2
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%11 = load i16, i16* %incdec.ptr1, align 2
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%conv2.1 = sext i16 %11 to i32
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%mul.1 = mul nsw i32 %conv2.1, %conv.1
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%shr.1 = ashr i32 %mul.1, 14
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%12 = call i32 @llvm.smax.i32(i32 %shr.1, i32 -32768)
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%13 = call i32 @llvm.smin.i32(i32 %12, i32 32767)
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%conv3.1 = trunc i32 %13 to i16
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%incdec.ptr4.1 = getelementptr inbounds i16, i16* %pDst.addr.09, i64 2
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store i16 %conv3.1, i16* %incdec.ptr4, align 2
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%dec.1 = add i32 %blkCnt.011, -2
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%cmp.not.1 = icmp eq i32 %dec.1, 0
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br i1 %cmp.not.1, label %while.end, label %while.body
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while.end: ; preds = %while.body, %while.body.prol.loopexit, %entry
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ret void
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}
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declare i32 @llvm.smax.i32(i32, i32) #1
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declare i32 @llvm.smin.i32(i32, i32) #1
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@ -649,3 +649,339 @@ define i32 @formulated_invalid(i32 %a) {
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%r = and i32 %s2, 16777215
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ret i32 %r
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}
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define i32 @mm_sat_base_32bit(i32 %x) {
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; V4T-LABEL: mm_sat_base_32bit:
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; V4T: @ %bb.0: @ %entry
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; V4T-NEXT: ldr r1, .LCPI18_0
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; V4T-NEXT: cmp r0, r1
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; V4T-NEXT: movge r0, r1
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; V4T-NEXT: mov r1, #1065353216
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; V4T-NEXT: orr r1, r1, #-1073741824
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; V4T-NEXT: cmn r0, #8388608
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; V4T-NEXT: movle r0, r1
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; V4T-NEXT: bx lr
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; V4T-NEXT: .p2align 2
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; V4T-NEXT: @ %bb.1:
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; V4T-NEXT: .LCPI18_0:
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; V4T-NEXT: .long 8388607 @ 0x7fffff
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;
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; V6T2-LABEL: mm_sat_base_32bit:
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; V6T2: @ %bb.0: @ %entry
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; V6T2-NEXT: movw r1, #65535
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; V6T2-NEXT: movt r1, #127
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; V6T2-NEXT: cmp r0, r1
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; V6T2-NEXT: movge r0, r1
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; V6T2-NEXT: movw r1, #0
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; V6T2-NEXT: movt r1, #65408
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; V6T2-NEXT: cmn r0, #8388608
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; V6T2-NEXT: movle r0, r1
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; V6T2-NEXT: bx lr
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entry:
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%0 = call i32 @llvm.smin.i32(i32 %x, i32 8388607)
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%1 = call i32 @llvm.smax.i32(i32 %0, i32 -8388608)
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ret i32 %1
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}
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define i16 @mm_sat_base_16bit(i16 %x) {
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; V4T-LABEL: mm_sat_base_16bit:
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; V4T: @ %bb.0: @ %entry
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; V4T-NEXT: mov r2, #255
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; V4T-NEXT: lsl r0, r0, #16
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; V4T-NEXT: orr r2, r2, #1792
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; V4T-NEXT: asr r1, r0, #16
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; V4T-NEXT: cmp r1, r2
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; V4T-NEXT: asrlt r2, r0, #16
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; V4T-NEXT: ldr r0, .LCPI19_0
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; V4T-NEXT: cmn r2, #2048
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; V4T-NEXT: movgt r0, r2
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; V4T-NEXT: bx lr
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; V4T-NEXT: .p2align 2
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; V4T-NEXT: @ %bb.1:
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; V4T-NEXT: .LCPI19_0:
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; V4T-NEXT: .long 4294965248 @ 0xfffff800
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;
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; V6T2-LABEL: mm_sat_base_16bit:
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; V6T2: @ %bb.0: @ %entry
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; V6T2-NEXT: sxth r0, r0
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; V6T2-NEXT: movw r1, #2047
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; V6T2-NEXT: cmp r0, r1
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; V6T2-NEXT: movlt r1, r0
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; V6T2-NEXT: movw r0, #63488
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; V6T2-NEXT: movt r0, #65535
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; V6T2-NEXT: cmn r1, #2048
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; V6T2-NEXT: movgt r0, r1
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; V6T2-NEXT: bx lr
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entry:
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%0 = call i16 @llvm.smin.i16(i16 %x, i16 2047)
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%1 = call i16 @llvm.smax.i16(i16 %0, i16 -2048)
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ret i16 %1
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}
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define i8 @mm_sat_base_8bit(i8 %x) {
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; V4T-LABEL: mm_sat_base_8bit:
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; V4T: @ %bb.0: @ %entry
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; V4T-NEXT: lsl r1, r0, #24
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; V4T-NEXT: mov r0, #31
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; V4T-NEXT: asr r2, r1, #24
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; V4T-NEXT: cmp r2, #31
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; V4T-NEXT: asrlt r0, r1, #24
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; V4T-NEXT: cmn r0, #32
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; V4T-NEXT: mvnle r0, #31
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; V4T-NEXT: bx lr
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;
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; V6T2-LABEL: mm_sat_base_8bit:
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; V6T2: @ %bb.0: @ %entry
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; V6T2-NEXT: sxtb r0, r0
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; V6T2-NEXT: cmp r0, #31
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; V6T2-NEXT: movge r0, #31
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; V6T2-NEXT: cmn r0, #32
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; V6T2-NEXT: mvnle r0, #31
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; V6T2-NEXT: bx lr
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entry:
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%0 = call i8 @llvm.smin.i8(i8 %x, i8 31)
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%1 = call i8 @llvm.smax.i8(i8 %0, i8 -32)
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ret i8 %1
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}
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define i32 @mm_sat_lower_upper_1(i32 %x) {
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; V4T-LABEL: mm_sat_lower_upper_1:
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; V4T: @ %bb.0: @ %entry
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; V4T-NEXT: ldr r1, .LCPI21_0
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; V4T-NEXT: cmp r0, r1
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; V4T-NEXT: movge r0, r1
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; V4T-NEXT: mov r1, #1065353216
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; V4T-NEXT: orr r1, r1, #-1073741824
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; V4T-NEXT: cmn r0, #8388608
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; V4T-NEXT: movle r0, r1
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; V4T-NEXT: bx lr
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; V4T-NEXT: .p2align 2
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; V4T-NEXT: @ %bb.1:
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; V4T-NEXT: .LCPI21_0:
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; V4T-NEXT: .long 8388607 @ 0x7fffff
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;
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; V6T2-LABEL: mm_sat_lower_upper_1:
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; V6T2: @ %bb.0: @ %entry
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; V6T2-NEXT: movw r1, #65535
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; V6T2-NEXT: movt r1, #127
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; V6T2-NEXT: cmp r0, r1
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; V6T2-NEXT: movge r0, r1
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; V6T2-NEXT: movw r1, #0
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; V6T2-NEXT: movt r1, #65408
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; V6T2-NEXT: cmn r0, #8388608
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; V6T2-NEXT: movle r0, r1
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; V6T2-NEXT: bx lr
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entry:
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%0 = call i32 @llvm.smin.i32(i32 %x, i32 8388607)
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%1 = call i32 @llvm.smax.i32(i32 %0, i32 -8388608)
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ret i32 %1
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}
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define i32 @mm_sat_lower_upper_2(i32 %x) {
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; V4T-LABEL: mm_sat_lower_upper_2:
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; V4T: @ %bb.0: @ %entry
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; V4T-NEXT: ldr r1, .LCPI22_0
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; V4T-NEXT: cmp r0, r1
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; V4T-NEXT: movge r0, r1
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; V4T-NEXT: mov r1, #1065353216
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; V4T-NEXT: orr r1, r1, #-1073741824
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; V4T-NEXT: cmn r0, #8388608
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; V4T-NEXT: movle r0, r1
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; V4T-NEXT: bx lr
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; V4T-NEXT: .p2align 2
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; V4T-NEXT: @ %bb.1:
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; V4T-NEXT: .LCPI22_0:
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; V4T-NEXT: .long 8388607 @ 0x7fffff
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;
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; V6T2-LABEL: mm_sat_lower_upper_2:
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; V6T2: @ %bb.0: @ %entry
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; V6T2-NEXT: movw r1, #65535
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; V6T2-NEXT: movt r1, #127
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; V6T2-NEXT: cmp r0, r1
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; V6T2-NEXT: movge r0, r1
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; V6T2-NEXT: movw r1, #0
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; V6T2-NEXT: movt r1, #65408
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; V6T2-NEXT: cmn r0, #8388608
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; V6T2-NEXT: movle r0, r1
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; V6T2-NEXT: bx lr
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entry:
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%0 = call i32 @llvm.smin.i32(i32 %x, i32 8388607)
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%1 = call i32 @llvm.smax.i32(i32 %0, i32 -8388608)
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ret i32 %1
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}
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define i32 @mm_sat_upper_lower_1(i32 %x) {
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; V4T-LABEL: mm_sat_upper_lower_1:
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; V4T: @ %bb.0: @ %entry
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; V4T-NEXT: mov r1, #1065353216
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; V4T-NEXT: cmn r0, #8388608
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; V4T-NEXT: orr r1, r1, #-1073741824
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; V4T-NEXT: movle r0, r1
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; V4T-NEXT: ldr r1, .LCPI23_0
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; V4T-NEXT: cmp r0, r1
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; V4T-NEXT: movge r0, r1
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; V4T-NEXT: bx lr
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; V4T-NEXT: .p2align 2
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; V4T-NEXT: @ %bb.1:
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; V4T-NEXT: .LCPI23_0:
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; V4T-NEXT: .long 8388607 @ 0x7fffff
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;
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; V6T2-LABEL: mm_sat_upper_lower_1:
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; V6T2: @ %bb.0: @ %entry
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; V6T2-NEXT: movw r1, #0
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; V6T2-NEXT: cmn r0, #8388608
|
||||
; V6T2-NEXT: movt r1, #65408
|
||||
; V6T2-NEXT: movle r0, r1
|
||||
; V6T2-NEXT: movw r1, #65535
|
||||
; V6T2-NEXT: movt r1, #127
|
||||
; V6T2-NEXT: cmp r0, r1
|
||||
; V6T2-NEXT: movge r0, r1
|
||||
; V6T2-NEXT: bx lr
|
||||
entry:
|
||||
%0 = call i32 @llvm.smax.i32(i32 %x, i32 -8388608)
|
||||
%1 = call i32 @llvm.smin.i32(i32 %0, i32 8388607)
|
||||
ret i32 %1
|
||||
}
|
||||
|
||||
define i32 @mm_sat_upper_lower_2(i32 %x) {
|
||||
; V4T-LABEL: mm_sat_upper_lower_2:
|
||||
; V4T: @ %bb.0: @ %entry
|
||||
; V4T-NEXT: mov r1, #1065353216
|
||||
; V4T-NEXT: cmn r0, #8388608
|
||||
; V4T-NEXT: orr r1, r1, #-1073741824
|
||||
; V4T-NEXT: movle r0, r1
|
||||
; V4T-NEXT: ldr r1, .LCPI24_0
|
||||
; V4T-NEXT: cmp r0, r1
|
||||
; V4T-NEXT: movge r0, r1
|
||||
; V4T-NEXT: bx lr
|
||||
; V4T-NEXT: .p2align 2
|
||||
; V4T-NEXT: @ %bb.1:
|
||||
; V4T-NEXT: .LCPI24_0:
|
||||
; V4T-NEXT: .long 8388607 @ 0x7fffff
|
||||
;
|
||||
; V6T2-LABEL: mm_sat_upper_lower_2:
|
||||
; V6T2: @ %bb.0: @ %entry
|
||||
; V6T2-NEXT: movw r1, #0
|
||||
; V6T2-NEXT: cmn r0, #8388608
|
||||
; V6T2-NEXT: movt r1, #65408
|
||||
; V6T2-NEXT: movle r0, r1
|
||||
; V6T2-NEXT: movw r1, #65535
|
||||
; V6T2-NEXT: movt r1, #127
|
||||
; V6T2-NEXT: cmp r0, r1
|
||||
; V6T2-NEXT: movge r0, r1
|
||||
; V6T2-NEXT: bx lr
|
||||
entry:
|
||||
%0 = call i32 @llvm.smax.i32(i32 %x, i32 -8388608)
|
||||
%1 = call i32 @llvm.smin.i32(i32 %0, i32 8388607)
|
||||
ret i32 %1
|
||||
}
|
||||
|
||||
define i32 @mm_sat_upper_lower_3(i32 %x) {
|
||||
; V4T-LABEL: mm_sat_upper_lower_3:
|
||||
; V4T: @ %bb.0: @ %entry
|
||||
; V4T-NEXT: mov r1, #1065353216
|
||||
; V4T-NEXT: cmn r0, #8388608
|
||||
; V4T-NEXT: orr r1, r1, #-1073741824
|
||||
; V4T-NEXT: movle r0, r1
|
||||
; V4T-NEXT: ldr r1, .LCPI25_0
|
||||
; V4T-NEXT: cmp r0, r1
|
||||
; V4T-NEXT: movge r0, r1
|
||||
; V4T-NEXT: bx lr
|
||||
; V4T-NEXT: .p2align 2
|
||||
; V4T-NEXT: @ %bb.1:
|
||||
; V4T-NEXT: .LCPI25_0:
|
||||
; V4T-NEXT: .long 8388607 @ 0x7fffff
|
||||
;
|
||||
; V6T2-LABEL: mm_sat_upper_lower_3:
|
||||
; V6T2: @ %bb.0: @ %entry
|
||||
; V6T2-NEXT: movw r1, #0
|
||||
; V6T2-NEXT: cmn r0, #8388608
|
||||
; V6T2-NEXT: movt r1, #65408
|
||||
; V6T2-NEXT: movle r0, r1
|
||||
; V6T2-NEXT: movw r1, #65535
|
||||
; V6T2-NEXT: movt r1, #127
|
||||
; V6T2-NEXT: cmp r0, r1
|
||||
; V6T2-NEXT: movge r0, r1
|
||||
; V6T2-NEXT: bx lr
|
||||
entry:
|
||||
%0 = call i32 @llvm.smax.i32(i32 %x, i32 -8388608)
|
||||
%1 = call i32 @llvm.smin.i32(i32 %0, i32 8388607)
|
||||
ret i32 %1
|
||||
}
|
||||
|
||||
define i32 @mm_sat_le_ge(i32 %x) {
|
||||
; V4T-LABEL: mm_sat_le_ge:
|
||||
; V4T: @ %bb.0: @ %entry
|
||||
; V4T-NEXT: mov r1, #1065353216
|
||||
; V4T-NEXT: cmn r0, #8388608
|
||||
; V4T-NEXT: orr r1, r1, #-1073741824
|
||||
; V4T-NEXT: movle r0, r1
|
||||
; V4T-NEXT: ldr r1, .LCPI26_0
|
||||
; V4T-NEXT: cmp r0, r1
|
||||
; V4T-NEXT: movge r0, r1
|
||||
; V4T-NEXT: bx lr
|
||||
; V4T-NEXT: .p2align 2
|
||||
; V4T-NEXT: @ %bb.1:
|
||||
; V4T-NEXT: .LCPI26_0:
|
||||
; V4T-NEXT: .long 8388607 @ 0x7fffff
|
||||
;
|
||||
; V6T2-LABEL: mm_sat_le_ge:
|
||||
; V6T2: @ %bb.0: @ %entry
|
||||
; V6T2-NEXT: movw r1, #0
|
||||
; V6T2-NEXT: cmn r0, #8388608
|
||||
; V6T2-NEXT: movt r1, #65408
|
||||
; V6T2-NEXT: movle r0, r1
|
||||
; V6T2-NEXT: movw r1, #65535
|
||||
; V6T2-NEXT: movt r1, #127
|
||||
; V6T2-NEXT: cmp r0, r1
|
||||
; V6T2-NEXT: movge r0, r1
|
||||
; V6T2-NEXT: bx lr
|
||||
entry:
|
||||
%0 = call i32 @llvm.smax.i32(i32 %x, i32 -8388608)
|
||||
%1 = call i32 @llvm.smin.i32(i32 %0, i32 8388607)
|
||||
ret i32 %1
|
||||
}
|
||||
|
||||
define i32 @mm_no_sat_incorrect_interval(i32 %x) {
|
||||
; V4T-LABEL: mm_no_sat_incorrect_interval:
|
||||
; V4T: @ %bb.0: @ %entry
|
||||
; V4T-NEXT: ldr r1, .LCPI27_0
|
||||
; V4T-NEXT: cmp r0, r1
|
||||
; V4T-NEXT: movle r0, r1
|
||||
; V4T-NEXT: ldr r1, .LCPI27_1
|
||||
; V4T-NEXT: cmp r0, r1
|
||||
; V4T-NEXT: movge r0, r1
|
||||
; V4T-NEXT: bx lr
|
||||
; V4T-NEXT: .p2align 2
|
||||
; V4T-NEXT: @ %bb.1:
|
||||
; V4T-NEXT: .LCPI27_0:
|
||||
; V4T-NEXT: .long 4275878552 @ 0xfedcba98
|
||||
; V4T-NEXT: .LCPI27_1:
|
||||
; V4T-NEXT: .long 8388607 @ 0x7fffff
|
||||
;
|
||||
; V6T2-LABEL: mm_no_sat_incorrect_interval:
|
||||
; V6T2: @ %bb.0: @ %entry
|
||||
; V6T2-NEXT: movw r1, #47768
|
||||
; V6T2-NEXT: movt r1, #65244
|
||||
; V6T2-NEXT: cmp r0, r1
|
||||
; V6T2-NEXT: movle r0, r1
|
||||
; V6T2-NEXT: movw r1, #65535
|
||||
; V6T2-NEXT: movt r1, #127
|
||||
; V6T2-NEXT: cmp r0, r1
|
||||
; V6T2-NEXT: movge r0, r1
|
||||
; V6T2-NEXT: bx lr
|
||||
entry:
|
||||
%0 = call i32 @llvm.smax.i32(i32 %x, i32 -19088744)
|
||||
%1 = call i32 @llvm.smin.i32(i32 %0, i32 8388607)
|
||||
ret i32 %1
|
||||
}
|
||||
|
||||
declare i32 @llvm.smin.i32(i32, i32)
|
||||
declare i32 @llvm.smax.i32(i32, i32)
|
||||
declare i16 @llvm.smin.i16(i16, i16)
|
||||
declare i16 @llvm.smax.i16(i16, i16)
|
||||
declare i8 @llvm.smin.i8(i8, i8)
|
||||
declare i8 @llvm.smax.i8(i8, i8)
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -608,3 +608,427 @@ entry:
|
|||
%saturateUp = select i1 %cmpUp, i32 8388607, i32 %saturateLow
|
||||
ret i32 %saturateUp
|
||||
}
|
||||
|
||||
define i32 @mm_unsigned_sat_base_32bit(i32 %x) {
|
||||
; V4T-LABEL: mm_unsigned_sat_base_32bit:
|
||||
; V4T: @ %bb.0: @ %entry
|
||||
; V4T-NEXT: ldr r1, .LCPI15_0
|
||||
; V4T-NEXT: cmp r0, r1
|
||||
; V4T-NEXT: movlt r1, r0
|
||||
; V4T-NEXT: bic r0, r1, r1, asr #31
|
||||
; V4T-NEXT: bx lr
|
||||
; V4T-NEXT: .p2align 2
|
||||
; V4T-NEXT: @ %bb.1:
|
||||
; V4T-NEXT: .LCPI15_0:
|
||||
; V4T-NEXT: .long 8388607 @ 0x7fffff
|
||||
;
|
||||
; V6-LABEL: mm_unsigned_sat_base_32bit:
|
||||
; V6: @ %bb.0: @ %entry
|
||||
; V6-NEXT: ldr r1, .LCPI15_0
|
||||
; V6-NEXT: cmp r0, r1
|
||||
; V6-NEXT: movlt r1, r0
|
||||
; V6-NEXT: bic r0, r1, r1, asr #31
|
||||
; V6-NEXT: bx lr
|
||||
; V6-NEXT: .p2align 2
|
||||
; V6-NEXT: @ %bb.1:
|
||||
; V6-NEXT: .LCPI15_0:
|
||||
; V6-NEXT: .long 8388607 @ 0x7fffff
|
||||
;
|
||||
; V6T2-LABEL: mm_unsigned_sat_base_32bit:
|
||||
; V6T2: @ %bb.0: @ %entry
|
||||
; V6T2-NEXT: movw r1, #65535
|
||||
; V6T2-NEXT: movt r1, #127
|
||||
; V6T2-NEXT: cmp r0, r1
|
||||
; V6T2-NEXT: movlt r1, r0
|
||||
; V6T2-NEXT: bic r0, r1, r1, asr #31
|
||||
; V6T2-NEXT: bx lr
|
||||
entry:
|
||||
%0 = call i32 @llvm.smin.i32(i32 %x, i32 8388607)
|
||||
%1 = call i32 @llvm.smax.i32(i32 %0, i32 0)
|
||||
ret i32 %1
|
||||
}
|
||||
|
||||
define i16 @mm_unsigned_sat_base_16bit(i16 %x) {
|
||||
; V4T-LABEL: mm_unsigned_sat_base_16bit:
|
||||
; V4T: @ %bb.0: @ %entry
|
||||
; V4T-NEXT: mov r2, #255
|
||||
; V4T-NEXT: lsl r0, r0, #16
|
||||
; V4T-NEXT: orr r2, r2, #1792
|
||||
; V4T-NEXT: asr r1, r0, #16
|
||||
; V4T-NEXT: cmp r1, r2
|
||||
; V4T-NEXT: asrlt r2, r0, #16
|
||||
; V4T-NEXT: bic r0, r2, r2, asr #31
|
||||
; V4T-NEXT: bx lr
|
||||
;
|
||||
; V6-LABEL: mm_unsigned_sat_base_16bit:
|
||||
; V6: @ %bb.0: @ %entry
|
||||
; V6-NEXT: mov r1, #255
|
||||
; V6-NEXT: sxth r0, r0
|
||||
; V6-NEXT: orr r1, r1, #1792
|
||||
; V6-NEXT: cmp r0, r1
|
||||
; V6-NEXT: movlt r1, r0
|
||||
; V6-NEXT: bic r0, r1, r1, asr #31
|
||||
; V6-NEXT: bx lr
|
||||
;
|
||||
; V6T2-LABEL: mm_unsigned_sat_base_16bit:
|
||||
; V6T2: @ %bb.0: @ %entry
|
||||
; V6T2-NEXT: sxth r0, r0
|
||||
; V6T2-NEXT: movw r1, #2047
|
||||
; V6T2-NEXT: cmp r0, r1
|
||||
; V6T2-NEXT: movlt r1, r0
|
||||
; V6T2-NEXT: bic r0, r1, r1, asr #31
|
||||
; V6T2-NEXT: bx lr
|
||||
entry:
|
||||
%0 = call i16 @llvm.smin.i16(i16 %x, i16 2047)
|
||||
%1 = call i16 @llvm.smax.i16(i16 %0, i16 0)
|
||||
ret i16 %1
|
||||
}
|
||||
|
||||
define i8 @mm_unsigned_sat_base_8bit(i8 %x) {
|
||||
; V4T-LABEL: mm_unsigned_sat_base_8bit:
|
||||
; V4T: @ %bb.0: @ %entry
|
||||
; V4T-NEXT: lsl r0, r0, #24
|
||||
; V4T-NEXT: mov r2, #31
|
||||
; V4T-NEXT: asr r1, r0, #24
|
||||
; V4T-NEXT: cmp r1, #31
|
||||
; V4T-NEXT: asrlt r2, r0, #24
|
||||
; V4T-NEXT: bic r0, r2, r2, asr #31
|
||||
; V4T-NEXT: bx lr
|
||||
;
|
||||
; V6-LABEL: mm_unsigned_sat_base_8bit:
|
||||
; V6: @ %bb.0: @ %entry
|
||||
; V6-NEXT: sxtb r0, r0
|
||||
; V6-NEXT: cmp r0, #31
|
||||
; V6-NEXT: movge r0, #31
|
||||
; V6-NEXT: bic r0, r0, r0, asr #31
|
||||
; V6-NEXT: bx lr
|
||||
;
|
||||
; V6T2-LABEL: mm_unsigned_sat_base_8bit:
|
||||
; V6T2: @ %bb.0: @ %entry
|
||||
; V6T2-NEXT: sxtb r0, r0
|
||||
; V6T2-NEXT: cmp r0, #31
|
||||
; V6T2-NEXT: movge r0, #31
|
||||
; V6T2-NEXT: bic r0, r0, r0, asr #31
|
||||
; V6T2-NEXT: bx lr
|
||||
entry:
|
||||
%0 = call i8 @llvm.smin.i8(i8 %x, i8 31)
|
||||
%1 = call i8 @llvm.smax.i8(i8 %0, i8 0)
|
||||
ret i8 %1
|
||||
}
|
||||
|
||||
define i32 @mm_unsigned_sat_lower_upper_1(i32 %x) {
|
||||
; V4T-LABEL: mm_unsigned_sat_lower_upper_1:
|
||||
; V4T: @ %bb.0: @ %entry
|
||||
; V4T-NEXT: ldr r1, .LCPI18_0
|
||||
; V4T-NEXT: cmp r0, r1
|
||||
; V4T-NEXT: movlt r1, r0
|
||||
; V4T-NEXT: bic r0, r1, r1, asr #31
|
||||
; V4T-NEXT: bx lr
|
||||
; V4T-NEXT: .p2align 2
|
||||
; V4T-NEXT: @ %bb.1:
|
||||
; V4T-NEXT: .LCPI18_0:
|
||||
; V4T-NEXT: .long 8388607 @ 0x7fffff
|
||||
;
|
||||
; V6-LABEL: mm_unsigned_sat_lower_upper_1:
|
||||
; V6: @ %bb.0: @ %entry
|
||||
; V6-NEXT: ldr r1, .LCPI18_0
|
||||
; V6-NEXT: cmp r0, r1
|
||||
; V6-NEXT: movlt r1, r0
|
||||
; V6-NEXT: bic r0, r1, r1, asr #31
|
||||
; V6-NEXT: bx lr
|
||||
; V6-NEXT: .p2align 2
|
||||
; V6-NEXT: @ %bb.1:
|
||||
; V6-NEXT: .LCPI18_0:
|
||||
; V6-NEXT: .long 8388607 @ 0x7fffff
|
||||
;
|
||||
; V6T2-LABEL: mm_unsigned_sat_lower_upper_1:
|
||||
; V6T2: @ %bb.0: @ %entry
|
||||
; V6T2-NEXT: movw r1, #65535
|
||||
; V6T2-NEXT: movt r1, #127
|
||||
; V6T2-NEXT: cmp r0, r1
|
||||
; V6T2-NEXT: movlt r1, r0
|
||||
; V6T2-NEXT: bic r0, r1, r1, asr #31
|
||||
; V6T2-NEXT: bx lr
|
||||
entry:
|
||||
%0 = call i32 @llvm.smin.i32(i32 %x, i32 8388607)
|
||||
%1 = call i32 @llvm.smax.i32(i32 %0, i32 0)
|
||||
ret i32 %1
|
||||
}
|
||||
|
||||
define i32 @mm_unsigned_sat_lower_upper_2(i32 %x) {
|
||||
; V4T-LABEL: mm_unsigned_sat_lower_upper_2:
|
||||
; V4T: @ %bb.0: @ %entry
|
||||
; V4T-NEXT: ldr r1, .LCPI19_0
|
||||
; V4T-NEXT: cmp r0, r1
|
||||
; V4T-NEXT: movlt r1, r0
|
||||
; V4T-NEXT: bic r0, r1, r1, asr #31
|
||||
; V4T-NEXT: bx lr
|
||||
; V4T-NEXT: .p2align 2
|
||||
; V4T-NEXT: @ %bb.1:
|
||||
; V4T-NEXT: .LCPI19_0:
|
||||
; V4T-NEXT: .long 8388607 @ 0x7fffff
|
||||
;
|
||||
; V6-LABEL: mm_unsigned_sat_lower_upper_2:
|
||||
; V6: @ %bb.0: @ %entry
|
||||
; V6-NEXT: ldr r1, .LCPI19_0
|
||||
; V6-NEXT: cmp r0, r1
|
||||
; V6-NEXT: movlt r1, r0
|
||||
; V6-NEXT: bic r0, r1, r1, asr #31
|
||||
; V6-NEXT: bx lr
|
||||
; V6-NEXT: .p2align 2
|
||||
; V6-NEXT: @ %bb.1:
|
||||
; V6-NEXT: .LCPI19_0:
|
||||
; V6-NEXT: .long 8388607 @ 0x7fffff
|
||||
;
|
||||
; V6T2-LABEL: mm_unsigned_sat_lower_upper_2:
|
||||
; V6T2: @ %bb.0: @ %entry
|
||||
; V6T2-NEXT: movw r1, #65535
|
||||
; V6T2-NEXT: movt r1, #127
|
||||
; V6T2-NEXT: cmp r0, r1
|
||||
; V6T2-NEXT: movlt r1, r0
|
||||
; V6T2-NEXT: bic r0, r1, r1, asr #31
|
||||
; V6T2-NEXT: bx lr
|
||||
entry:
|
||||
%0 = call i32 @llvm.smin.i32(i32 %x, i32 8388607)
|
||||
%1 = call i32 @llvm.smax.i32(i32 %0, i32 0)
|
||||
ret i32 %1
|
||||
}
|
||||
|
||||
define i32 @mm_unsigned_sat_upper_lower_1(i32 %x) {
|
||||
; V4T-LABEL: mm_unsigned_sat_upper_lower_1:
|
||||
; V4T: @ %bb.0: @ %entry
|
||||
; V4T-NEXT: bic r1, r0, r0, asr #31
|
||||
; V4T-NEXT: ldr r0, .LCPI20_0
|
||||
; V4T-NEXT: cmp r1, r0
|
||||
; V4T-NEXT: movlo r0, r1
|
||||
; V4T-NEXT: bx lr
|
||||
; V4T-NEXT: .p2align 2
|
||||
; V4T-NEXT: @ %bb.1:
|
||||
; V4T-NEXT: .LCPI20_0:
|
||||
; V4T-NEXT: .long 8388607 @ 0x7fffff
|
||||
;
|
||||
; V6-LABEL: mm_unsigned_sat_upper_lower_1:
|
||||
; V6: @ %bb.0: @ %entry
|
||||
; V6-NEXT: bic r1, r0, r0, asr #31
|
||||
; V6-NEXT: ldr r0, .LCPI20_0
|
||||
; V6-NEXT: cmp r1, r0
|
||||
; V6-NEXT: movlo r0, r1
|
||||
; V6-NEXT: bx lr
|
||||
; V6-NEXT: .p2align 2
|
||||
; V6-NEXT: @ %bb.1:
|
||||
; V6-NEXT: .LCPI20_0:
|
||||
; V6-NEXT: .long 8388607 @ 0x7fffff
|
||||
;
|
||||
; V6T2-LABEL: mm_unsigned_sat_upper_lower_1:
|
||||
; V6T2: @ %bb.0: @ %entry
|
||||
; V6T2-NEXT: bic r1, r0, r0, asr #31
|
||||
; V6T2-NEXT: movw r0, #65535
|
||||
; V6T2-NEXT: movt r0, #127
|
||||
; V6T2-NEXT: cmp r1, r0
|
||||
; V6T2-NEXT: movlo r0, r1
|
||||
; V6T2-NEXT: bx lr
|
||||
entry:
|
||||
%0 = call i32 @llvm.smax.i32(i32 %x, i32 0)
|
||||
%1 = call i32 @llvm.umin.i32(i32 %0, i32 8388607)
|
||||
ret i32 %1
|
||||
}
|
||||
|
||||
define i32 @mm_unsigned_sat_upper_lower_2(i32 %x) {
|
||||
; V4T-LABEL: mm_unsigned_sat_upper_lower_2:
|
||||
; V4T: @ %bb.0: @ %entry
|
||||
; V4T-NEXT: bic r1, r0, r0, asr #31
|
||||
; V4T-NEXT: ldr r0, .LCPI21_0
|
||||
; V4T-NEXT: cmp r1, r0
|
||||
; V4T-NEXT: movlo r0, r1
|
||||
; V4T-NEXT: bx lr
|
||||
; V4T-NEXT: .p2align 2
|
||||
; V4T-NEXT: @ %bb.1:
|
||||
; V4T-NEXT: .LCPI21_0:
|
||||
; V4T-NEXT: .long 8388607 @ 0x7fffff
|
||||
;
|
||||
; V6-LABEL: mm_unsigned_sat_upper_lower_2:
|
||||
; V6: @ %bb.0: @ %entry
|
||||
; V6-NEXT: bic r1, r0, r0, asr #31
|
||||
; V6-NEXT: ldr r0, .LCPI21_0
|
||||
; V6-NEXT: cmp r1, r0
|
||||
; V6-NEXT: movlo r0, r1
|
||||
; V6-NEXT: bx lr
|
||||
; V6-NEXT: .p2align 2
|
||||
; V6-NEXT: @ %bb.1:
|
||||
; V6-NEXT: .LCPI21_0:
|
||||
; V6-NEXT: .long 8388607 @ 0x7fffff
|
||||
;
|
||||
; V6T2-LABEL: mm_unsigned_sat_upper_lower_2:
|
||||
; V6T2: @ %bb.0: @ %entry
|
||||
; V6T2-NEXT: bic r1, r0, r0, asr #31
|
||||
; V6T2-NEXT: movw r0, #65535
|
||||
; V6T2-NEXT: movt r0, #127
|
||||
; V6T2-NEXT: cmp r1, r0
|
||||
; V6T2-NEXT: movlo r0, r1
|
||||
; V6T2-NEXT: bx lr
|
||||
entry:
|
||||
%0 = call i32 @llvm.smax.i32(i32 %x, i32 0)
|
||||
%1 = call i32 @llvm.umin.i32(i32 %0, i32 8388607)
|
||||
ret i32 %1
|
||||
}
|
||||
|
||||
define i32 @mm_unsigned_sat_upper_lower_3(i32 %x) {
|
||||
; V4T-LABEL: mm_unsigned_sat_upper_lower_3:
|
||||
; V4T: @ %bb.0: @ %entry
|
||||
; V4T-NEXT: bic r1, r0, r0, asr #31
|
||||
; V4T-NEXT: ldr r0, .LCPI22_0
|
||||
; V4T-NEXT: cmp r1, r0
|
||||
; V4T-NEXT: movlo r0, r1
|
||||
; V4T-NEXT: bx lr
|
||||
; V4T-NEXT: .p2align 2
|
||||
; V4T-NEXT: @ %bb.1:
|
||||
; V4T-NEXT: .LCPI22_0:
|
||||
; V4T-NEXT: .long 8388607 @ 0x7fffff
|
||||
;
|
||||
; V6-LABEL: mm_unsigned_sat_upper_lower_3:
|
||||
; V6: @ %bb.0: @ %entry
|
||||
; V6-NEXT: bic r1, r0, r0, asr #31
|
||||
; V6-NEXT: ldr r0, .LCPI22_0
|
||||
; V6-NEXT: cmp r1, r0
|
||||
; V6-NEXT: movlo r0, r1
|
||||
; V6-NEXT: bx lr
|
||||
; V6-NEXT: .p2align 2
|
||||
; V6-NEXT: @ %bb.1:
|
||||
; V6-NEXT: .LCPI22_0:
|
||||
; V6-NEXT: .long 8388607 @ 0x7fffff
|
||||
;
|
||||
; V6T2-LABEL: mm_unsigned_sat_upper_lower_3:
|
||||
; V6T2: @ %bb.0: @ %entry
|
||||
; V6T2-NEXT: bic r1, r0, r0, asr #31
|
||||
; V6T2-NEXT: movw r0, #65535
|
||||
; V6T2-NEXT: movt r0, #127
|
||||
; V6T2-NEXT: cmp r1, r0
|
||||
; V6T2-NEXT: movlo r0, r1
|
||||
; V6T2-NEXT: bx lr
|
||||
entry:
|
||||
%0 = call i32 @llvm.smax.i32(i32 %x, i32 0)
|
||||
%1 = call i32 @llvm.umin.i32(i32 %0, i32 8388607)
|
||||
ret i32 %1
|
||||
}
|
||||
|
||||
define i32 @mm_no_unsigned_sat_incorrect_constant(i32 %x) {
|
||||
; V4T-LABEL: mm_no_unsigned_sat_incorrect_constant:
|
||||
; V4T: @ %bb.0: @ %entry
|
||||
; V4T-NEXT: orr r1, r0, r0, asr #31
|
||||
; V4T-NEXT: ldr r0, .LCPI23_0
|
||||
; V4T-NEXT: cmp r1, r0
|
||||
; V4T-NEXT: movlt r0, r1
|
||||
; V4T-NEXT: bx lr
|
||||
; V4T-NEXT: .p2align 2
|
||||
; V4T-NEXT: @ %bb.1:
|
||||
; V4T-NEXT: .LCPI23_0:
|
||||
; V4T-NEXT: .long 8388607 @ 0x7fffff
|
||||
;
|
||||
; V6-LABEL: mm_no_unsigned_sat_incorrect_constant:
|
||||
; V6: @ %bb.0: @ %entry
|
||||
; V6-NEXT: orr r1, r0, r0, asr #31
|
||||
; V6-NEXT: ldr r0, .LCPI23_0
|
||||
; V6-NEXT: cmp r1, r0
|
||||
; V6-NEXT: movlt r0, r1
|
||||
; V6-NEXT: bx lr
|
||||
; V6-NEXT: .p2align 2
|
||||
; V6-NEXT: @ %bb.1:
|
||||
; V6-NEXT: .LCPI23_0:
|
||||
; V6-NEXT: .long 8388607 @ 0x7fffff
|
||||
;
|
||||
; V6T2-LABEL: mm_no_unsigned_sat_incorrect_constant:
|
||||
; V6T2: @ %bb.0: @ %entry
|
||||
; V6T2-NEXT: orr r1, r0, r0, asr #31
|
||||
; V6T2-NEXT: movw r0, #65535
|
||||
; V6T2-NEXT: movt r0, #127
|
||||
; V6T2-NEXT: cmp r1, r0
|
||||
; V6T2-NEXT: movlt r0, r1
|
||||
; V6T2-NEXT: bx lr
|
||||
entry:
|
||||
%0 = call i32 @llvm.smax.i32(i32 %x, i32 -1)
|
||||
%1 = call i32 @llvm.smin.i32(i32 %0, i32 8388607)
|
||||
ret i32 %1
|
||||
}
|
||||
|
||||
define i32 @mm_no_unsigned_sat_incorrect_constant2(i32 %x) {
|
||||
; V4T-LABEL: mm_no_unsigned_sat_incorrect_constant2:
|
||||
; V4T: @ %bb.0: @ %entry
|
||||
; V4T-NEXT: bic r1, r0, r0, asr #31
|
||||
; V4T-NEXT: mov r0, #1
|
||||
; V4T-NEXT: orr r0, r0, #8388608
|
||||
; V4T-NEXT: cmp r1, #8388608
|
||||
; V4T-NEXT: movls r0, r1
|
||||
; V4T-NEXT: bx lr
|
||||
;
|
||||
; V6-LABEL: mm_no_unsigned_sat_incorrect_constant2:
|
||||
; V6: @ %bb.0: @ %entry
|
||||
; V6-NEXT: bic r1, r0, r0, asr #31
|
||||
; V6-NEXT: mov r0, #1
|
||||
; V6-NEXT: orr r0, r0, #8388608
|
||||
; V6-NEXT: cmp r1, #8388608
|
||||
; V6-NEXT: movls r0, r1
|
||||
; V6-NEXT: bx lr
|
||||
;
|
||||
; V6T2-LABEL: mm_no_unsigned_sat_incorrect_constant2:
|
||||
; V6T2: @ %bb.0: @ %entry
|
||||
; V6T2-NEXT: bic r1, r0, r0, asr #31
|
||||
; V6T2-NEXT: movw r0, #1
|
||||
; V6T2-NEXT: movt r0, #128
|
||||
; V6T2-NEXT: cmp r1, #8388608
|
||||
; V6T2-NEXT: movls r0, r1
|
||||
; V6T2-NEXT: bx lr
|
||||
entry:
|
||||
%0 = call i32 @llvm.smax.i32(i32 %x, i32 0)
|
||||
%1 = call i32 @llvm.umin.i32(i32 %0, i32 8388609)
|
||||
ret i32 %1
|
||||
}
|
||||
|
||||
define i32 @mm_no_unsigned_sat_incorrect_interval(i32 %x) {
|
||||
; V4T-LABEL: mm_no_unsigned_sat_incorrect_interval:
|
||||
; V4T: @ %bb.0: @ %entry
|
||||
; V4T-NEXT: ldr r1, .LCPI25_0
|
||||
; V4T-NEXT: cmn r0, #4
|
||||
; V4T-NEXT: mvnle r0, #3
|
||||
; V4T-NEXT: cmp r0, r1
|
||||
; V4T-NEXT: movge r0, r1
|
||||
; V4T-NEXT: bx lr
|
||||
; V4T-NEXT: .p2align 2
|
||||
; V4T-NEXT: @ %bb.1:
|
||||
; V4T-NEXT: .LCPI25_0:
|
||||
; V4T-NEXT: .long 8388607 @ 0x7fffff
|
||||
;
|
||||
; V6-LABEL: mm_no_unsigned_sat_incorrect_interval:
|
||||
; V6: @ %bb.0: @ %entry
|
||||
; V6-NEXT: ldr r1, .LCPI25_0
|
||||
; V6-NEXT: cmn r0, #4
|
||||
; V6-NEXT: mvnle r0, #3
|
||||
; V6-NEXT: cmp r0, r1
|
||||
; V6-NEXT: movge r0, r1
|
||||
; V6-NEXT: bx lr
|
||||
; V6-NEXT: .p2align 2
|
||||
; V6-NEXT: @ %bb.1:
|
||||
; V6-NEXT: .LCPI25_0:
|
||||
; V6-NEXT: .long 8388607 @ 0x7fffff
|
||||
;
|
||||
; V6T2-LABEL: mm_no_unsigned_sat_incorrect_interval:
|
||||
; V6T2: @ %bb.0: @ %entry
|
||||
; V6T2-NEXT: cmn r0, #4
|
||||
; V6T2-NEXT: movw r1, #65535
|
||||
; V6T2-NEXT: mvnle r0, #3
|
||||
; V6T2-NEXT: movt r1, #127
|
||||
; V6T2-NEXT: cmp r0, r1
|
||||
; V6T2-NEXT: movge r0, r1
|
||||
; V6T2-NEXT: bx lr
|
||||
entry:
|
||||
%0 = call i32 @llvm.smax.i32(i32 %x, i32 -4)
|
||||
%1 = call i32 @llvm.smin.i32(i32 %0, i32 8388607)
|
||||
ret i32 %1
|
||||
}
|
||||
|
||||
declare i32 @llvm.smin.i32(i32, i32)
|
||||
declare i32 @llvm.smax.i32(i32, i32)
|
||||
declare i16 @llvm.smin.i16(i16, i16)
|
||||
declare i16 @llvm.smax.i16(i16, i16)
|
||||
declare i8 @llvm.smin.i8(i8, i8)
|
||||
declare i8 @llvm.smax.i8(i8, i8)
|
||||
declare i32 @llvm.umin.i32(i32, i32)
|
||||
|
|
|
|||
Loading…
Reference in a new issue