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[RISCV] Fix incorrect codegen introduced by D119688.

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We should not emit a tail agnostic vlse for a tail undisturbed vmv.s.x

In D119688:
-    if (IsScalarMove && !Node->getOperand(0).isUndef())
+    bool HasPassthruOperand = Node->getOpcode() != ISD::SPLAT_VECTOR;
+    if (HasPassthruOperand && !IsScalarMove &&
!Node->getOperand(0).isUndef())
       break;

The IsScalarMove check in the if statement had been changed.

Differential Revision: https://reviews.llvm.org/D120963
This commit is contained in:
Zakk Chen 2022-03-03 19:44:46 -08:00
parent 3de970718c
commit 33b61c5678
2 changed files with 4 additions and 3 deletions
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2
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
View file

@ -1633,7 +1633,7 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
bool IsScalarMove = Node->getOpcode() == RISCVISD::VMV_S_X_VL ||
Node->getOpcode() == RISCVISD::VFMV_S_F_VL;
bool HasPassthruOperand = Node->getOpcode() != ISD::SPLAT_VECTOR;
if (HasPassthruOperand && !IsScalarMove && !Node->getOperand(0).isUndef())
if (HasPassthruOperand && !Node->getOperand(0).isUndef())
break;
SDValue Src = HasPassthruOperand ? Node->getOperand(1) : Node->getOperand(0);
auto *Ld = dyn_cast<LoadSDNode>(Src);

5
llvm/test/CodeGen/RISCV/rvv/vmv.s.x-rv64.ll
View file

@ -291,8 +291,9 @@ entry:
define <vscale x 1 x i64> @intrinsic_vmv.s.x_x_nxv1i64_bug(<vscale x 1 x i64> %0, i64* %1) nounwind {
; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv1i64_bug:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; CHECK-NEXT: vlse64.v v8, (a0), zero
; CHECK-NEXT: ld a0, 0(a0)
; CHECK-NEXT: vsetivli zero, 1, e64, m1, tu, mu
; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: ret
entry:
%a = load i64, i64* %1, align 8