[NFC][Codegen] Harden a few tests to not rely that volatile store to null isn't erased
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@ -4,7 +4,7 @@
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; Long branch is assumed because the block has a higher alignment
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; requirement than the function.
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define i32 @invert_bcc_block_align_higher_func(i32 %x, i32 %y) align 4 #0 {
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define i32 @invert_bcc_block_align_higher_func(i32 %x, i32 %y, i32* %dst) align 4 #0 {
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; CHECK-LABEL: invert_bcc_block_align_higher_func:
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; CHECK: ; %bb.0: ; %common.ret
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; CHECK-NEXT: cmp w0, w1
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@ -12,17 +12,17 @@ define i32 @invert_bcc_block_align_higher_func(i32 %x, i32 %y) align 4 #0 {
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; CHECK-NEXT: mov w9, #42
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; CHECK-NEXT: cset w0, ne
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; CHECK-NEXT: csel w8, w9, w8, eq
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; CHECK-NEXT: str w8, [x8]
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; CHECK-NEXT: str w8, [x2]
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; CHECK-NEXT: ret
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%1 = icmp eq i32 %x, %y
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br i1 %1, label %bb1, label %bb2
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bb2:
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store volatile i32 9, i32* undef
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store volatile i32 9, i32* %dst
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ret i32 1
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bb1:
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store volatile i32 42, i32* undef
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store volatile i32 42, i32* %dst
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ret i32 0
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}
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@ -1,27 +1,28 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=aarch64-apple-darwin -aarch64-bcc-offset-bits=3 < %s | FileCheck %s
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define i32 @invert_bcc(float %x, float %y) #0 {
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define i32 @invert_bcc(float %x, float %y, i32* %dst0, i32* %dst1) #0 {
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; CHECK-LABEL: invert_bcc:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: mov w0, wzr
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; CHECK-NEXT: fcmp s0, s1
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; CHECK-NEXT: mov w8, #42
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; CHECK-NEXT: b.pl LBB0_3
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; CHECK-NEXT: b.ne LBB0_3
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; CHECK-NEXT: b LBB0_2
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; CHECK-NEXT: LBB0_3:
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; CHECK-NEXT: b.gt LBB0_2
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; CHECK-NEXT: ; %bb.1: ; %common.ret
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; CHECK-NEXT: str w8, [x8]
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; CHECK-NEXT: ret
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; CHECK-NEXT: LBB0_2: ; %bb2
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; CHECK-NEXT: mov w0, #1
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; CHECK-NEXT: b.vc LBB0_1
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; CHECK-NEXT: b LBB0_2
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; CHECK-NEXT: LBB0_1: ; %bb2
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; CHECK-NEXT: mov w8, #9
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; CHECK-NEXT: ; InlineAsm Start
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; CHECK-NEXT: nop
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; CHECK-NEXT: nop
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; CHECK-NEXT: ; InlineAsm End
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; CHECK-NEXT: str w8, [x8]
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; CHECK-NEXT: str w8, [x0]
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; CHECK-NEXT: mov w0, #1
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; CHECK-NEXT: ret
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; CHECK-NEXT: LBB0_2: ; %bb1
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; CHECK-NEXT: mov w0, wzr
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; CHECK-NEXT: mov w8, #42
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; CHECK-NEXT: str w8, [x1]
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; CHECK-NEXT: ret
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%1 = fcmp ueq float %x, %y
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br i1 %1, label %bb1, label %bb2
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@ -31,11 +32,11 @@ bb2:
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"nop
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nop",
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""() #0
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store volatile i32 9, i32* undef
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store volatile i32 9, i32* %dst0
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ret i32 1
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bb1:
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store volatile i32 42, i32* undef
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store volatile i32 42, i32* %dst1
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ret i32 0
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}
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@ -16,18 +16,18 @@ entry:
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; CHECK: mul i32
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; CHECK-NOT: call i32
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define amdgpu_kernel void @caller(i32 %x) {
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define amdgpu_kernel void @caller(i32 %x, i32 addrspace(1)* %dst) {
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entry:
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%res = call i32 @callee(i32 %x)
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store volatile i32 %res, i32 addrspace(1)* undef
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store volatile i32 %res, i32 addrspace(1)* %dst
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ret void
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}
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; CHECK-LABEL: @alias_caller(
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; CHECK-NOT: call
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define amdgpu_kernel void @alias_caller(i32 %x) {
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define amdgpu_kernel void @alias_caller(i32 %x, i32 addrspace(1)* %dst) {
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entry:
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%res = call i32 @c_alias(i32 %x)
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store volatile i32 %res, i32 addrspace(1)* undef
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store volatile i32 %res, i32 addrspace(1)* %dst
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ret void
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}
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