[X86] Disable combineVectorSizedSetCCEquality for soft float.
The vector types aren't legal with soft float. Also disable under NoImplicitFloat for good measure. Fixes PR56351. Differential Revision: https://reviews.llvm.org/D129060
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@ -51654,9 +51654,13 @@ static SDValue combineVectorSizedSetCCEquality(SDNode *SetCC, SelectionDAG &DAG,
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// Use XOR (plus OR) and PTEST after SSE4.1 for 128/256-bit operands.
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// Use PCMPNEQ (plus OR) and KORTEST for 512-bit operands.
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// Otherwise use PCMPEQ (plus AND) and mask testing.
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if ((OpSize == 128 && Subtarget.hasSSE2()) ||
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(OpSize == 256 && Subtarget.hasAVX()) ||
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(OpSize == 512 && Subtarget.useAVX512Regs())) {
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bool NoImplicitFloatOps =
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DAG.getMachineFunction().getFunction().hasFnAttribute(
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Attribute::NoImplicitFloat);
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if (!Subtarget.useSoftFloat() && !NoImplicitFloatOps &&
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((OpSize == 128 && Subtarget.hasSSE2()) ||
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(OpSize == 256 && Subtarget.hasAVX()) ||
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(OpSize == 512 && Subtarget.useAVX512Regs()))) {
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bool HasPT = Subtarget.hasSSE41();
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// PTEST and MOVMSK are slow on Knights Landing and Knights Mill and widened
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18
llvm/test/CodeGen/X86/pr56351.ll
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18
llvm/test/CodeGen/X86/pr56351.ll
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@ -0,0 +1,18 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mattr=+soft-float | FileCheck %s
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define i1 @foo(i128* %x, i128* %y) {
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; CHECK-LABEL: foo:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movq (%rdi), %rax
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; CHECK-NEXT: movq 8(%rdi), %rcx
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; CHECK-NEXT: xorq 8(%rsi), %rcx
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; CHECK-NEXT: xorq (%rsi), %rax
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; CHECK-NEXT: orq %rcx, %rax
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; CHECK-NEXT: sete %al
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; CHECK-NEXT: retq
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%a = load i128, i128* %x, align 16
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%b = load i128, i128* %y, align 16
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%c = icmp eq i128 %a, %b
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ret i1 %c
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}
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