[AMDGPU] Handle legacy multiply-accumulate opcodes in convertToThreeAddress
Handle V_MAC_LEGACY_F32 and V_FMAC_LEGACY_F32 in convertToThreeAddress, to avoid the need for an extra mov instruction in some cases. Differential Revision: https://reviews.llvm.org/D120704
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@ -3246,9 +3246,15 @@ MachineInstr *SIInstrInfo::convertToThreeAddress(MachineInstr &MI,
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bool IsF16 = Opc == AMDGPU::V_MAC_F16_e32 || Opc == AMDGPU::V_MAC_F16_e64 ||
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Opc == AMDGPU::V_FMAC_F16_e32 || Opc == AMDGPU::V_FMAC_F16_e64;
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bool IsFMA = Opc == AMDGPU::V_FMAC_F32_e32 || Opc == AMDGPU::V_FMAC_F32_e64 ||
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Opc == AMDGPU::V_FMAC_LEGACY_F32_e32 ||
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Opc == AMDGPU::V_FMAC_LEGACY_F32_e64 ||
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Opc == AMDGPU::V_FMAC_F16_e32 || Opc == AMDGPU::V_FMAC_F16_e64 ||
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Opc == AMDGPU::V_FMAC_F64_e32 || Opc == AMDGPU::V_FMAC_F64_e64;
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bool IsF64 = Opc == AMDGPU::V_FMAC_F64_e32 || Opc == AMDGPU::V_FMAC_F64_e64;
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bool IsLegacy = Opc == AMDGPU::V_MAC_LEGACY_F32_e32 ||
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Opc == AMDGPU::V_MAC_LEGACY_F32_e64 ||
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Opc == AMDGPU::V_FMAC_LEGACY_F32_e32 ||
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Opc == AMDGPU::V_FMAC_LEGACY_F32_e64;
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switch (Opc) {
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default:
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@ -3256,13 +3262,17 @@ MachineInstr *SIInstrInfo::convertToThreeAddress(MachineInstr &MI,
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case AMDGPU::V_MAC_F16_e64:
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case AMDGPU::V_FMAC_F16_e64:
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case AMDGPU::V_MAC_F32_e64:
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case AMDGPU::V_MAC_LEGACY_F32_e64:
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case AMDGPU::V_FMAC_F32_e64:
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case AMDGPU::V_FMAC_LEGACY_F32_e64:
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case AMDGPU::V_FMAC_F64_e64:
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break;
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case AMDGPU::V_MAC_F16_e32:
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case AMDGPU::V_FMAC_F16_e32:
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case AMDGPU::V_MAC_F32_e32:
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case AMDGPU::V_MAC_LEGACY_F32_e32:
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case AMDGPU::V_FMAC_F32_e32:
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case AMDGPU::V_FMAC_LEGACY_F32_e32:
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case AMDGPU::V_FMAC_F64_e32: {
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int Src0Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
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AMDGPU::OpName::src0);
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@ -3292,6 +3302,7 @@ MachineInstr *SIInstrInfo::convertToThreeAddress(MachineInstr &MI,
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const MachineOperand *Omod = getNamedOperand(MI, AMDGPU::OpName::omod);
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if (!Src0Mods && !Src1Mods && !Src2Mods && !Clamp && !Omod && !IsF64 &&
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!IsLegacy &&
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// If we have an SGPR input, we will violate the constant bus restriction.
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(ST.getConstantBusLimit(Opc) > 1 || !Src0->isReg() ||
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!RI.isSGPRReg(MBB.getParent()->getRegInfo(), Src0->getReg()))) {
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@ -3361,10 +3372,14 @@ MachineInstr *SIInstrInfo::convertToThreeAddress(MachineInstr &MI,
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}
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}
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unsigned NewOpc = IsFMA ? (IsF16 ? AMDGPU::V_FMA_F16_gfx9_e64
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: IsF64 ? AMDGPU::V_FMA_F64_e64
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: AMDGPU::V_FMA_F32_e64)
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: (IsF16 ? AMDGPU::V_MAD_F16_e64 : AMDGPU::V_MAD_F32_e64);
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unsigned NewOpc = IsFMA ? IsF16 ? AMDGPU::V_FMA_F16_gfx9_e64
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: IsF64 ? AMDGPU::V_FMA_F64_e64
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: IsLegacy
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? AMDGPU::V_FMA_LEGACY_F32_e64
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: AMDGPU::V_FMA_F32_e64
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: IsF16 ? AMDGPU::V_MAD_F16_e64
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: IsLegacy ? AMDGPU::V_MAD_LEGACY_F32_e64
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: AMDGPU::V_MAD_F32_e64;
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if (pseudoToMCOpcode(NewOpc) == -1)
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return nullptr;
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@ -272,8 +272,7 @@ define float @v_mad_legacy_f32(float %a, float %b, float %c) #2 {
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; GFX6-LABEL: v_mad_legacy_f32:
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; GFX6: ; %bb.0:
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; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX6-NEXT: v_mac_legacy_f32_e32 v2, v0, v1
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; GFX6-NEXT: v_mov_b32_e32 v0, v2
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; GFX6-NEXT: v_mad_legacy_f32 v0, v0, v1, v2
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; GFX6-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX8-LABEL: v_mad_legacy_f32:
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@ -292,8 +291,7 @@ define float @v_mad_legacy_f32(float %a, float %b, float %c) #2 {
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; GFX101: ; %bb.0:
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; GFX101-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX101-NEXT: s_waitcnt_vscnt null, 0x0
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; GFX101-NEXT: v_mac_legacy_f32_e32 v2, v0, v1
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; GFX101-NEXT: v_mov_b32_e32 v0, v2
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; GFX101-NEXT: v_mad_legacy_f32 v0, v0, v1, v2
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; GFX101-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX103-LABEL: v_mad_legacy_f32:
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@ -7,8 +7,7 @@ define float @v_fma(float %a, float %b, float %c) {
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; GCN: ; %bb.0:
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; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GCN-NEXT: s_waitcnt_vscnt null, 0x0
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; GCN-NEXT: v_fmac_legacy_f32_e32 v2, v0, v1
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; GCN-NEXT: v_mov_b32_e32 v0, v2
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; GCN-NEXT: v_fma_legacy_f32 v0, v0, v1, v2
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; GCN-NEXT: s_setpc_b64 s[30:31]
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%fma = call float @llvm.amdgcn.fma.legacy(float %a, float %b, float %c)
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ret float %fma
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@ -65,10 +65,10 @@ define amdgpu_kernel void @test_mad_legacy_f32(float addrspace(1)* %out, float %
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}
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; GCN-LABEL: {{^}}test_mad_legacy_f32_imm:
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; GFX6: v_mac_legacy_f32_e32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}
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; GFX6: v_mad_legacy_f32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}
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; GFX8: v_mad_legacy_f32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}
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; GFX9: v_mad_legacy_f32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}
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; GFX101: v_mac_legacy_f32_e64 v{{[0-9]+}}, 0x41200000, s{{[0-9]+}}
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; GFX101: v_mad_legacy_f32 v{{[0-9]+}}, 0x41200000, s{{[0-9]+}}
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; GFX103: v_mul_legacy_f32_e64 v{{[0-9]+}}, 0x41200000, s{{[0-9]+}}
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; GFX103: v_add_f32_e32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}
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define amdgpu_kernel void @test_mad_legacy_f32_imm(float addrspace(1)* %out, float %a, float %c) #2 {
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