[RISCV] Supplement patterns for vnsrl.wx/vnsra.wx when splat shift is sext or zext
Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D122786
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@ -839,6 +839,22 @@ multiclass VPatWidenBinaryFPVL_VV_VF_WV_WF<SDNode op, string instruction_name> {
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defm : VPatWidenBinaryFPVL_WV_WF<op, riscv_fpextend_vl_oneuse, instruction_name>;
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}
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multiclass VPatNarrowShiftSplatExt_WX<SDNode op, PatFrags extop, string instruction_name> {
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foreach vti = AllWidenableIntVectors in {
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def : Pat<
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(vti.Vti.Vector
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(riscv_trunc_vector_vl
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(op (vti.Wti.Vector vti.Wti.RegClass:$rs2),
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(vti.Wti.Vector (extop (vti.Vti.Vector (SplatPat GPR:$rs1)),
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(vti.Vti.Mask true_mask), VLOpFrag)),
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(vti.Wti.Mask true_mask), VLOpFrag),
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(vti.Vti.Mask true_mask), VLOpFrag)),
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(!cast<Instruction>(instruction_name#"_WX_"#vti.Vti.LMul.MX)
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vti.Wti.RegClass:$rs2, GPR:$rs1,
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vti.Vti.AVL, vti.Vti.Log2SEW)>;
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}
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}
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//===----------------------------------------------------------------------===//
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// Patterns.
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//===----------------------------------------------------------------------===//
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@ -931,6 +947,8 @@ foreach vtiTowti = AllWidenableIntVectors in {
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true_mask, VLOpFrag)), true_mask, VLOpFrag)),
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(!cast<Instruction>("PseudoVNSRA_WX_"#vti.LMul.MX)
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wti.RegClass:$rs1, GPR:$rs2, GPR:$vl, vti.Log2SEW)>;
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defm : VPatNarrowShiftSplatExt_WX<riscv_sra_vl, riscv_sext_vl_oneuse, "PseudoVNSRA">;
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defm : VPatNarrowShiftSplatExt_WX<riscv_sra_vl, riscv_zext_vl_oneuse, "PseudoVNSRA">;
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def : Pat<(vti.Vector
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(riscv_trunc_vector_vl
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(wti.Vector
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@ -938,7 +956,6 @@ foreach vtiTowti = AllWidenableIntVectors in {
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true_mask, VLOpFrag)), true_mask, VLOpFrag)),
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(!cast<Instruction>("PseudoVNSRA_WI_"#vti.LMul.MX)
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wti.RegClass:$rs1, uimm5:$rs2, GPR:$vl, vti.Log2SEW)>;
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def : Pat<(vti.Vector
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(riscv_trunc_vector_vl
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(wti.Vector
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@ -946,6 +963,8 @@ foreach vtiTowti = AllWidenableIntVectors in {
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true_mask, VLOpFrag)), true_mask, VLOpFrag)),
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(!cast<Instruction>("PseudoVNSRL_WX_"#vti.LMul.MX)
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wti.RegClass:$rs1, GPR:$rs2, GPR:$vl, vti.Log2SEW)>;
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defm : VPatNarrowShiftSplatExt_WX<riscv_srl_vl, riscv_sext_vl_oneuse, "PseudoVNSRL">;
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defm : VPatNarrowShiftSplatExt_WX<riscv_srl_vl, riscv_zext_vl_oneuse, "PseudoVNSRL">;
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def : Pat<(vti.Vector
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(riscv_trunc_vector_vl
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(wti.Vector
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@ -15,6 +15,34 @@ define <8 x i8> @vnsra_v8i16_v8i8_scalar(<8 x i16> %x, i16 %y) {
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ret <8 x i8> %b
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}
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define <8 x i8> @vnsra_v8i16_v8i8_scalar_sext(<8 x i16> %x, i8 %y) {
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; CHECK-LABEL: vnsra_v8i16_v8i8_scalar_sext:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, mu
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; CHECK-NEXT: vnsra.wx v8, v8, a0
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; CHECK-NEXT: ret
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%insert = insertelement <8 x i8> poison, i8 %y, i8 0
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%splat = shufflevector <8 x i8> %insert, <8 x i8> poison, <8 x i32> zeroinitializer
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%sext = sext <8 x i8> %splat to <8 x i16>
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%a = ashr <8 x i16> %x, %sext
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%b = trunc <8 x i16> %a to <8 x i8>
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ret <8 x i8> %b
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}
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define <8 x i8> @vnsra_v8i16_v8i8_scalar_zext(<8 x i16> %x, i8 %y) {
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; CHECK-LABEL: vnsra_v8i16_v8i8_scalar_zext:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, mu
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; CHECK-NEXT: vnsra.wx v8, v8, a0
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; CHECK-NEXT: ret
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%insert = insertelement <8 x i8> poison, i8 %y, i8 0
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%splat = shufflevector <8 x i8> %insert, <8 x i8> poison, <8 x i32> zeroinitializer
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%zext = zext <8 x i8> %splat to <8 x i16>
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%a = ashr <8 x i16> %x, %zext
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%b = trunc <8 x i16> %a to <8 x i8>
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ret <8 x i8> %b
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}
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define <4 x i16> @vnsra_v4i32_v4i16_scalar(<4 x i32> %x, i32 %y) {
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; CHECK-LABEL: vnsra_v4i32_v4i16_scalar:
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; CHECK: # %bb.0:
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@ -28,6 +56,34 @@ define <4 x i16> @vnsra_v4i32_v4i16_scalar(<4 x i32> %x, i32 %y) {
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ret <4 x i16> %b
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}
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define <4 x i16> @vnsra_v4i32_v4i16_scalar_sext(<4 x i32> %x, i16 %y) {
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; CHECK-LABEL: vnsra_v4i32_v4i16_scalar_sext:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, mu
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; CHECK-NEXT: vnsra.wx v8, v8, a0
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; CHECK-NEXT: ret
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%insert = insertelement <4 x i16> poison, i16 %y, i16 0
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%splat = shufflevector <4 x i16> %insert, <4 x i16> poison, <4 x i32> zeroinitializer
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%sext = sext <4 x i16> %splat to <4 x i32>
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%a = ashr <4 x i32> %x, %sext
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%b = trunc <4 x i32> %a to <4 x i16>
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ret <4 x i16> %b
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}
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define <4 x i16> @vnsra_v4i32_v4i16_scalar_zext(<4 x i32> %x, i16 %y) {
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; CHECK-LABEL: vnsra_v4i32_v4i16_scalar_zext:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, mu
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; CHECK-NEXT: vnsra.wx v8, v8, a0
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; CHECK-NEXT: ret
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%insert = insertelement <4 x i16> poison, i16 %y, i16 0
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%splat = shufflevector <4 x i16> %insert, <4 x i16> poison, <4 x i32> zeroinitializer
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%zext = zext <4 x i16> %splat to <4 x i32>
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%a = ashr <4 x i32> %x, %zext
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%b = trunc <4 x i32> %a to <4 x i16>
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ret <4 x i16> %b
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}
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define <2 x i32> @vnsra_v2i64_v2i32_scalar(<2 x i64> %x, i64 %y) {
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; CHECK-LABEL: vnsra_v2i64_v2i32_scalar:
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; CHECK: # %bb.0:
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@ -41,6 +97,34 @@ define <2 x i32> @vnsra_v2i64_v2i32_scalar(<2 x i64> %x, i64 %y) {
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ret <2 x i32> %b
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}
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define <2 x i32> @vnsra_v2i64_v2i32_scalar_sext(<2 x i64> %x, i32 %y) {
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; CHECK-LABEL: vnsra_v2i64_v2i32_scalar_sext:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, mu
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; CHECK-NEXT: vnsra.wx v8, v8, a0
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; CHECK-NEXT: ret
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%insert = insertelement <2 x i32> poison, i32 %y, i32 0
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%splat = shufflevector <2 x i32> %insert, <2 x i32> poison, <2 x i32> zeroinitializer
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%sext = sext <2 x i32> %splat to <2 x i64>
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%a = ashr <2 x i64> %x, %sext
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%b = trunc <2 x i64> %a to <2 x i32>
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ret <2 x i32> %b
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}
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define <2 x i32> @vnsra_v2i64_v2i32_scalar_zext(<2 x i64> %x, i32 %y) {
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; CHECK-LABEL: vnsra_v2i64_v2i32_scalar_zext:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, mu
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; CHECK-NEXT: vnsra.wx v8, v8, a0
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; CHECK-NEXT: ret
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%insert = insertelement <2 x i32> poison, i32 %y, i32 0
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%splat = shufflevector <2 x i32> %insert, <2 x i32> poison, <2 x i32> zeroinitializer
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%zext = zext <2 x i32> %splat to <2 x i64>
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%a = ashr <2 x i64> %x, %zext
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%b = trunc <2 x i64> %a to <2 x i32>
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ret <2 x i32> %b
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}
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define <8 x i8> @vnsra_v8i16_v8i8_imm(<8 x i16> %x) {
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; CHECK-LABEL: vnsra_v8i16_v8i8_imm:
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; CHECK: # %bb.0:
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@ -87,6 +171,34 @@ define <8 x i8> @vnsrl_v8i16_v8i8_scalar(<8 x i16> %x, i16 %y) {
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ret <8 x i8> %b
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}
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define <8 x i8> @vnsrl_v8i16_v8i8_scalar_sext(<8 x i16> %x, i8 %y) {
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; CHECK-LABEL: vnsrl_v8i16_v8i8_scalar_sext:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, mu
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; CHECK-NEXT: vnsrl.wx v8, v8, a0
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; CHECK-NEXT: ret
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%insert = insertelement <8 x i8> poison, i8 %y, i16 0
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%splat = shufflevector <8 x i8> %insert, <8 x i8> poison, <8 x i32> zeroinitializer
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%sext = sext <8 x i8> %splat to <8 x i16>
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%a = lshr <8 x i16> %x, %sext
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%b = trunc <8 x i16> %a to <8 x i8>
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ret <8 x i8> %b
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}
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define <8 x i8> @vnsrl_v8i16_v8i8_scalar_zext(<8 x i16> %x, i8 %y) {
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; CHECK-LABEL: vnsrl_v8i16_v8i8_scalar_zext:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, mu
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; CHECK-NEXT: vnsrl.wx v8, v8, a0
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; CHECK-NEXT: ret
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%insert = insertelement <8 x i8> poison, i8 %y, i16 0
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%splat = shufflevector <8 x i8> %insert, <8 x i8> poison, <8 x i32> zeroinitializer
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%zext = zext <8 x i8> %splat to <8 x i16>
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%a = lshr <8 x i16> %x, %zext
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%b = trunc <8 x i16> %a to <8 x i8>
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ret <8 x i8> %b
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}
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define <4 x i16> @vnsrl_v4i32_v4i16_scalar(<4 x i32> %x, i32 %y) {
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; CHECK-LABEL: vnsrl_v4i32_v4i16_scalar:
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; CHECK: # %bb.0:
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ret <4 x i16> %b
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}
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define <4 x i16> @vnsrl_v4i32_v4i16_scalar_sext(<4 x i32> %x, i16 %y) {
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; CHECK-LABEL: vnsrl_v4i32_v4i16_scalar_sext:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, mu
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; CHECK-NEXT: vnsrl.wx v8, v8, a0
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; CHECK-NEXT: ret
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%insert = insertelement <4 x i16> poison, i16 %y, i16 0
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%splat = shufflevector <4 x i16> %insert, <4 x i16> poison, <4 x i32> zeroinitializer
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%sext = sext <4 x i16> %splat to <4 x i32>
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%a = lshr <4 x i32> %x, %sext
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%b = trunc <4 x i32> %a to <4 x i16>
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ret <4 x i16> %b
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}
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define <4 x i16> @vnsrl_v4i32_v4i16_scalar_zext(<4 x i32> %x, i16 %y) {
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; CHECK-LABEL: vnsrl_v4i32_v4i16_scalar_zext:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, mu
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; CHECK-NEXT: vnsrl.wx v8, v8, a0
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; CHECK-NEXT: ret
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%insert = insertelement <4 x i16> poison, i16 %y, i16 0
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%splat = shufflevector <4 x i16> %insert, <4 x i16> poison, <4 x i32> zeroinitializer
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%zext = zext <4 x i16> %splat to <4 x i32>
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%a = lshr <4 x i32> %x, %zext
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%b = trunc <4 x i32> %a to <4 x i16>
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ret <4 x i16> %b
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}
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define <2 x i32> @vnsrl_v2i64_v2i32_scalar(<2 x i64> %x, i64 %y) {
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; CHECK-LABEL: vnsrl_v2i64_v2i32_scalar:
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; CHECK: # %bb.0:
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ret <2 x i32> %b
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}
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define <2 x i32> @vnsrl_v2i64_v2i32_scalar_sext(<2 x i64> %x, i32 %y) {
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; CHECK-LABEL: vnsrl_v2i64_v2i32_scalar_sext:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, mu
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; CHECK-NEXT: vnsrl.wx v8, v8, a0
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; CHECK-NEXT: ret
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%insert = insertelement <2 x i32> poison, i32 %y, i32 0
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%splat = shufflevector <2 x i32> %insert, <2 x i32> poison, <2 x i32> zeroinitializer
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%sext = sext <2 x i32> %splat to <2 x i64>
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%a = lshr <2 x i64> %x, %sext
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%b = trunc <2 x i64> %a to <2 x i32>
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ret <2 x i32> %b
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}
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define <2 x i32> @vnsrl_v2i64_v2i32_scalar_zext(<2 x i64> %x, i32 %y) {
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; CHECK-LABEL: vnsrl_v2i64_v2i32_scalar_zext:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, mu
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; CHECK-NEXT: vnsrl.wx v8, v8, a0
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; CHECK-NEXT: ret
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%insert = insertelement <2 x i32> poison, i32 %y, i32 0
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%splat = shufflevector <2 x i32> %insert, <2 x i32> poison, <2 x i32> zeroinitializer
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%zext = zext <2 x i32> %splat to <2 x i64>
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%a = lshr <2 x i64> %x, %zext
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%b = trunc <2 x i64> %a to <2 x i32>
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ret <2 x i32> %b
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}
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define <8 x i8> @vnsrl_v8i16_v8i8_imm(<8 x i16> %x) {
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; CHECK-LABEL: vnsrl_v8i16_v8i8_imm:
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; CHECK: # %bb.0:
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