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[RISCV] Make getInstSeqCost handle other Zb* instructions.

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We haven't been updating this as Zb* instructions have been used
for immediate materialization. They will hit the default case and
trigger an llvm_unreachable. Instead of trying to list them all,
assume instructions that aren't explicitly listed aren't compressible.

Spotted while looking at integer materialization for other reasons.
I haven't seen a crash from this yet.
This commit is contained in:
Craig Topper 2022-04-20 22:00:10 -07:00
parent ce2257d69f
commit 186d5c8af5
1 changed files with 2 additions and 6 deletions
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8
llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp
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@ -18,10 +18,9 @@ static int getInstSeqCost(RISCVMatInt::InstSeq &Res, bool HasRVC) {
int Cost = 0;
for (auto Instr : Res) {
bool Compressed;
// Assume instructions that aren't listed aren't compressible.
bool Compressed = false;
switch (Instr.Opc) {
default:
llvm_unreachable("Unexpected opcode");
case RISCV::SLLI:
case RISCV::SRLI:
Compressed = true;
@ -31,9 +30,6 @@ static int getInstSeqCost(RISCVMatInt::InstSeq &Res, bool HasRVC) {
case RISCV::LUI:
Compressed = isInt<6>(Instr.Imm);
break;
case RISCV::ADD_UW:
Compressed = false;
break;
}
// Two RVC instructions take the same space as one RVI instruction, but
// can take longer to execute than the single RVI instruction. Thus, we