[ARM] Fix IT block generation after Thumb2SizeReduce with -Oz
Fixes a regression caused by D82439, in which IT blocks were no longer being generated when -Oz is present. This was due to the CPSR register being marked as dead, while this case was not accounted for. Differential Revision: https://reviews.llvm.org/D83667
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@ -587,6 +587,13 @@ bool ARMBaseInstrInfo::DefinesPredicate(
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const MachineOperand &MO = MI.getOperand(i);
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if ((MO.isRegMask() && MO.clobbersPhysReg(ARM::CPSR)) ||
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(MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)) {
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// Filter out T1 instructions that have a dead CPSR,
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// allowing IT blocks to be generated containing T1 instructions
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const MCInstrDesc &MCID = MI.getDesc();
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if (MCID.TSFlags & ARMII::ThumbArithFlagSetting && MO.isDead())
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continue;
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Pred.push_back(MO);
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Found = true;
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}
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@ -37,26 +37,25 @@ define i32 @test_values(i32 %a, i32 %b) minsize optsize {
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; CHECK-V7M: mov r2, r0
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; CHECK-V7M-NEXT: ldr r0, .LCPI0_0
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; CHECK-V7M-NEXT: cmp r2, #50
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; CHECK-V7M-NEXT: beq .LBB0_5
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; CHECK-V7M-NEXT: beq .LBB0_3
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; CHECK-V7M-NEXT: cmp r2, #1
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; CHECK-V7M-NEXT: beq .LBB0_7
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; CHECK-V7M-NEXT: ittt eq
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; CHECK-V7M-NEXT: addeq r0, r1
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; CHECK-V7M-NEXT: addeq r0, #1
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; CHECK-V7M-NEXT: bxeq lr
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; CHECK-V7M-NEXT: cmp r2, #30
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; CHECK-V7M-NEXT: beq .LBB0_8
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; CHECK-V7M-NEXT: cbnz r2, .LBB0_6
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; CHECK-V7M-NEXT: ittt eq
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; CHECK-V7M-NEXT: addeq r0, r1
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; CHECK-V7M-NEXT: addeq r0, #2
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; CHECK-V7M-NEXT: bxeq lr
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; CHECK-V7M-NEXT: cbnz r2, .LBB0_4
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; CHECK-V7M-NEXT: .LBB0_2:
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; CHECK-V7M-NEXT: add r0, r1
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; CHECK-V7M-NEXT: bx lr
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; CHECK-V7M-NEXT: .LBB0_5:
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; CHECK-V7M-NEXT: .LBB0_3:
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; CHECK-V7M-NEXT: add r0, r1
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; CHECK-V7M-NEXT: adds r0, #4
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; CHECK-V7M-NEXT: .LBB0_6:
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; CHECK-V7M-NEXT: bx lr
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; CHECK-V7M-NEXT: .LBB0_7:
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; CHECK-V7M-NEXT: add r0, r1
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; CHECK-V7M-NEXT: adds r0, #1
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; CHECK-V7M-NEXT: bx lr
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; CHECK-V7M-NEXT: .LBB0_8:
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; CHECK-V7M-NEXT: add r0, r1
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; CHECK-V7M-NEXT: adds r0, #2
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; CHECK-V7M-NEXT: .LBB0_4:
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; CHECK-V7M-NEXT: bx lr
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; CHECK-V7M-NEXT: .p2align 2
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; CHECK-V7M-NEXT: .LCPI0_0:
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