[AArch64] Lowering and legalization of strict FP16
For strict FP16 to work correctly needs some changes in lowering and legalization: * SelectionDAGLegalize::PromoteNode was missing handling for some strict fp opcodes. * Some of the custom lowering of strict fp operations needed to be adjusted to work with FP16. * Custom lowering needed to be added for round-to-int operations. With this, and the previous patches for the rest of the strict fp isel, we can set IsStrictFPEnabled = true. Differential Revision: https://reviews.llvm.org/D115620
This commit is contained in:
John Brawn
parent
d43d9e1d5c
commit
12c1022679
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@ -4714,6 +4714,12 @@ void SelectionDAGLegalize::PromoteNode(SDNode *Node) {
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Results.push_back(DAG.getNode(ISD::FP_ROUND, dl, OVT,
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Tmp3, DAG.getIntPtrConstant(0, dl)));
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break;
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case ISD::STRICT_FADD:
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case ISD::STRICT_FSUB:
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case ISD::STRICT_FMUL:
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case ISD::STRICT_FDIV:
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case ISD::STRICT_FMINNUM:
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case ISD::STRICT_FMAXNUM:
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case ISD::STRICT_FREM:
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case ISD::STRICT_FPOW:
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Tmp1 = DAG.getNode(ISD::STRICT_FP_EXTEND, dl, {NVT, MVT::Other},
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@ -4738,6 +4744,22 @@ void SelectionDAGLegalize::PromoteNode(SDNode *Node) {
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DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2, Tmp3),
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DAG.getIntPtrConstant(0, dl)));
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break;
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case ISD::STRICT_FMA:
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Tmp1 = DAG.getNode(ISD::STRICT_FP_EXTEND, dl, {NVT, MVT::Other},
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{Node->getOperand(0), Node->getOperand(1)});
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Tmp2 = DAG.getNode(ISD::STRICT_FP_EXTEND, dl, {NVT, MVT::Other},
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{Node->getOperand(0), Node->getOperand(2)});
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Tmp3 = DAG.getNode(ISD::STRICT_FP_EXTEND, dl, {NVT, MVT::Other},
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{Node->getOperand(0), Node->getOperand(3)});
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Tmp4 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Tmp1.getValue(1),
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Tmp2.getValue(1), Tmp3.getValue(1));
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Tmp4 = DAG.getNode(Node->getOpcode(), dl, {NVT, MVT::Other},
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{Tmp4, Tmp1, Tmp2, Tmp3});
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Tmp4 = DAG.getNode(ISD::STRICT_FP_ROUND, dl, {OVT, MVT::Other},
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{Tmp4.getValue(1), Tmp4, DAG.getIntPtrConstant(0, dl)});
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Results.push_back(Tmp4);
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Results.push_back(Tmp4.getValue(1));
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break;
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case ISD::FCOPYSIGN:
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case ISD::FPOWI: {
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Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0));
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@ -4754,6 +4776,16 @@ void SelectionDAGLegalize::PromoteNode(SDNode *Node) {
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Tmp3, DAG.getIntPtrConstant(isTrunc, dl)));
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break;
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}
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case ISD::STRICT_FPOWI:
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Tmp1 = DAG.getNode(ISD::STRICT_FP_EXTEND, dl, {NVT, MVT::Other},
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{Node->getOperand(0), Node->getOperand(1)});
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Tmp2 = DAG.getNode(Node->getOpcode(), dl, {NVT, MVT::Other},
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{Tmp1.getValue(1), Tmp1, Node->getOperand(2)});
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Tmp3 = DAG.getNode(ISD::STRICT_FP_ROUND, dl, {OVT, MVT::Other},
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{Tmp2.getValue(1), Tmp2, DAG.getIntPtrConstant(0, dl)});
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Results.push_back(Tmp3);
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Results.push_back(Tmp3.getValue(1));
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break;
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case ISD::FFLOOR:
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case ISD::FCEIL:
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case ISD::FRINT:
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@ -4778,12 +4810,19 @@ void SelectionDAGLegalize::PromoteNode(SDNode *Node) {
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break;
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case ISD::STRICT_FFLOOR:
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case ISD::STRICT_FCEIL:
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case ISD::STRICT_FRINT:
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case ISD::STRICT_FNEARBYINT:
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case ISD::STRICT_FROUND:
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case ISD::STRICT_FROUNDEVEN:
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case ISD::STRICT_FTRUNC:
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case ISD::STRICT_FSQRT:
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case ISD::STRICT_FSIN:
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case ISD::STRICT_FCOS:
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case ISD::STRICT_FLOG:
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case ISD::STRICT_FLOG2:
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case ISD::STRICT_FLOG10:
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case ISD::STRICT_FEXP:
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case ISD::STRICT_FEXP2:
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Tmp1 = DAG.getNode(ISD::STRICT_FP_EXTEND, dl, {NVT, MVT::Other},
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{Node->getOperand(0), Node->getOperand(1)});
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Tmp2 = DAG.getNode(Node->getOpcode(), dl, {NVT, MVT::Other},
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@ -539,64 +539,41 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
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else
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setOperationAction(ISD::FCOPYSIGN, MVT::f16, Promote);
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setOperationAction(ISD::FREM, MVT::f16, Promote);
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setOperationAction(ISD::FREM, MVT::v4f16, Expand);
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setOperationAction(ISD::FREM, MVT::v8f16, Expand);
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setOperationAction(ISD::FPOW, MVT::f16, Promote);
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setOperationAction(ISD::FPOW, MVT::v4f16, Expand);
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setOperationAction(ISD::FPOW, MVT::v8f16, Expand);
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setOperationAction(ISD::FPOWI, MVT::f16, Promote);
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setOperationAction(ISD::FPOWI, MVT::v4f16, Expand);
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setOperationAction(ISD::FPOWI, MVT::v8f16, Expand);
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setOperationAction(ISD::FCOS, MVT::f16, Promote);
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setOperationAction(ISD::FCOS, MVT::v4f16, Expand);
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setOperationAction(ISD::FCOS, MVT::v8f16, Expand);
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setOperationAction(ISD::FSIN, MVT::f16, Promote);
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setOperationAction(ISD::FSIN, MVT::v4f16, Expand);
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setOperationAction(ISD::FSIN, MVT::v8f16, Expand);
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setOperationAction(ISD::FSINCOS, MVT::f16, Promote);
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setOperationAction(ISD::FSINCOS, MVT::v4f16, Expand);
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setOperationAction(ISD::FSINCOS, MVT::v8f16, Expand);
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setOperationAction(ISD::FEXP, MVT::f16, Promote);
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setOperationAction(ISD::FEXP, MVT::v4f16, Expand);
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setOperationAction(ISD::FEXP, MVT::v8f16, Expand);
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setOperationAction(ISD::FEXP2, MVT::f16, Promote);
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setOperationAction(ISD::FEXP2, MVT::v4f16, Expand);
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setOperationAction(ISD::FEXP2, MVT::v8f16, Expand);
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setOperationAction(ISD::FLOG, MVT::f16, Promote);
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setOperationAction(ISD::FLOG, MVT::v4f16, Expand);
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setOperationAction(ISD::FLOG, MVT::v8f16, Expand);
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setOperationAction(ISD::FLOG2, MVT::f16, Promote);
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setOperationAction(ISD::FLOG2, MVT::v4f16, Expand);
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setOperationAction(ISD::FLOG2, MVT::v8f16, Expand);
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setOperationAction(ISD::FLOG10, MVT::f16, Promote);
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setOperationAction(ISD::FLOG10, MVT::v4f16, Expand);
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setOperationAction(ISD::FLOG10, MVT::v8f16, Expand);
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for (auto Op : {ISD::FREM, ISD::FPOW, ISD::FPOWI,
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ISD::FCOS, ISD::FSIN, ISD::FSINCOS,
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ISD::FEXP, ISD::FEXP2, ISD::FLOG,
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ISD::FLOG2, ISD::FLOG10, ISD::STRICT_FREM,
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ISD::STRICT_FPOW, ISD::STRICT_FPOWI, ISD::STRICT_FCOS,
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ISD::STRICT_FSIN, ISD::STRICT_FEXP, ISD::STRICT_FEXP2,
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ISD::STRICT_FLOG, ISD::STRICT_FLOG2, ISD::STRICT_FLOG10}) {
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setOperationAction(Op, MVT::f16, Promote);
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setOperationAction(Op, MVT::v4f16, Expand);
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setOperationAction(Op, MVT::v8f16, Expand);
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}
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if (!Subtarget->hasFullFP16()) {
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setOperationAction(ISD::SELECT, MVT::f16, Promote);
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setOperationAction(ISD::SELECT_CC, MVT::f16, Promote);
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setOperationAction(ISD::SETCC, MVT::f16, Promote);
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setOperationAction(ISD::BR_CC, MVT::f16, Promote);
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setOperationAction(ISD::FADD, MVT::f16, Promote);
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setOperationAction(ISD::FSUB, MVT::f16, Promote);
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setOperationAction(ISD::FMUL, MVT::f16, Promote);
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setOperationAction(ISD::FDIV, MVT::f16, Promote);
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setOperationAction(ISD::FMA, MVT::f16, Promote);
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setOperationAction(ISD::FNEG, MVT::f16, Promote);
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setOperationAction(ISD::FABS, MVT::f16, Promote);
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setOperationAction(ISD::FCEIL, MVT::f16, Promote);
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setOperationAction(ISD::FSQRT, MVT::f16, Promote);
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setOperationAction(ISD::FFLOOR, MVT::f16, Promote);
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setOperationAction(ISD::FNEARBYINT, MVT::f16, Promote);
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setOperationAction(ISD::FRINT, MVT::f16, Promote);
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setOperationAction(ISD::FROUND, MVT::f16, Promote);
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setOperationAction(ISD::FROUNDEVEN, MVT::f16, Promote);
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setOperationAction(ISD::FTRUNC, MVT::f16, Promote);
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setOperationAction(ISD::FMINNUM, MVT::f16, Promote);
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setOperationAction(ISD::FMAXNUM, MVT::f16, Promote);
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setOperationAction(ISD::FMINIMUM, MVT::f16, Promote);
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setOperationAction(ISD::FMAXIMUM, MVT::f16, Promote);
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for (auto Op :
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{ISD::SELECT, ISD::SELECT_CC, ISD::SETCC,
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ISD::BR_CC, ISD::FADD, ISD::FSUB,
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ISD::FMUL, ISD::FDIV, ISD::FMA,
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ISD::FNEG, ISD::FABS, ISD::FCEIL,
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ISD::FSQRT, ISD::FFLOOR, ISD::FNEARBYINT,
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ISD::FRINT, ISD::FROUND, ISD::FROUNDEVEN,
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ISD::FTRUNC, ISD::FMINNUM, ISD::FMAXNUM,
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ISD::FMINIMUM, ISD::FMAXIMUM, ISD::STRICT_FADD,
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ISD::STRICT_FSUB, ISD::STRICT_FMUL, ISD::STRICT_FDIV,
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ISD::STRICT_FMA, ISD::STRICT_FCEIL, ISD::STRICT_FFLOOR,
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ISD::STRICT_FSQRT, ISD::STRICT_FRINT, ISD::STRICT_FNEARBYINT,
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ISD::STRICT_FROUND, ISD::STRICT_FTRUNC, ISD::STRICT_FROUNDEVEN,
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ISD::STRICT_FMINNUM, ISD::STRICT_FMAXNUM, ISD::STRICT_FMINIMUM,
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ISD::STRICT_FMAXIMUM})
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setOperationAction(Op, MVT::f16, Promote);
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// Round-to-integer need custom lowering for fp16, as Promote doesn't work
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// because the result type is integer.
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for (auto Op : {ISD::STRICT_LROUND, ISD::STRICT_LLROUND, ISD::STRICT_LRINT,
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ISD::STRICT_LLRINT})
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setOperationAction(Op, MVT::f16, Custom);
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// promote v4f16 to v4f32 when that is known to be safe.
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setOperationAction(ISD::FADD, MVT::v4f16, Promote);
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@ -1402,6 +1379,8 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
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}
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PredictableSelectIsExpensive = Subtarget->predictableSelectIsExpensive();
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IsStrictFPEnabled = true;
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}
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void AArch64TargetLowering::addTypeForNEON(MVT VT) {
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@ -2592,7 +2571,18 @@ static SDValue emitStrictFPComparison(SDValue LHS, SDValue RHS, const SDLoc &dl,
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bool IsSignaling) {
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EVT VT = LHS.getValueType();
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assert(VT != MVT::f128);
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assert(VT != MVT::f16 && "Lowering of strict fp16 not yet implemented");
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const bool FullFP16 =
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static_cast<const AArch64Subtarget &>(DAG.getSubtarget()).hasFullFP16();
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if (VT == MVT::f16 && !FullFP16) {
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LHS = DAG.getNode(ISD::STRICT_FP_EXTEND, dl, {MVT::f32, MVT::Other},
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{Chain, LHS});
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RHS = DAG.getNode(ISD::STRICT_FP_EXTEND, dl, {MVT::f32, MVT::Other},
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{LHS.getValue(1), RHS});
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Chain = RHS.getValue(1);
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VT = MVT::f32;
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}
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unsigned Opcode =
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IsSignaling ? AArch64ISD::STRICT_FCMPE : AArch64ISD::STRICT_FCMP;
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return DAG.getNode(Opcode, dl, {VT, MVT::Other}, {Chain, LHS, RHS});
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@ -3468,8 +3458,7 @@ SDValue AArch64TargetLowering::LowerVectorFP_TO_INT(SDValue Op,
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MVT::getVectorVT(MVT::getFloatingPointVT(VT.getScalarSizeInBits()),
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VT.getVectorNumElements());
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if (IsStrict) {
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SDValue Ext = DAG.getNode(ISD::STRICT_FP_EXTEND, dl,
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{ExtVT, MVT::Other},
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SDValue Ext = DAG.getNode(ISD::STRICT_FP_EXTEND, dl, {ExtVT, MVT::Other},
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{Op.getOperand(0), Op.getOperand(1)});
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return DAG.getNode(Op.getOpcode(), dl, {VT, MVT::Other},
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{Ext.getValue(1), Ext.getValue(0)});
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@ -3506,8 +3495,14 @@ SDValue AArch64TargetLowering::LowerFP_TO_INT(SDValue Op,
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// f16 conversions are promoted to f32 when full fp16 is not supported.
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if (SrcVal.getValueType() == MVT::f16 && !Subtarget->hasFullFP16()) {
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assert(!IsStrict && "Lowering of strict fp16 not yet implemented");
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SDLoc dl(Op);
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if (IsStrict) {
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SDValue Ext =
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DAG.getNode(ISD::STRICT_FP_EXTEND, dl, {MVT::f32, MVT::Other},
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{Op.getOperand(0), SrcVal});
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return DAG.getNode(Op.getOpcode(), dl, {Op.getValueType(), MVT::Other},
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{Ext.getValue(1), Ext.getValue(0)});
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}
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return DAG.getNode(
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Op.getOpcode(), dl, Op.getValueType(),
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DAG.getNode(ISD::FP_EXTEND, dl, MVT::f32, SrcVal));
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@ -3730,10 +3725,15 @@ SDValue AArch64TargetLowering::LowerINT_TO_FP(SDValue Op,
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SDValue SrcVal = Op.getOperand(IsStrict ? 1 : 0);
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// f16 conversions are promoted to f32 when full fp16 is not supported.
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if (Op.getValueType() == MVT::f16 &&
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!Subtarget->hasFullFP16()) {
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assert(!IsStrict && "Lowering of strict fp16 not yet implemented");
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if (Op.getValueType() == MVT::f16 && !Subtarget->hasFullFP16()) {
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SDLoc dl(Op);
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if (IsStrict) {
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SDValue Val = DAG.getNode(Op.getOpcode(), dl, {MVT::f32, MVT::Other},
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{Op.getOperand(0), SrcVal});
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return DAG.getNode(
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ISD::STRICT_FP_ROUND, dl, {MVT::f16, MVT::Other},
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{Val.getValue(1), Val.getValue(0), DAG.getIntPtrConstant(0, dl)});
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}
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return DAG.getNode(
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ISD::FP_ROUND, dl, MVT::f16,
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DAG.getNode(Op.getOpcode(), dl, MVT::f32, SrcVal),
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@ -5367,6 +5367,18 @@ SDValue AArch64TargetLowering::LowerOperation(SDValue Op,
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return LowerCTTZ(Op, DAG);
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case ISD::VECTOR_SPLICE:
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return LowerVECTOR_SPLICE(Op, DAG);
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case ISD::STRICT_LROUND:
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case ISD::STRICT_LLROUND:
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case ISD::STRICT_LRINT:
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case ISD::STRICT_LLRINT: {
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assert(Op.getOperand(1).getValueType() == MVT::f16 &&
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"Expected custom lowering of rounding operations only for f16");
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SDLoc DL(Op);
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SDValue Ext = DAG.getNode(ISD::STRICT_FP_EXTEND, DL, {MVT::f32, MVT::Other},
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{Op.getOperand(0), Op.getOperand(1)});
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return DAG.getNode(Op.getOpcode(), DL, {Op.getValueType(), MVT::Other},
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{Ext.getValue(1), Ext.getValue(0)});
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}
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}
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}
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1173
llvm/test/CodeGen/AArch64/fp-intrinsics-fp16.ll
Normal file
1173
llvm/test/CodeGen/AArch64/fp-intrinsics-fp16.ll
Normal file
File diff suppressed because it is too large
Load diff
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@ -1,5 +1,5 @@
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; RUN: llc -mtriple=aarch64-none-eabi %s -disable-strictnode-mutation -o - | FileCheck %s
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; RUN: llc -mtriple=aarch64-none-eabi -global-isel=true -global-isel-abort=2 -disable-strictnode-mutation %s -o - | FileCheck %s
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; RUN: llc -mtriple=aarch64-none-eabi %s -o - | FileCheck %s
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; RUN: llc -mtriple=aarch64-none-eabi -global-isel=true -global-isel-abort=2 %s -o - | FileCheck %s
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; Check that constrained fp intrinsics are correctly lowered.
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