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[RISCV] Add another test case showing failure to use remw when the RHS has been zero extended from less than i32. NFC

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This commit is contained in:
Craig Topper 2021-02-20 13:48:18 -08:00
parent 9a4b574dd6
commit 038bd14712
1 changed files with 12 additions and 0 deletions
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12
llvm/test/CodeGen/RISCV/rv64m-exhaustive-w-insts.ll
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@ -1123,6 +1123,18 @@ define signext i32 @sext_i32_remw_zext_sext_i16(i16 zeroext %0, i16 signext %1)
ret i32 %5
}
define signext i32 @sext_i32_remw_sext_zext_i16(i16 signext %a, i16 zeroext %b) nounwind {
; RV64IM-LABEL: sext_i32_remw_sext_zext_i16:
; RV64IM: # %bb.0:
; RV64IM-NEXT: rem a0, a0, a1
; RV64IM-NEXT: sext.w a0, a0
; RV64IM-NEXT: ret
%1 = sext i16 %a to i32
%2 = zext i16 %b to i32
%3 = srem i32 %1, %2
ret i32 %3
}
define i32 @aext_remuw_aext_aext(i32 %a, i32 %b) nounwind {
; RV64IM-LABEL: aext_remuw_aext_aext:
; RV64IM: # %bb.0: