feat: Add command to generate Verilog

Signed-off-by: Christoph Heiss <contact@christoph-heiss.at>

.gitignore

@@ -3,3 +3,4 @@ dist/
 *.o
 *.gtkw
 *.vcd
+*.v

pyproject.toml

@@ -13,6 +13,7 @@ amaranth = "^0.3"
 
 [tool.poetry.scripts]
 sim = "teuthida.sim:start"
+verilog = "teuthida.gen:gen_verilog"
 
 [build-system]
 requires = ["poetry-core>=1.0.0"]

teuthida/gen.py

@@ -0,0 +1,9 @@
+from amaranth.back import verilog
+from . import Cpu
+
+def gen_verilog():
+    cpu = Cpu()
+
+    with open('teuthida.v', 'w') as f:
+        f.write(verilog.convert(cpu))
+