refactor: Simplify some bool logic
Signed-off-by: Christoph Heiss <contact@christoph-heiss.at>
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66d5327af7
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@ -20,7 +20,7 @@ class Alu(Elaboratable):
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def elaborate(self, _):
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m = Module()
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with m.If(self.en == 1):
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with m.If(self.en):
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with m.Switch(self.op):
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with m.Case(AluOp.ADD):
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m.d.comb += self.out.eq(self.in1 + self.in2)
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@ -44,12 +44,14 @@ class RegisterFile(Elaboratable):
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self.out1 = Signal(xlen)
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self.out2 = Signal(xlen)
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self.dbgout = Signal(xlen)
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def elaborate(self, _):
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m = Module()
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with m.Switch(self.sel1):
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with m.Case(0):
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# TODO: Optimize away everywhere else
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# TODO: Optimize away in decoder
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m.d.comb += self.out1.eq(0)
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with m.Default():
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m.d.comb += self.out1.eq(self.regs[self.sel1 - 1])
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@ -60,8 +62,8 @@ class RegisterFile(Elaboratable):
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with m.Default():
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m.d.comb += self.out2.eq(self.regs[self.sel2 - 1])
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with m.If(self.wren == 1):
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# TODO: Eliminate need for checking for x0
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with m.If(self.wren):
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# TODO: Optimize x0 check away in decoder
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with m.If((self.wrsel > 0) & (self.wrsel < 31)):
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m.d.comb += self.regs[self.wrsel - 1].eq(self.wrval)
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@ -247,7 +249,7 @@ class Cpu(Elaboratable):
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regs = m.submodules.regs = RegisterFile()
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dec = m.submodules.dec = InstructionDecoder(alu, regs)
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with m.If(self.halt == 0):
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with m.If(~self.halt):
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with m.Switch(self.stage):
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with m.Case(PipelineStage.FETCH):
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m.d.comb += [
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