commit 0ca5b8c12eb64a567ff873adf709e1f4a29cad89 Author: Christoph Heiss Date: Fri Mar 25 14:22:53 2022 +0100 Initial commit Signed-off-by: Christoph Heiss diff --git a/.editorconfig b/.editorconfig new file mode 100644 index 0000000..f6da06d --- /dev/null +++ b/.editorconfig @@ -0,0 +1,9 @@ +root = true + +[*] +end_of_line = lf +insert_final_newline = true +charset = utf-8 +indent_style = space +indent_size = 4 +trim_trailing_whitespace = true diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..1be5bdb --- /dev/null +++ b/.gitignore @@ -0,0 +1,2 @@ +__pycache__/ +dist/ diff --git a/poetry.lock b/poetry.lock new file mode 100644 index 0000000..18a918e --- /dev/null +++ b/poetry.lock @@ -0,0 +1,141 @@ +[[package]] +name = "amaranth" +version = "0.3" +description = "Amaranth hardware definition language" +category = "main" +optional = false +python-versions = "~=3.6" + +[package.dependencies] +importlib-resources = {version = "*", markers = "python_version < \"3.9\""} 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"teuthida.sim:start" + +[build-system] +requires = ["poetry-core>=1.0.0"] +build-backend = "poetry.core.masonry.api" diff --git a/teuthida/sim.py b/teuthida/sim.py new file mode 100644 index 0000000..be15edb --- /dev/null +++ b/teuthida/sim.py @@ -0,0 +1,13 @@ +from amaranth import * +from nmigen.back.pysim import Simulator, Delay, Settle + +def process(): + yield + +def start(): + m = Module() + sim = Simulator(m) + sim.add_clock(1e-6) # 1 MHz + sim.add_process(process) + + sim.run()